CN112542187B - Circuit for reading ID and chip state at high speed and flash memory - Google Patents
Circuit for reading ID and chip state at high speed and flash memory Download PDFInfo
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- CN112542187B CN112542187B CN202011632894.8A CN202011632894A CN112542187B CN 112542187 B CN112542187 B CN 112542187B CN 202011632894 A CN202011632894 A CN 202011632894A CN 112542187 B CN112542187 B CN 112542187B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1036—Read-write modes for single port memories, i.e. having either a random port or a serial port using data shift registers
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Abstract
The invention discloses a circuit for reading ID and chip state at high speed and a flash memory, wherein 8-bit judgment logic is generated by combining a low 7-bit interface and an SPI interface of a shift register of an instruction generation circuit and is respectively used for generating an instruction for reading a chip ID or a state register, the instruction is simultaneously provided for an output shift register of a data output circuit, the value of the output chip ID or the state register is selected to be sent to a D end of the output shift register according to the instruction for reading the chip ID or the state register, and finally the instruction is output through the shift register; the combinational logic behind the Q end of the output shift register is put to the D end of the output shift register to be executed, so that the circuit can output data one clock cycle earlier than a general read instruction of a flash memory, the combinational logic of IO ports is reduced, and the reading speed is improved.
Description
Technical Field
The invention relates to the technical field of flash memories, in particular to a circuit for reading ID and chip states at high speed and a flash memory.
Background
As shown in fig. 1 (CK is not shown, and all is connected to SPI clock clk), at present, the circuit for reading chip ID and reading status register outputs chip ID code and status when receiving operation command, and because it has no address and idle status, in the conventional design, its highest supportable reading speed does not reach the speed of general reading command of flash memory, thereby restricting the data transmission speed of flash memory.
Therefore, the prior art still needs to be improved and developed.
Disclosure of Invention
The invention aims to provide a circuit for reading ID and chip state at high speed and a flash memory, and aims to solve the problem that the reading speed of the existing circuit for reading the ID and the state register of the chip does not reach the speed of a general reading instruction of the flash memory, and the transmission speed of flash data is restricted.
The technical scheme of the invention is as follows: a circuit for reading ID and chip status at high speed, comprising:
the instruction generating circuit is used for generating an instruction for reading the chip ID or the status register and comprises a shift register;
the data output circuit is used for outputting the chip ID or the numerical value of the state register according to the chip ID reading instruction or the state register reading instruction generated by the instruction generating circuit and comprises an output shift register;
the instruction generating circuit is connected with the data output circuit: the low 7 bits of the shift register and the SPI interface are combined to generate 8 bits of judgment logic which is respectively used for generating an instruction for reading the chip ID or the state register and simultaneously providing the instruction for the output shift register, and the output shift register outputs the instruction by selecting the value of the output chip ID or the state register to the D end of the output shift register according to the instruction for reading the chip ID or the state register and finally outputting the instruction through the shift register.
The circuit for reading the ID and the chip state at high speed comprises a command generating circuit, a data strobe control data _ SEL, a first selector, a second selector, a third shift register, a fourth selector and a fourth shift register, wherein a B end of the first selector is connected with command data cmd, an SEL end of the first selector is connected with the data strobe control data _ SEL, an A end of the first selector is connected with a Q end of the first shift register, a Y end of the first selector is connected with a D end of the first shift register, and the Q end of the first shift register is connected with the B end of the second selector; the SEL end of the second selector is connected with the data strobe control data _ SEL, the A end of the second selector is connected with the Q end of the second shift register, the Y end of the second selector is connected with the D end of the second shift register, and the Q end of the second shift register is connected with the B end of the third selector; the SEL end of the third selector is connected with the data strobe control data _ SEL, the A end of the third selector is connected with the Q end of the third shift register, the Y end of the third selector is connected with the D end of the third shift register, and the Q end of the third shift register is connected with the B end of the fourth selector; the SEL end of the fourth selector is connected with the data strobe control data _ SEL, the A end of the fourth selector is connected with the Q end of the fourth shift register, and the Y end of the fourth selector is connected with the D end of the fourth shift register; and the Y end of the first selector, the Y end of the second selector, the Y end of the third selector and the Y end of the fourth selector are connected together to generate combinational logic of reading the chip ID or the instruction of reading the state register, and the combinational logic is transmitted to the data output circuit.
The circuit for reading ID and chip state at high speed is characterized in that the first selector, the second selector, the third selector and the fourth selector adopt an alternative data selector.
The circuit for reading the ID and the chip state at high speed adopts a D trigger as the first shift register, the second shift register, the third shift register and the fourth shift register.
The circuit for reading the ID and the chip state at high speed is characterized in that the data output circuit comprises a fifth selector, a sixth selector, a seventh selector, an eighth selector, a ninth selector, a first output shift register, a tenth selector, a second output shift register, an eleventh selector, a third output shift register, a twelfth selector and a fourth output shift register, the data of the state register is input to the A end of the fifth selector, the chip ID is input to the B end of the fifth selector, the combinational logic is input to the SEL end of the fifth selector, and the Y end of the fifth selector is connected with the A end of the twelfth selector; the A end of the sixth selector inputs data of the status register, the B end of the sixth selector inputs chip ID, the SEL end of the sixth selector inputs combinational logic, and the Y end of the sixth selector is connected with the A end of the eleventh selector; the A end of the seventh selector inputs data of the status register, the B end of the seventh selector inputs chip ID, the SEL end of the seventh selector inputs combinational logic, and the Y end of the seventh selector is connected with the A end of the tenth selector; the A end of the eighth selector inputs data of the status register, the B end of the eighth selector inputs chip ID, the SEL end of the eighth selector inputs combinational logic, and the Y end of the eighth selector is connected with the A end of the ninth selector; the B terminal of the ninth selector is connected to 1' B0, the SEL terminal of the ninth selector is connected to the output data strobe control data _ out _ SEL, the Y terminal of the ninth selector is connected to the D terminal of the first output shift register, the Q terminal of the first output shift register is connected to the B terminal of the tenth selector, the SEL terminal of the tenth selector is connected to the output data strobe control data _ out _ SEL, the Y terminal of the tenth selector is connected to the D terminal of the second output shift register, the Q terminal of the second output shift register is connected to the B terminal of the eleventh selector, the SEL terminal of the eleventh selector is connected to the output data strobe control data _ out _ SEL, the Y terminal of the eleventh selector is connected to the D terminal of the third output shift register, the Q terminal of the third output shift register is connected to the B terminal of the twelfth selector, the SEL terminal of the twelfth selector is connected to the output data strobe control data _ out _ SEL, and the Y terminal of the twelfth selector is connected to the D terminal of the fourth output shift register, the Q terminal of the fourth output shift register outputs data.
In the circuit for reading ID and chip state at high speed, the fifth selector, the sixth selector, the seventh selector and the eighth selector adopt one-out-of-two data selectors.
In the circuit for reading ID and chip state at high speed, the ninth selector, the tenth selector, the eleventh selector, the twelfth selector and the fourth output shift register adopt one-out-of-two data selectors.
In the circuit for reading the ID and the chip state at high speed, the first output shift register, the second output shift register, the third output shift register and the fourth output shift register adopt D triggers.
A flash memory comprising a circuit for reading ID and chip status at high speed as described in any of the above.
The invention has the beneficial effects that: the invention provides a circuit for reading ID and chip state at high speed and a flash memory, 8-bit judgment logic is generated by combining a low-order 7-bit interface and an SPI interface of a shift register of an instruction generating circuit and is respectively used for generating an instruction for reading the ID or the state register of a chip, the instruction is simultaneously provided for an output shift register of a data output circuit, the ID or the value of the state register of the output chip is selected to the D end of the output shift register according to the instruction for reading the ID or the state register of the chip, and finally the instruction is output through the shift register; the combinational logic behind the Q end of the output shift register is put to the D end of the output shift register to be executed, so that the circuit can output data one clock cycle earlier than a general read instruction of a flash memory, the combinational logic of IO ports is reduced, and the reading speed is improved.
Drawings
FIG. 1 is a schematic diagram of a prior art circuit for reading ID and chip status.
FIG. 2 is a schematic diagram of a circuit for reading ID and chip status at high speed in the present invention.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
As shown in fig. 2 (CK not shown, clock clk connected all to SPI), a circuit for reading ID and chip status at high speed, comprising:
an instruction generating circuit 1 for generating an instruction to read a chip ID or read a status register, including a shift register;
the data output circuit 2 is used for outputting the chip ID or the numerical value of the state register according to the instruction of the read chip ID or the read state register generated by the instruction generating circuit 1 and comprises an output shift register;
the instruction generating circuit 1 and the data output circuit 2 are connected: the low 7 bits of the shift register and an SPI interface (indicating a serial peripheral interface) are combined to generate 8 bits of judgment logic which is respectively used for generating an instruction for reading the chip ID or the state register and simultaneously providing the instruction to the output shift register, the value of the output chip ID or the state register is selected to the D end of the output shift register according to the instruction for reading the chip ID or the state register, and finally the output is carried out through the shift register.
In some embodiments, the instruction generating circuit 1 includes a first selector, a first shift register, a second selector, a second shift register, a third selector, a third shift register, a fourth selector, and a fourth shift register, where a terminal B of the first selector is connected to instruction data cmd (i.e., instruction data received by the SPI interface), a terminal SEL of the first selector is connected to data strobe control data _ SEL, a terminal a of the first selector is connected to a terminal Q of the first shift register, a terminal Y of the first selector is connected to a terminal D of the first shift register, and a terminal Q of the first shift register is connected to a terminal B of the second selector; the SEL end of the second selector is connected with the data strobe control data _ SEL, the A end of the second selector is connected with the Q end of the second shift register, the Y end of the second selector is connected with the D end of the second shift register, and the Q end of the second shift register is connected with the B end of the third selector; the SEL end of the third selector is connected with the data strobe control data _ SEL, the A end of the third selector is connected with the Q end of the third shift register, the Y end of the third selector is connected with the D end of the third shift register, and the Q end of the third shift register is connected with the B end of the fourth selector; the SEL end of the fourth selector is connected with the data strobe control data _ SEL, the A end of the fourth selector is connected with the Q end of the fourth shift register, and the Y end of the fourth selector is connected with the D end of the fourth shift register; the Y terminal of the first selector, the Y terminal of the second selector, the Y terminal of the third selector, and the Y terminal of the fourth selector are connected together to generate a combinational logic of an instruction for reading a chip ID or a read status register, and the combinational logic is transmitted to the data output circuit 2.
In some embodiments, the first selector, the second selector, the third selector, and the fourth selector are alternative data selectors.
In some embodiments, the first shift register, the second shift register, the third shift register and the fourth shift register employ D flip-flops.
In some specific embodiments, the data output circuit 2 includes a fifth selector, a sixth selector, a seventh selector, an eighth selector, a ninth selector, a first output shift register, a tenth selector, a second output shift register, an eleventh selector, a third output shift register, a twelfth selector, and a fourth output shift register, the a terminal of the fifth selector inputs the data of the status register, the B terminal of the fifth selector inputs the chip ID, the SEL terminal of the fifth selector inputs the combinational logic, and the Y terminal of the fifth selector is connected to the a terminal of the twelfth selector; the A end of the sixth selector inputs data of the status register, the B end of the sixth selector inputs chip ID, the SEL end of the sixth selector inputs combinational logic, and the Y end of the sixth selector is connected with the A end of the eleventh selector; the A end of the seventh selector inputs data of the status register, the B end of the seventh selector inputs chip ID, the SEL end of the seventh selector inputs combinational logic, and the Y end of the seventh selector is connected with the A end of the tenth selector; the A end of the eighth selector inputs data of the status register, the B end of the eighth selector inputs chip ID, the SEL end of the eighth selector inputs combinational logic, and the Y end of the eighth selector is connected with the A end of the ninth selector; the B terminal of the ninth selector is connected to 1' B0 (meaning that the last bit complement of the output shift register is 0), the SEL terminal of the ninth selector is connected to the output data strobe control data _ out _ SEL, the Y terminal of the ninth selector is connected to the D terminal of the first output shift register, the Q terminal of the first output shift register is connected to the B terminal of the tenth selector, the SEL terminal of the tenth selector is connected to the output data strobe control data _ out _ SEL, the Y terminal of the tenth selector is connected to the D terminal of the second output shift register, the Q terminal of the second output shift register is connected to the B terminal of the eleventh selector, the SEL terminal of the eleventh selector is connected to the output data strobe control data _ out _ SEL, the Y terminal of the eleventh selector is connected to the D terminal of the third output shift register, the Q terminal of the third output shift register is connected to the B terminal of the twelfth selector, the SEL terminal of the twelfth selector is connected to the output data strobe control data _ out _ SEL, the Y end of the twelfth selector is connected with the D end of the fourth output shift register, and the Q end of the fourth output shift register outputs data.
In some embodiments, the fifth selector, the sixth selector, the seventh selector, and the eighth selector are alternative data selectors.
In some embodiments, the ninth selector, the tenth selector, the eleventh selector, the twelfth selector, and the fourth output shift register are one-out-of-two data selectors.
In some embodiments, the first output shift register, the second output shift register, the third output shift register and the fourth output shift register employ D flip-flops.
The technical scheme also protects a flash memory which comprises the circuit for reading the ID and the chip state at high speed.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.
In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (8)
1. A circuit for reading ID and chip status at high speed, comprising:
the instruction generating circuit is used for generating an instruction for reading the chip ID or the status register and comprises a shift register;
the data output circuit is used for outputting the chip ID or the numerical value of the state register according to the chip ID reading instruction or the state register reading instruction generated by the instruction generating circuit and comprises an output shift register;
the instruction generating circuit is connected with the data output circuit: the low 7 bits of the shift register and the SPI interface are combined to generate 8 bits of judgment logic which is respectively used for generating an instruction for reading the chip ID or the state register and simultaneously providing the instruction to the output shift register, the value of the output chip ID or the state register is selected to be sent to the D end of the output shift register according to the instruction for reading the chip ID or the state register, and finally the output is carried out through the shift register;
the instruction generating circuit comprises a first selector, a first shift register, a second selector, a second shift register, a third selector, a third shift register, a fourth selector and a fourth shift register, wherein the terminal B of the first selector is connected with instruction data cmd, the terminal SEL of the first selector is connected with data strobe control data _ SEL, the terminal A of the first selector is connected with the terminal Q of the first shift register, the terminal Y of the first selector is connected with the terminal D of the first shift register, and the terminal Q of the first shift register is connected with the terminal B of the second selector; the SEL end of the second selector is connected with the data strobe control data _ SEL, the A end of the second selector is connected with the Q end of the second shift register, the Y end of the second selector is connected with the D end of the second shift register, and the Q end of the second shift register is connected with the B end of the third selector; the SEL end of the third selector is connected with the data strobe control data _ SEL, the A end of the third selector is connected with the Q end of the third shift register, the Y end of the third selector is connected with the D end of the third shift register, and the Q end of the third shift register is connected with the B end of the fourth selector; the SEL end of the fourth selector is connected with the data strobe control data _ SEL, the A end of the fourth selector is connected with the Q end of the fourth shift register, and the Y end of the fourth selector is connected with the D end of the fourth shift register; and the Y end of the first selector, the Y end of the second selector, the Y end of the third selector and the Y end of the fourth selector are connected together to generate combinational logic of reading the chip ID or the instruction of reading the state register, and the combinational logic is transmitted to the data output circuit.
2. The circuit for reading ID and chip status at high speed according to claim 1, wherein the first selector, the second selector, the third selector, and the fourth selector are either one of data selectors.
3. The circuit for reading ID and chip status at high speed according to any of claims 1 or 2, wherein the first shift register, the second shift register, the third shift register and the fourth shift register employ D flip-flops.
4. The circuit for reading ID and chip status at high speed according to claim 1, wherein the data output circuit comprises a fifth selector, a sixth selector, a seventh selector, an eighth selector, a ninth selector, a first output shift register, a tenth selector, a second output shift register, an eleventh selector, a third output shift register, a twelfth selector and a fourth output shift register, the A terminal of the fifth selector inputs the data of the status register, the B terminal of the fifth selector inputs the chip ID, the SEL terminal of the fifth selector inputs the combinational logic, and the Y terminal of the fifth selector is connected to the A terminal of the twelfth selector; the A end of the sixth selector inputs data of the status register, the B end of the sixth selector inputs chip ID, the SEL end of the sixth selector inputs combinational logic, and the Y end of the sixth selector is connected with the A end of the eleventh selector; the A end of the seventh selector inputs data of the status register, the B end of the seventh selector inputs chip ID, the SEL end of the seventh selector inputs combinational logic, and the Y end of the seventh selector is connected with the A end of the tenth selector; the A end of the eighth selector inputs data of the status register, the B end of the eighth selector inputs chip ID, the SEL end of the eighth selector inputs combinational logic, and the Y end of the eighth selector is connected with the A end of the ninth selector; the B terminal of the ninth selector is connected to 1' B0, the SEL terminal of the ninth selector is connected to the output data strobe control data _ out _ SEL, the Y terminal of the ninth selector is connected to the D terminal of the first output shift register, the Q terminal of the first output shift register is connected to the B terminal of the tenth selector, the SEL terminal of the tenth selector is connected to the output data strobe control data _ out _ SEL, the Y terminal of the tenth selector is connected to the D terminal of the second output shift register, the Q terminal of the second output shift register is connected to the B terminal of the eleventh selector, the SEL terminal of the eleventh selector is connected to the output data strobe control data _ out _ SEL, the Y terminal of the eleventh selector is connected to the D terminal of the third output shift register, the Q terminal of the third output shift register is connected to the B terminal of the twelfth selector, the SEL terminal of the twelfth selector is connected to the output data strobe control data _ out _ SEL, and the Y terminal of the twelfth selector is connected to the D terminal of the fourth output shift register, the Q terminal of the fourth output shift register outputs data.
5. The circuit for reading ID and chip status at high speed according to claim 4, wherein the fifth selector, the sixth selector, the seventh selector, and the eighth selector are one-out-of-two data selectors.
6. The circuit for reading ID and chip status at high speed according to claim 4, wherein the ninth selector, the tenth selector, the eleventh selector, the twelfth selector and the fourth output shift register use one-out-of-two data selectors.
7. The circuit for reading ID and chip status at high speed according to claim 4, wherein said first output shift register, said second output shift register, said third output shift register and said fourth output shift register employ D flip-flops.
8. A flash memory comprising a circuit for reading ID and chip status at high speed as claimed in any one of claims 1 to 7.
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| KR20040093767A (en) * | 2003-04-30 | 2004-11-09 | 매그나칩 반도체 유한회사 | Serial interface circuit |
| US7538577B2 (en) * | 2005-06-29 | 2009-05-26 | Thomas Bollinger | System and method for configuring a field programmable gate array |
| JP5245617B2 (en) * | 2008-07-30 | 2013-07-24 | 富士通株式会社 | Register control circuit and register control method |
| CN106445879B (en) * | 2016-11-18 | 2018-03-23 | 南京火零信息科技有限公司 | A kind of SoC devices |
| CN106776467B (en) * | 2016-12-15 | 2020-04-28 | 中国电子科技集团公司第二十研究所 | SPI FLASH control chip for command receiving system |
| CN110673524B (en) * | 2019-09-27 | 2020-09-22 | 安凯(广州)微电子技术有限公司 | High-speed SPI master mode controller |
| CN111897749A (en) * | 2020-06-23 | 2020-11-06 | 中国船舶重工集团公司第七0七研究所 | Quad-SPI (Serial peripheral interface) controller and externally-extended FLASH communication control system and method |
| CN111506529B (en) * | 2020-06-30 | 2020-10-16 | 深圳市芯天下技术有限公司 | High-speed SPI instruction response circuit applied to FLASH |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105389270A (en) * | 2015-12-22 | 2016-03-09 | 上海爱信诺航芯电子科技有限公司 | System and device for improving instruction cache hit ratio of system-on-chip |
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Address after: 518000 Room 101, building 10, Dayun software Town, 8288 Longgang Avenue, he'ao community, Yuanshan street, Longgang District, Shenzhen City, Guangdong Province Applicant after: XTX Technology Inc. Address before: 518000, Guangdong province Shenzhen Longgang District Henggang street Longgang road 8288, Dayun software town tenth, 1 floor Applicant before: Paragon Technology (Shenzhen) Ltd. |
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| GR01 | Patent grant | ||
| GR01 | Patent grant |