CN111490019B - 一种集成电路结构及其制造方法 - Google Patents
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Abstract
本发明提供了一种集成电路结构及其制造方法,其利用在衬底中形成第一密封层以及在衬底上形成第二密封层,并使得所述第一密封层和第二密封层均为压应力,来抵消衬底的翘曲力。并且,第一密封层和第二密封层的无机填充料的填充比不同,以使得两者具有压应力差,能够保证衬底不翘曲的同时,保证第一密封层和第二密封层的结合力。
Description
技术领域
本发明涉及集成电路封装测试制造领域,具体涉及一种集成电路结构及其制造方法。
背景技术
现有的嵌入式半导体集成封装结构,往往是通过在衬底上形成凹槽来内嵌一芯片的形式,具体的可以参见图1。在图1中,衬底1是一个具有较大面积的衬底,其可以集成多种且多个芯片,以实现不同的集成电路封装功能,为了在衬底1中嵌入芯片,需要将芯片的中心位置设置一凹槽2来放置至少一个芯片。该方法虽然可以节省纵向空间,减薄封装体,但是随着后续封装工艺中的热效应加持,会使得所述衬底1的边缘朝向所述凹槽2的开口方向弯曲。如果叠置多个器件,其经历的热效应会更多,其弯曲也可能更厉害,从而导致衬底与封装层的剥离以及衬底的裂纹产生等问题。
发明内容
基于解决上述问题,本发明提供了一种集成电路结构,其包括:
衬底,其包括相对的第一表面和第二表面;所述第一表面上包括一凹槽以及围绕所述凹槽的多个连接件,所述衬底具有使得所述衬底的边缘朝向所述凹槽的开口方向弯曲的应力;
第一半导体芯片,设置于所述凹槽中;
第一密封层,填充所述凹槽并露出所述第一半导体芯片的焊盘,且所述第一密封层的上表面与所述第一表面齐平;
线路层,形成于所述上表面与所述第一表面上且电连接所述焊盘和所述多个连接件;
第二半导体芯片,倒装于所述线路层上;
第二密封层,密封所述第二半导体芯片且完全覆盖所述上表面和所述第一表面;
所述第一密封层具有第一压应力,所述第二密封层具有第二压应力,所述第一压应力的方向朝向所述凹槽的侧壁,并且第一压应力的压力值小于第二压应力的压力值。
其中,所述第一压应力的压力值与所述第二压应力的压力值之比为0.3-0.5;其中,所述第一压应力的压力值为0.3-0.7MPa,所述第二压应力的压力值为1-1.2MPa。
其中,所述第一密封层和第二密封层均包括有机塑封体和无机填充料,其中所述第二密封层中的无机填充料的重量百分比大于所述第一密封层中的无机填充料的重量百分比。
其中,所述多个连接件包括彼此连通的第一部分和第二部分,所述第一部分具有第一孔径且为在所述第一表面上的填充一导电材料的通孔,所述第二部分具有第二孔径且为在所述第二表面上的填充所述导电材料的凹陷,其中所述第一孔径小于所述第二孔径。
其中,还包括在所述第二表面上的未填充导电材料的其他凹陷,所述其他凹陷环绕在所述第二表面的边缘。
根据上述封装结构,本发明还提供了一种集成电路结构的制造方法,其包括:
(1)提供一衬底,所述衬底包括相对的第一表面和第二表面;
(2)在所述第一表面上形成一凹槽,在所述第二表面的边缘形成环形排列的多个凹陷;
(3)在所述凹槽中固定第一半导体芯片;
(4)在所述凹槽中填充满第一密封材料,并在第一温度下预固化所述第一密封材料形成半固化的第一密封层;
(5)研磨所述第一表面,使得所述第一半导体芯片的焊盘露出;
(6)在所述第一表面上形成多个通孔,所述多个通孔与所述多个凹陷的一部分连通以形成多个连接孔;
(7)在所述多个连接孔中填充导电材料形成多个连接件;
(8)在所述第一表面形成线路层,所述线路层电连接所述多个连接件和所述焊盘;
(9)在所述线路层上倒装第二半导体芯片;
(10)使用第二密封材料密封所述第二半导体芯片,同时使得所述第二密封材料覆盖所述第一表面以形成第二密封层;并在第二温度下同时固化所述第一密封层和第二密封层,以使得所述第一密封层具有第一压应力,所述第二密封层具有第二压应力,所述第一压应力的方向朝向所述凹槽的侧壁,并且第一压应力的压力值小于第二压应力的压力值。
其中,还包括步骤(11),在所述第二表面上形成钝化层,并经图案化露出所述多个连接件,然后植球并经回流焊工艺形成焊球。
其中,所述第一压应力的压力值与所述第二压应力的压力值之比为0.3-0.5;其中,所述第一压应力的压力值为0.3-0.7MPa,所述第二压应力的压力值为1-1.2MPa。
其中,所述第一密封层和第二密封层均包括有机塑封体和无机填充料,其中所述第二密封层中的无机填充料的重量百分比大于所述第一密封层中的无机填充料的重量百分比。
其中,所述第二温度大于所述第一温度;且在步骤(10)中,在第二温度下同时固化所述第一密封层和第二密封层的时候,其降温速度小于等于2℃/min。
本发明相对于现有技术的主要贡献有以下几点:
(1)采用具有不同重量百分比的有机填充料的密封材料实现第一密封层和第二密封层不同的应力值;
(2)采用较为缓慢的降温进行固化所述第一密封层和第二密封层,以在所述第一密封层和第二密封层中形成压应力;
(3)第一密封层和第二密封层的压应力叠加以抵消衬底的翘曲力,并且使得第一密封层形成在所述衬底中(即凹槽内),其压应力施加于凹槽侧壁,可以防止衬底中心位置的应力过大;
(4)第一密封层和第二密封层的应力均为压应力,且相差不大,可以防止第一和第二密封层界面处的应力过大,进而防止界面处的分层;
(5)在所述衬底的下表面形成多个凹陷可以缓冲衬底的边缘应力,以缓和衬底的应力不平衡问题,同时所述多个凹陷部分充当连接件,可以实现自对准且便于填充导电材料。
附图说明
图1为现有技术中的嵌入式衬底的剖视图;
图2为本发明的集成电路结构的剖视图;
图3为本发明的集成电路结构的俯视图;
图4-15为本发明的集成电路结构制造方法的流程示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚,下面将结合本公开实施例的附图,对本公开实施例的技术方案进行清楚、完整地描述。显然,所描述的实施例是本公开的一部分实施例,而不是全部的实施例。基于所描述的本公开的实施例,本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例,都属于本公开保护的范围。
除非另外定义,本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性,而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同,而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接,而是可以包括电性的连接,不管是直接的还是间接的。“上”、“下”、“左”、“右”等仅用于表示相对位置关系,当被描述对象的绝对位置改变后,则该相对位置关系也可能相应地改变。
下面将结合附图对根据本发明公开实施例的集成电路结构及其制造方法进行详细的描述。
参见图2和图3,该本发明的集成电路结构包括衬底10,所述衬底10为硅衬底、绝缘体上硅衬底或者是陶瓷衬底、玻璃衬底等比较硬质的衬底。本实施例中,所述衬底10为陶瓷衬底,其包括相对的第一表面11和第二表面12,所述衬底10的厚度为1-5mm。所述衬底10具有使得所述衬底10的边缘朝向所述凹槽13的开口方向弯曲的应力(在背景技术部分已经说明,在此不再详述)。
在所述衬底10的第一表面11的中心位置设置一凹槽13,所述凹槽13可以是长方形、正方形、多边形或者圆形等合适的形状,并且所述凹槽13通过开槽工艺形成,具有500-1000μm的深度。所述凹槽13可以容置至少一个半导体芯片,即第一半导体芯片14。
在所述凹槽13的周边具有多个连接件19,所述连接件19为倒T形结构,其包括彼此连通的第一部分和第二部分,所述第一部分具有第一孔径且为在所述第一表面11上的填充一导电材料的通孔18,所述第二部分具有第二孔径且为在所述第二表面上的填充所述导电材料的凹陷17,其中所述第一孔径小于所述第二孔径。参见图3,所述凹陷17为多个,其仅有部分被填充所述导电材料形成上述第二部分,而其他的凹陷17为未填充的,其设置的目的主要是为了缓冲衬底的边缘应力,以缓和衬底的应力不平衡问题。
所述第一半导体芯片14可以是高功率或发热元件,例如IGBT、HEMT、MOSFET等裸芯片,也可以是逻辑芯片、控制芯片、传输门芯片、整流芯片等封装芯片,其厚度大致为200-450μm。所述第一半导体芯片14可以通过粘合层将非有源面固定在所述凹槽13的底部。所述第一半导体芯片14的有源面具有多个焊盘15。
在所述凹槽13中填充有第一密封层16,所述第一密封层16的上表面与所述第一表面11齐平且露出所述焊盘15,其构成一平坦表面。
在所述第一表面11上具有线路层20,所述线路层20可以是图案化的金属层,例如铜层、铝层、银层等。所述线路层20可以根据实际需要合理设置其图案,所述线路层20至少将所述第一半导体芯片14的焊盘15电连接至所述连接件19,以实现背面引出。
在所述第一表面11上设置有倒装的第二半导体芯片21,所述第二半导体芯片21通过焊球22倒装于所述线路层20上。所述第二半导体芯片21可选为指纹芯片、图像传感器芯片、存储器芯片等,其可以为一个或多个,其可以是堆叠体或者是横向排列的多个芯片。
在第一表面11上设置有第二密封层23,所述第二密封层23密封所述第二半导体芯片21且完全覆盖所述第一表面11。该第二密封层23的厚度通常大于所述第一密封层16的厚度。
在所述第二表面上形成有钝化层24,并经图案化露出所述多个连接件19,多个焊球25电连接所述多个连接件19。
在本发明中,其最为重要的设计在于,使得所述第一密封层16具有第一压应力F1,所述第二密封层23具有第二压应力F2,所述第一压应力F1的方向朝向所述凹槽13的侧壁,并且第一压应力F1的压力值小于第二压应力F2的压力值。
其中,第一密封层16形成在所述衬底10中(即凹槽13内),其第一压应力F1施加于凹槽侧壁,可以防止衬底10中心位置的应力过大。该第一压应力F1的压力值不可以过大,优选为小于第二压应力F2的压力值,其是为了防止F1对衬底10施加较小面积的集中应力,以造成衬底10的损毁。
并且,第一密封层16和第二密封层23的压应力叠加以抵消衬底的翘曲力,这在图1中很明确的。且第一密封层16和第二密封层23的应力均为压应力,且相差不大,优选的所述第一压应力的压力值与所述第二压应力的压力值之比为0.3-0.5;其中,所述第一压应力的压力值为0.3-0.7MPa,所述第二压应力的压力值为1-1.2MPa,可以防止第一和第二密封层界面处的应力过大,进而防止界面处的分层。
为了实现上述第一密封层16具有第一压应力F1,所述第二密封层23具有第二压应力F2,所述第一密封层16和第二密封层23均包括有机塑封体和无机填充料,只是其无机填充料的重量百分比不同。所述有机塑封体为热固化材料,例如环氧树脂、聚酰亚胺等聚合物材料,所述无机填充料可以是氧化硅颗粒、氮化硅颗粒、氧化铝颗粒、碳化硅颗粒中的一种或几种。
其中所述第二密封层23中的无机填充料的重量百分比大于所述第一密封层16中的无机填充料的重量百分比,以此实现在相同的固化过程之后,所述第一密封层16的压应力小于所述第二密封层23的压应力,具体的固化过程将在下述内容具体说明。其中,所述第一密封层16中的无机填充料的重量百分比为1-5%,所述第二密封层23的无机填充料的重量百分比为7-15%。
为了得到上述集成电路结构,本发明还提供了一种集成电路结构的制造方法,其包括:(1)提供一衬底,所述衬底包括相对的第一表面和第二表面;
(2)在所述第一表面上形成一凹槽,在所述第二表面的边缘形成环形排列的多个凹陷;
(3)在所述凹槽中固定第一半导体芯片;
(4)在所述凹槽中填充满第一密封材料,并在第一温度下预固化所述第一密封材料形成半固化的第一密封层;
(5)研磨所述第一表面,使得所述第一半导体芯片的焊盘露出;
(6)在所述第一表面上形成多个通孔,所述多个通孔与所述多个凹陷的一部分连通以形成多个连接孔;
(7)在所述多个连接孔中填充导电材料形成多个连接件;
(8)在所述第一表面形成线路层,所述线路层电连接所述多个连接件和所述焊盘;
(9)在所述线路层上倒装第二半导体芯片;
(10)使用第二密封材料密封所述第二半导体芯片,同时使得所述第二密封材料覆盖所述第一表面以形成第二密封层;并在第二温度下同时固化所述第一密封层和第二密封层,以使得所述第一密封层具有第一压应力,所述第二密封层具有第二压应力,所述第一压应力的方向朝向所述凹槽的侧壁,并且第一压应力的压力值小于第二压应力的压力值;
(11)在所述第二表面上形成钝化层,并经图案化露出所述多个连接件,然后植球并经回流焊工艺形成焊球。
具体的,参见图4-15,其包括以下步骤:
参见图4,提供一衬底10,所述衬底10为陶瓷衬底,其包括相对的第一表面11和第二表面12,所述衬底10的厚度为1-5mm。
参见图5,对所述衬底10进行蚀刻开槽形成在第一表面11上的凹槽13,以及在第二表面12上的环绕所述凹槽13的多个凹陷17。形成凹槽13和凹陷17可以采用常规的湿法蚀刻、干法蚀刻、机械开槽、激光开槽等技术实现。所述凹槽的深度为500-1000μm。
参见图6,在所述凹槽13中固定第一半导体芯片14,所述第一半导体芯片14的有源面朝上,且该有源面具有多个焊盘15。在本发明中,第一半导体芯片14可以通过粘合层进行固定,常用的粘合层可以选自粘合胶带、导热胶等。
参见图7,在所述凹槽13中填充满第一密封材料,并在50℃左右的温度下预固化所述第一密封材料形成半固化的第一密封层16。预固化时间大致为10min左右,其将第一密封材料进行固化,但是其应力达不到本发明所需。其中,所述第一密封层16中的无机填充料的重量百分比为1-5%。
参见图8,通过研磨所述第一表面11以使得所述焊盘15露出,并且获得较为平坦的表面。
参见图9,在所述衬底10的上表面形成多个通孔18,该通孔18连通部分的凹陷17,并且该通孔18可以通过从背面的凹陷17处进行刻蚀得到,方便对准。该通孔18的孔径小于所述凹陷17的孔径。
参见图10,在所述通孔18和部分凹陷17中填充导电材料,例如铜等,以形成连接件19,该连接件19呈现倒T形。
参见图11,在所述第一表面11形成线路层20,所述线路层20电连接所述多个连接件19和所述焊盘15。所述线路层20可以通过化学镀等方法进行金属平铺后图案化形成,其可以为铜等材料。
参见图12,在所述线路层20上通过焊球22倒装第二半导体芯片21,其需要经过回流焊工艺。
参见图13,使用第二密封材料密封所述第二半导体芯片21,同时使得所述第二密封材料覆盖所述第一表面以形成第二密封层23;其中,所述第二密封层23的无机填充料的重量百分比为7-15%;并在80℃温度下同时固化所述第一密封层16和第二密封层23,以使得所述第一密封层16具有第一压应力F1,所述第二密封层具有第二压应力F2,所述第一压应力F1的方向朝向所述凹槽13的侧壁,并且第一压应力F1的压力值小于第二压应力F2的压力值。
固化过程是极为苛刻的,本发明人发现当降温曲线极为缓和时,即降温速度比较慢时,其应力值表现为压应力,且该压应力使得第一密封层16和第二密封层23足以抵消衬底10的热应力。在本发明中,将上述半成品放置于烘烤炉中,并经80℃左右的温度进行烘烤十分钟,然后进行降温至常温,该降温的降温速率应当小于等于2℃/min。在进行自然降温时,降温速度较快,其压应力极小,而在小于等于2℃/min其压应力适中且足以保证抵消翘曲力,以此获得所述第一压应力F1的压力值为0.3-0.7MPa,所述第二压应力F2的压力值为1-1.2MPa。
参见图14,在所述第二表面12上形成钝化层24。所述钝化层24为氧化硅、氮化硅等材料,其通过CVD等方法形成。
参见图15,图案化所述钝化层25露出所述多个连接件19的下底面,然后植球并经回流焊工艺形成焊球25。
本发明采用具有不同重量百分比的有机填充料的密封材料实现第一密封层和第二密封层不同的应力值;采用较为缓慢的降温进行固化所述第一密封层和第二密封层,以在所述第一密封层和第二密封层中形成压应力;第一密封层和第二密封层的压应力叠加以抵消衬底的翘曲力,并且使得第一密封层形成在所述衬底中(即凹槽内),其压应力施加于凹槽侧壁,可以防止衬底中心位置的应力过大;第一密封层和第二密封层的应力均为压应力,且相差不大,可以防止第一和第二密封层界面处的应力过大,进而防止界面处的分层;在所述衬底的下表面形成多个凹陷可以缓冲衬底的边缘应力,以缓和衬底的应力不平衡问题,同时所述多个凹陷部分充当连接件,可以实现自对准且便于填充导电材料。
最后应说明的是:显然,上述实施例仅仅是为清楚地说明本发明所作的举例,而并非对实施方式的限定。对于所属领域的普通技术人员来说,在上述说明的基础上还可以做出其它不同形式的变化或变动。这里无需也无法对所有的实施方式予以穷举。而由此所引申出的显而易见的变化或变动仍处于本发明的保护范围之中。
Claims (8)
1.一种集成电路结构,其包括:
衬底,其包括相对的第一表面和第二表面;所述第一表面上包括一凹槽以及围绕所述凹槽的多个连接件,所述衬底具有使得所述衬底的边缘朝向所述凹槽的开口方向弯曲的应力;
第一半导体芯片,设置于所述凹槽中;
第一密封层,填充所述凹槽并露出所述第一半导体芯片的焊盘,且所述第一密封层的上表面与所述第一表面齐平;
线路层,形成于所述上表面与所述第一表面上且电连接所述焊盘和所述多个连接件;
第二半导体芯片,倒装于所述线路层上;
第二密封层,密封所述第二半导体芯片且完全覆盖所述上表面和所述第一表面;
其特征在于,所述第一密封层具有第一压应力,所述第二密封层具有第二压应力,所述第一压应力的方向朝向所述凹槽的侧壁,并且第一压应力的压力值小于第二压应力的压力值;其中,所述第一压应力的压力值与所述第二压应力的压力值之比为0.3-0.5;其中,所述第一压应力的压力值为0.3-0.7MPa,所述第二压应力的压力值为1-1.2MPa。
2.根据权利要求1所述的集成电路结构,其特征在于:所述第一密封层和第二密封层均包括有机塑封体和无机填充料,其中所述第二密封层中的无机填充料的重量百分比大于所述第一密封层中的无机填充料的重量百分比。
3.根据权利要求1或2所述的集成电路结构,其特征在于:所述多个连接件包括彼此连通的第一部分和第二部分,所述第一部分具有第一孔径且为在所述第一表面上的填充一导电材料的通孔,所述第二部分具有第二孔径且为在所述第二表面上的填充所述导电材料的凹陷,其中所述第一孔径小于所述第二孔径。
4.根据权利要求3所述的集成电路结构,其特征在于:还包括在所述第二表面上的未填充导电材料的其他凹陷,所述其他凹陷环绕在所述第二表面的边缘。
5.一种集成电路结构的制造方法,其包括:
(1)提供一衬底,所述衬底包括相对的第一表面和第二表面;
(2)在所述第一表面上形成一凹槽,在所述第二表面的边缘形成环形排列的多个凹陷;
(3)在所述凹槽中固定第一半导体芯片;
(4)在所述凹槽中填充满第一密封材料,并在第一温度下预固化所述第一密封材料形成半固化的第一密封层;
(5)研磨所述第一表面,使得所述第一半导体芯片的焊盘露出;
(6)在所述第一表面上形成多个通孔,所述多个通孔与所述多个凹陷的一部分连通以形成多个连接孔;
(7)在所述多个连接孔中填充导电材料形成多个连接件;
(8)在所述第一表面形成线路层,所述线路层电连接所述多个连接件和所述焊盘;
(9)在所述线路层上倒装第二半导体芯片;
(10)使用第二密封材料密封所述第二半导体芯片,同时使得所述第二密封材料覆盖所述第一表面以形成第二密封层;并在第二温度下同时固化所述第一密封层和第二密封层,以使得所述第一密封层具有第一压应力,所述第二密封层具有第二压应力,所述第一压应力的方向朝向所述凹槽的侧壁,并且第一压应力的压力值小于第二压应力的压力值;其中,所述第一压应力的压力值与所述第二压应力的压力值之比为0.3-0.5;其中,所述第一压应力的压力值为0.3-0.7MPa,所述第二压应力的压力值为1-1.2MPa。
6.根据权利要求5所述的集成电路结构的制造方法,其特征在于:还包括步骤(11),在所述第二表面上形成钝化层,并经图案化露出所述多个连接件,然后植球并经回流焊工艺形成焊球。
7.根据权利要求5所述的集成电路结构的制造方法,其特征在于:所述第一密封层和第二密封层均包括有机塑封体和无机填充料,其中所述第二密封层中的无机填充料的重量百分比大于所述第一密封层中的无机填充料的重量百分比。
8.根据权利要求5所述的集成电路结构的制造方法,其特征在于:所述第二温度大于所述第一温度;且在步骤(10)中,在第二温度下同时固化所述第一密封层和第二密封层的时候,其降温速度小于等于2℃/min。
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