CN111446335A - Light emitting diode and preparation method thereof - Google Patents
Light emitting diode and preparation method thereof Download PDFInfo
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- CN111446335A CN111446335A CN202010211462.3A CN202010211462A CN111446335A CN 111446335 A CN111446335 A CN 111446335A CN 202010211462 A CN202010211462 A CN 202010211462A CN 111446335 A CN111446335 A CN 111446335A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/04—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
- H01L33/06—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/26—Materials of the light emitting region
- H01L33/30—Materials of the light emitting region containing only elements of group III and group V of the periodic system
- H01L33/32—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen
- H01L33/325—Materials of the light emitting region containing only elements of group III and group V of the periodic system containing nitrogen characterised by the doping materials
Abstract
The invention relates to the technical field of display, and discloses a light-emitting diode and a preparation method thereof, wherein the preparation method comprises the following steps: forming light emitting diode units distributed in an array on a substrate, wherein each light emitting diode unit comprises a buffer layer, an n-GaN layer, an MQV layer and a p-GaN layer along the direction departing from the substrate; forming a first metal layer on the light emitting diode unit, and patterning the first metal layer through a composition process to form a first metal pattern; and forming a side wall limiting structure in the partial region of the p-GaN layer by taking the first metal pattern as a mask. The LED prepared by the LED preparation method provided by the invention forms a side wall limiting structure at a local position in the p-GaN layer, and the side wall limiting structure can inhibit the side wall effect. The preparation method of the light-emitting diode not only can realize small current injection in a large-size light-emitting diode and avoid the side wall effect, but also can be compatible with the existing semiconductor process.
Description
Technical Field
The invention relates to the technical field of display, in particular to a light-emitting diode and a preparation method thereof.
Background
in recent years, Micro light-Emitting diodes (Micro L ED) have attracted much attention as a novel self-luminous display technology, and compared with liquid crystal displays (L i liquid crystal displays, L CDs), Micro L ED has a simpler structure, and as a self-luminous technology, Micro L ED is superior to L CDs in terms of display contrast, response speed, color gamut, viewing angle, and the like, and compared with Organic light-Emitting diodes (O L ED), Micro L ED has certain advantages in terms of brightness, efficiency, and lifetime.
in the prior Micro L ED display technology, the size of the L ED is relatively large (generally more than 30 um), and the current density of the L ED is 1-10A/cm 2to further reduce the injection current to reduce brightness and reduce power consumption to meet the brightness and power consumption requirements of most display products, the mainstream solution is to reduce the size of the L ED.
however, this solution has the following problems that 1. the reduction of the dimension of the L ED causes a significant dimensional effect, i.e. the current density of the L ED increases and the peak External Quantum Efficiency (EQE) decreases, 2.Micro L ED usually requires transfer from the original substrate to the target substrate, as exemplified by pick and place transfer method, the reduction of the dimension of the L ED reduces the precision and yield of the transfer method, further increasing the difficulty of mass transfer.
Disclosure of Invention
The invention discloses a light-emitting diode and a preparation method thereof, wherein the preparation method of the light-emitting diode not only can realize small current injection in a large-size light-emitting diode and avoid the side wall effect, but also can be compatible with the existing semiconductor process.
In order to achieve the purpose, the invention provides the following technical scheme:
A method for preparing a light-emitting diode comprises the following steps:
Forming light emitting diode units distributed in an array on a substrate, wherein each light emitting diode unit comprises a buffer layer, an n-GaN layer, an MQV layer and a p-GaN layer along the direction deviating from the substrate;
Forming a first metal layer on the light emitting diode unit, and patterning the first metal layer through a composition process to form a first metal pattern;
And forming a side wall limiting structure in the partial region of the p-GaN layer by taking the first metal pattern as a mask.
In the preparation method of the light-emitting diode, the light-emitting diode units distributed in an array mode are formed on the substrate, the first metal layer is formed on one side, away from the substrate, of the light-emitting diode units, the first metal pattern is formed through the composition process, the first metal pattern is used as a mask, and the side wall limiting structure is formed in the p-GaN layer.
The LED prepared by the LED preparation method provided by the invention forms a side wall limiting structure at a local position in the p-GaN layer, and the side wall limiting structure can inhibit the side wall effect.
Therefore, the preparation method of the light-emitting diode not only can realize small current injection in a large-size light-emitting diode and avoid the side wall effect, but also can be compatible with the existing semiconductor process.
Preferably, the method of forming the sidewall limiting structure comprises:
Implanting deep-level impurity ions into the p-GaN layer by using the first metal pattern as a mask through an ion implantation process to form an implanted region, and reducing the conductivity of the implanted region through an annealing process at 700-800 ℃; the deep level impurity ions are impurity level impurity ions which are about 1-1.7eV away from the conduction band bottom or the valence band top of the GaN.
Preferably, after reducing the conductivity of the implanted region, the method further comprises:
Removing the first metal pattern, and etching to the n-GaN layer along the direction of the p-GaN layer pointing to the substrate by a composition process outside the coverage of the injection region;
Forming a first insulating layer on the n-GaN layer, and forming a first via hole on the first insulating layer through a patterning process;
Forming a first electrode layer on the first insulating layer, and forming a first electrode pattern on the first electrode layer through a patterning process, wherein the first electrode pattern is connected with the n-GaN layer through the first via hole;
Forming a second insulating layer on the first electrode pattern, and forming a second via hole and a third via hole on the second insulating layer through a patterning process, wherein a vertical projection of the third via hole on the substrate covers a vertical projection of the first via hole on the substrate;
And forming a second electrode layer on the second insulating layer, wherein the second electrode layer is partially filled in the third via hole, and the second insulating layer is formed into a second electrode pattern through a composition process, and the second electrode pattern is connected with the p-GaN layer through the second via hole.
Preferably, when the second electrode layer is patterned to form the second electrode pattern, an annealing process needs to be performed in a nitrogen atmosphere, where the annealing condition is that the temperature is 500 ℃ and the duration is 30 min.
Preferably, the method of forming the sidewall limiting structure comprises:
And implanting Si ions into the partial region of the p-GaN layer by using the first metal pattern as a mask through an ion implantation process to form an n-type conductive region.
Preferably, after the n-type conductive region is formed, the method further includes:
Removing the first metal pattern, and forming an ohmic contact electrode ITO layer on the p-GaN layer;
Bonding a silicon wafer on the ITO layer by a bonding process;
Peeling off the substrate;
Removing the buffer layer;
Forming a second metal layer on the n-GaN layer, and patterning the second metal layer through a composition process to form a second metal pattern;
Injecting Mg ions into the partial region of the n-GaN layer by using the second metal pattern as a mask through an ion injection process to form a p-type conductive region;
Removing the second metal pattern, forming an insulating layer on the n-GaN layer, and forming a first via hole on the insulating layer through a composition process;
And forming a first electrode layer on the insulating layer, forming a first electrode pattern on the first electrode layer through a composition process, and connecting the first electrode pattern with the n-GaN layer through the first via hole.
Preferably, the preparation process for forming the first metal layer is one of a magnetron sputtering process, a thermal evaporation process, an electron beam evaporation process and an electroplating process.
Preferably, the patterning process for forming the first metal pattern is a photolithography process, an etching process and a photoresist removing process, wherein the etching process includes one of a wet etching process, a reactive ion etching process or an ion beam etching process.
Preferably, the patterning process for forming the light emitting diode units distributed in an array on the substrate includes a photolithography process, a reactive ion etching process, and a photoresist removing process.
The invention also provides a light-emitting diode which is prepared by adopting any one of the preparation methods of the light-emitting diode provided by the technical scheme.
Drawings
Fig. 1 is a schematic flow chart of a method for manufacturing a light emitting diode according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a film layer according to a first embodiment of the present invention;
FIG. 3 is a schematic view of a film layer according to a first embodiment of the present invention;
FIG. 4 is a schematic view of a first embodiment of the present invention;
FIG. 5 is a diagram illustrating a second embodiment of the present invention;
Fig. 6 is a schematic diagram of a film layer in a second embodiment of the invention.
Icon: 10-a substrate; 20-a buffer layer; a 30-n-GaN layer; a 301-p type conductivity region; a 40-MQV layer; a 50-p-GaN layer; 501-an injection region; a 502-n type conductive region; 60-a first metal pattern; 70-an insulating layer; 80-a first electrode pattern; 90-a second electrode pattern; 100-an ITO layer; 110-BCB glue; a 120-silicon wafer; 130-second metal pattern.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 3 and fig. 5, the present invention provides a method for manufacturing a light emitting diode, including:
Step S101: forming an array of light emitting diode units on a substrate 10, each light emitting diode unit comprising a buffer layer 20, an n-GaN layer 30, an MQV layer 40 and a p-GaN layer 50 in a direction away from the substrate 10;
Step S102: forming a first metal layer on the light emitting diode unit, and patterning the first metal layer through a patterning process to form a first metal pattern 60;
Step S103: a sidewall restriction structure is formed in a partial region of the p-GaN layer 50 using the first metal pattern 60 as a mask.
In the above method for manufacturing the light emitting diode, the light emitting diode units are formed on the substrate 10 in an array, the first metal layer is formed on the side of the light emitting diode units away from the substrate 10, the first metal pattern 60 is formed by using a patterning process, and the sidewall limiting structure is formed in the p-GaN layer 50 by using the first metal pattern 60 as a mask.
The light-emitting diode prepared by the preparation method of the light-emitting diode provided by the invention forms a side wall limiting structure at a local position in the p-GaN layer 50, and the side wall limiting structure can inhibit the side wall effect.
Therefore, the preparation method of the light-emitting diode not only can realize small current injection in a large-size light-emitting diode and avoid the side wall effect, but also can be compatible with the existing semiconductor process.
it should be noted that, due to patterning processes such as etching, the L ED has a large number of defects and dangling bonds on the sidewall, and the defects introduce impurity levels into the semiconductor energy band and cause indirect (SRH) non-radiative recombination, so that the light-emitting efficiency and brightness of the L ED are reduced at the same current density, that is, the sidewall effect is generated.
It is noted that the size of each led unit can be set according to the requirement, for example, the size of the led unit can be set to be less than 30 μm in the present embodiment; the substrate 10 may be a sapphire substrate, a silicon substrate, a SiC substrate, a glass substrate, or the like, and specifically, in each embodiment of the present invention, the material for preparing the substrate 10 is a sapphire substrate as an example; the MQW layer is called Multiple Quantum Well in English and called Multiple Quantum Well in Chinese.
Of course, the surface of the substrate 10 needs to be cleaned by a standard cleaning process before the light emitting diode unit is formed on the substrate 10.
In addition, the preparation process for forming the first metal layer may be one of a magnetron spraying process, a thermal evaporation process, an electron beam evaporation process, or an electroplating process, and takes the magnetron spraying process as an example: the first metal layer can be made of Ni or Cr, and the thickness of the first metal layer is 300-500 nm; the patterning process of the first metal layer comprises photoetching, a wet etching process and a photoresist removing process, wherein the alternative process of the wet etching process is a reactive ion ICP (inductively coupled plasma) etching process or an ion beam IBE (ion beam) etching process.
On the basis of the above technical solutions, it should be noted that there are various methods for forming the sidewall limiting structure, which are at least one of the following two ways, and the specific embodiments are as follows:
The first implementation mode comprises the following steps:
In one embodiment, a horizontal structure micro light emitting diode with a p-region partially electrically modified, and specifically, a method for forming a sidewall limiting structure includes:
Implanting deep-level impurity ions into the p-GaN layer 50 by using the first metal pattern 60 as a mask through an ion implantation process to form an implanted region 501, and reducing the conductivity of the implanted region 501 through an annealing process at 700-800 ℃; the deep level impurity ions are impurity level impurity ions about 1-1.7eV from the conduction band bottom or the valence band top of GaN.
the reasons for the reduced conductivity are (1) lattice defects caused by ion bombardment, which form defect levels in energy bands to capture carriers, and (2) ions entering the lattice and then being in interstitial positions to scatter carriers, so that the conductivity is reduced, the mobility is greatly reduced, and the resistance is significantly increased due to defects and substitutional ion scattering, and the like, and the injected ions form a transverse electric field in the L ED to further suppress the side wall effect, as shown in FIG. 2.
Setting an ion implantation process: energy of 50-250keV and dose of 2-6 x 10 13cm-2The implanted ion is N +、F+Or B +And the like. As shown in FIG. 4 as N +As a result of the experiment after ion implantation, the resistance increased by 4 orders or more at an appropriate temperature.
On the basis of the above technical solution, after reducing the conductivity of the implanted region, the method further includes:
Removing the first metal pattern 60, and etching to the n-GaN layer 30 along the direction of the p-GaN layer 50 pointing to the substrate 10 by the composition process outside the coverage of the injection region 501;
Forming a first insulating layer on the n-GaN layer 30, and forming a first via hole on the first insulating layer through a patterning process;
Forming a first electrode layer on the first insulating layer, and forming the first electrode layer into a first electrode pattern 80 through a patterning process, the first electrode pattern 80 being connected to the n-GaN layer 30 through a first via hole;
Forming a second insulating layer on the first electrode pattern 80, and forming a second via hole and a third via hole on the second insulating layer through a patterning process, wherein a vertical projection of the third via hole on the substrate 10 covers a vertical projection of the first via hole on the substrate 10;
A second electrode layer is formed on the second insulating layer, the second electrode layer partially fills the third via hole, and the second insulating layer is patterned to form a second electrode pattern 90, and the second electrode pattern 90 is connected to the p-GaN layer 50 through the second via hole, as shown in fig. 3.
It is noted that, in the method described in the above technical solution, the electrode on the n-GaN layer 30 includes a first electrode layer and a second electrode layer, and the electrode on the p-GaN layer 50 is only the second electrode layer; embodiment one the insulating layer 70 in fig. 3 includes a first insulating layer and a second insulating layer.
Note that, the process of removing the first metal pattern 60 is wet etching; the composition process of etching to the n-GaN layer 30 along the direction of the p-GaN layer 50 pointing to the substrate 10 is photoetching, ICP etching and photoresist removing; the first insulating layer and the second insulating layer are formed by Plasma Enhanced Chemical Vapor Deposition (PECVD), which can be SiOx or SiNx with a thickness of 300-500 nm; the processes for forming the first via hole and the second via hole are photolithography, RIE etching process and photoresist removing process.
In addition, the preparation process for forming the first electrode layer is a magnetron sputtering process, the preparation material is Ti or Al, the thickness is 10-30nm when the preparation material is Ti, and the thickness is 200-300nm when the preparation material is Al; the process of forming the first electrode pattern 80 from the first electrode layer is photolithography, wet etching, and photoresist removal.
Specifically, the preparation process for forming the second electrode layer is a magnetron sputtering process, the preparation material is Ni or Au or Ti or Al, the thickness is 5-30nm when the preparation material is Ni, 5-30nm when the preparation material is Au, 10-30nm when the preparation material is Ti, and 600-800nm when the preparation material is Al.
On the basis of the above technical solution, when the second electrode layer is formed into the second electrode pattern 90 by the composition process, an annealing process needs to be performed in a nitrogen atmosphere, wherein the annealing condition is that the temperature is 500 ℃ and the duration is 30 min.
The second embodiment:
The second embodiment is a vertical structure micro light emitting diode with p region and n region partially reversely doped, and specifically, the method for forming the sidewall limiting structure includes:
Si ions are implanted into a partial region of the p-GaN layer 50 using an ion implantation process using the first metal pattern (not shown) as a mask to form an n-type conductive region 502.
On the basis of the above technical solution, after the n-type conductive region 502 is formed, the method further includes:
Removing the first metal pattern and forming an ohmic contact electrode ITO layer 100 on the p-GaN layer 50;
Bonding a silicon wafer 120 on the ITO layer 100 by a bonding process;
Peeling off the substrate 10;
Removing the buffer layer 20;
Forming a second metal layer on the n-GaN layer 30, and patterning the second metal layer through a patterning process to form a second metal pattern 130;
Using the second metal pattern 130 as a mask, and implanting Mg ions into a partial region of the n-GaN layer 30 by using an ion implantation process to form a p-type conductive region;
Removing the second metal pattern 130, forming an insulating layer 70 on the n-GaN layer 30, and forming a first via hole on the insulating layer 70 through a patterning process;
A first electrode layer is formed on the insulating layer 70 and is formed into a first electrode pattern 80 through a patterning process, and the first electrode pattern 80 is connected to the n-GaN layer 30 through first via holes, as shown in fig. 5 and 6.
it should be noted that the process of removing the first metal pattern is wet etching, the thickness of the ITO layer 100 is 600-800nm, BCB glue 110 (chinese benzocyclobutene, english-called benzo cyclobutene) is spin-coated on the surface of the ITO layer 100 before the silicon wafer 120 is bonded on the ITO layer 100 by using a bonding process, the process of removing the substrate 10 is a laser lift-off LL O process, and the preparation material of the buffer layer 20 is AlN or GaN.
In addition, the preparation process for forming the second metal layer may be one of a magnetron spraying process, a thermal evaporation process, an electron beam evaporation process, or an electroplating process, and takes the magnetron spraying process as an example: the second metal layer can be made of Ni or Cr, and the thickness of the second metal layer is 300-500 nm; the second metal layer patterning process comprises photoetching, a wet etching process and a photoresist removing process, wherein the alternative process of the wet etching process is a reactive ion ICP (inductively coupled plasma) etching process or an ion beam IBE (ion beam) etching process.
The insulating layer 70 is formed by Plasma Enhanced Chemical Vapor Deposition (PECVD), which may be SiOx or SiNx with a thickness of 300-500 nm; the process for forming the first via hole comprises photoetching, RIE etching process and photoresist removing process; the preparation process for forming the first electrode layer is a magnetron sputtering process, the preparation material is Ti or Al, the thickness is 10-30nm when the preparation material is Ti, and the thickness is 200-300nm when the preparation material is Al; the process of forming the first electrode pattern 80 from the first electrode layer is photolithography, wet etching, and photoresist removal.
It should be noted that, when Mg ions are implanted, there is a certain requirement for the implantation depth of Mg ions along the direction from the n-GaN layer 30 to the p-GaN layer 50: at most, not more than the mqw layer and reaches the n-type conductive region 502 formed by the previous implantation to avoid Mg ion implantation from causing the n-type conductive region 502 formed in the p-GaN layer 50 to return to p-type conductivity.
In this embodiment, the p-GaN layer 50 is implanted with Si ions to form the n-type conductive region 502, and the n-GaN layer 30 is implanted with Mg ions to form the p-type conductive region, so that the sidewall confinement is achieved by reverse cut of the pn junction. Wherein ion implantation in the p-GaN layer 50 is a semiconductor doping process, the conductivity may be reduced or increased depending on the number of ions to be doped.
On the basis of the technical solutions in the first embodiment and the second embodiment, it should be noted that the patterning process for forming the light emitting diode units distributed in an array on the substrate 10 includes photolithography, a reactive ion ICP etching process, and a photoresist removing process.
The invention also provides a light-emitting diode which is prepared by adopting any one of the preparation methods of the light-emitting diode provided by the technical scheme.
It will be apparent to those skilled in the art that various changes and modifications may be made in the embodiments of the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (10)
1. A method for preparing a light-emitting diode is characterized by comprising the following steps:
Forming light emitting diode units distributed in an array on a substrate, wherein each light emitting diode unit comprises a buffer layer, an n-GaN layer, an MQV layer and a p-GaN layer along the direction deviating from the substrate;
Forming a first metal layer on the light emitting diode unit, and patterning the first metal layer through a composition process to form a first metal pattern;
And forming a side wall limiting structure in the partial region of the p-GaN layer by taking the first metal pattern as a mask.
2. The method of manufacturing according to claim 1, wherein the method of forming the sidewall limiting structure comprises:
Implanting deep-level impurity ions into the p-GaN layer by using the first metal pattern as a mask through an ion implantation process to form an implanted region, and reducing the conductivity of the implanted region through an annealing process at 700-800 ℃; the deep level impurity ions are impurity level impurity ions which are about 1-1.7eV away from the conduction band bottom or the valence band top of the GaN.
3. The method of claim 2, further comprising, after reducing the conductivity of the implanted region:
Removing the first metal pattern, and etching to the n-GaN layer along the direction of the p-GaN layer pointing to the substrate by a composition process outside the coverage of the injection region;
Forming a first insulating layer on the n-GaN layer, and forming a first via hole on the first insulating layer through a patterning process;
Forming a first electrode layer on the first insulating layer, and forming a first electrode pattern on the first electrode layer through a patterning process, wherein the first electrode pattern is connected with the n-GaN layer through the first via hole;
Forming a second insulating layer on the first electrode pattern, and forming a second via hole and a third via hole on the second insulating layer through a patterning process, wherein a vertical projection of the third via hole on the substrate covers a vertical projection of the first via hole on the substrate;
And forming a second electrode layer on the second insulating layer, wherein the second electrode layer is partially filled in the third via hole, and the second insulating layer is formed into a second electrode pattern through a composition process, and the second electrode pattern is connected with the p-GaN layer through the second via hole.
4. The method according to claim 3, wherein an annealing process is performed in a nitrogen atmosphere at a temperature of 500 ℃ for 30min when the second electrode layer is patterned to form the second electrode pattern.
5. The method of manufacturing according to claim 1, wherein the method of forming the sidewall limiting structure comprises:
And implanting Si ions into the partial region of the p-GaN layer by using the first metal pattern as a mask through an ion implantation process to form an n-type conductive region.
6. The method of claim 5, further comprising, after forming the n-type conductive region:
Removing the first metal pattern, and forming an ohmic contact electrode ITO layer on the p-GaN layer;
Bonding a silicon wafer on the ITO layer by a bonding process;
Peeling off the substrate;
Removing the buffer layer;
Forming a second metal layer on the n-GaN layer, and patterning the second metal layer through a composition process to form a second metal pattern;
Injecting Mg ions into the partial region of the n-GaN layer by using the second metal pattern as a mask through an ion injection process to form a p-type conductive region;
Removing the second metal pattern, forming an insulating layer on the n-GaN layer, and forming a first via hole on the insulating layer through a composition process;
And forming a first electrode layer on the insulating layer, forming a first electrode pattern on the first electrode layer through a composition process, and connecting the first electrode pattern with the n-GaN layer through the first via hole.
7. The production method according to any one of claims 1 to 6, wherein a production process for forming the first metal layer is one of a magnetron sputtering process, a thermal evaporation process, an electron beam evaporation process, and an electroplating process.
8. The method of claim 7, wherein the patterning process for forming the first metal pattern is a photolithography process, an etching process and a photoresist removal process, wherein the etching process includes one of a wet etching process, a reactive ion etching process or an ion beam etching process.
9. The method according to claim 7, wherein the patterning process for forming the light emitting diode units distributed in an array on the substrate comprises a photolithography process, a reactive ion etching process and a photoresist removing process.
10. A light-emitting diode produced by the method for producing a light-emitting diode according to any one of claims 1 to 9.
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| CN114242853A (en) * | 2021-12-29 | 2022-03-25 | 深圳市思坦科技有限公司 | Preparation method of LED device, LED device and display device |
| WO2023142147A1 (en) * | 2022-01-31 | 2023-08-03 | Jade Bird Display (Shanghai) Company | Micro led structure and micro display panel |
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| WO2023142147A1 (en) * | 2022-01-31 | 2023-08-03 | Jade Bird Display (Shanghai) Company | Micro led structure and micro display panel |
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| CN111446335B (en) | 2021-12-14 |
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