CN111446166A - 一种利用聚合物隔离层生成双沟槽晶体管的工艺方法 - Google Patents
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Abstract
本发明公开一种利用聚合物隔离层生成双沟槽晶体管的工艺方法,包括以下步骤:S1、在硅片基板上蚀刻出第一沟槽;S2、将初加工晶体管置于氧化炉管中进行氧化操作,并在第一沟槽的内侧壁生成氧化硅保护层;S3、以化学气相沉积工艺,在第一沟槽的氧化硅保护层上沉积形成有机硅薄膜层;S4、以含氟气体进行电浆化处理,形成侧壁;S5、随后在第一沟槽的底部向下继续蚀刻硅片基板的Si层,形成第二沟槽;S6、以O2电浆工艺,去除位于第一沟槽底部的有机硅薄膜层,形成双沟槽结构。双沟槽设计结构在同样封装体积取得更大的晶体管面积,使得双沟槽的静态电流通过以及承载高电压能力均得以增加,其极大化有效的电晶体面积能够提升1.5~2倍。
Description
技术领域
本发明属于晶片生产技术领域,具体涉及一种利用聚合物隔离层生成双沟槽晶体管的工艺方法。
背景技术
半导体集成电路(IC)工业经历了迅速的发展。在IC的发展过程中,通常增大了功能密度(即每个芯片区域的互连器件的数量),而减小了几何尺寸(即使用制造工艺可以制造的最小器件或互连线)。IC性能的提高主要是通过不断缩小集成电路器件的尺寸以提高它的速度来实现的。这种按比例缩小的工艺优点在于提高了生产效率并且降低了相关费用。同时,这种按比例缩小的工艺也增加了处理和制造IC的复杂性。
现在一般采用MOS-FET and IGBT方法来对晶体管进行开槽,比如MOS-FET andIGBT,目前工艺,只进行完成蚀刻单个浅沟槽。如图1所示,为现有工艺中生产的单沟槽晶体管,在晶体管材的厚度一定时,而单沟槽晶体管的单沟槽设计宽度是工艺方法所制(现有采用MOS-FET and IGBT方法已经是极限宽度),进而导致在单位面积的单晶硅表面能够蚀刻的浅沟槽条数有限。整个单晶硅表面形成的单沟槽壁的有效接触面积有限,限制了通过单沟槽的静态电流通过以及承载高电压能力,而从而使晶体管材的整体性能较差。
发明内容
针对现有技术的不足,本发明的目的在于提供一种利用聚合物隔离层生成双沟槽晶体管的工艺方法,解决了现有技术中单沟槽晶体管的通电能力以及承载高电压能力有限的技术问题。
本发明的目的可以通过以下技术方案实现:
一种利用聚合物隔离层生成双沟槽晶体管的工艺方法,包括以下步骤:
S1、选用硅片基板,并在硅片基板上蚀刻出第一沟槽,形成初加工晶体管,同时清洗去除第一沟槽侧壁的杂质;
S3、以化学气相沉积法使用有机前驱物,在第一沟槽的氧化硅保护层上均匀覆盖形成有机硅薄膜层;
S4、以含氟气体进行电浆化处理,并提供偏压电位,形成侧壁,此时蚀刻停止在氧化硅保护层上;
S5、用氮化硅侧壁作为硬掩模,随后在第一沟槽的底部以干蚀刻工艺继续蚀刻硅片基板的Si层,形成第二沟槽,并清洗去除第二沟槽侧壁的杂质;
S6、在400kHz-13.56mkHz的RF双极或三极电源产生的电浆,去除位于第一沟槽底部的有机硅薄膜层,使第一沟槽与第二沟槽形成整体呈双沟槽结构,即成型完成。
进一步的,所述S2中采用的氧化炉管中氧化操作的温度为900-1050℃。
进一步的,所述S3中所述有机硅薄膜层与氧化硅保护层的蚀刻比大于10:1。
进一步的,所述S3中采用的化学气相沉积工艺是在400-800℃温度下,以SiH2Cl2+NH3为原料进行沉积操作。
进一步的,所述S3中形成有机硅薄膜层的方法采用旋转涂布方式形成。
本发明的有益效果:
本申请通过使用双次蚀刻的步骤利用氮化硅隔离层工艺,在单沟槽晶体管内再增加沟槽,双沟槽设计结构在同样封装体积取得更大的晶体管面积,使得双沟槽的静态电流通过以及承载高电压能力均得以增加,从而使晶体管材的整体性能得到较大提成,其极大化有效的电晶体面积能够提升1.5~2倍。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1是本发明实施例的现有单沟槽晶体管结构示意图;
图2是本发明实施例的S1步骤成型结构示意图;
图3是本发明实施例的S2步骤成型结构示意图;
图4是本发明实施例的S3步骤成型结构示意图;
图5是本发明实施例的S5步骤成型结构示意图;
图6是本发明实施例的S6步骤成型结构示意图。
具体实施方式
下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其它实施例,都属于本发明保护的范围。
本实施例提供一种利用氮化硅隔离层生成双沟槽晶体管的工艺方法,包括以下步骤:
S1、如图2所示,选用硅片基板,并在硅片基板上蚀刻(etch)出第一沟槽11,形成初加工晶体管1。
S2、如图3所示,将初加工晶体管1置于温度为900-1050℃的氧化炉管中进行氧化操作,以便在第一沟槽的内侧壁生成厚度为的氧化硅保护层,且氧化硅保护层101的厚度x小于第一沟槽11位于第二沟槽12上边沿y宽度的1/10,同时在第一沟槽11所在的初加工晶体管1上方也形成氧化硅保护层101。
S3、如图4所示,以化学气相沉积法使用有机前驱物(organic precurser)或者使用旋转涂布方式,在第一沟槽11的氧化硅保护层101上均匀覆盖形成有机硅薄膜层102(即聚合物隔离层);其中有机硅薄膜层102与氧化硅保护层101的蚀刻比大于10:1,达到
S4、以含氟气体进行电浆化处理,并提供偏压电位,形成侧壁,此时蚀刻停止在氧化硅保护层101上。
S5、如图5所示,以第一沟槽11侧壁蚀刻出的有机硅薄膜层102作为硬掩模(hardmask),随后在第一沟槽的底部向下继续蚀刻(etch)硅片基板的Si层,形成第二沟槽,并清洗去除第二沟槽12侧壁的杂质。
S6、如图6所示,以O2电浆工艺(用400kHz-13.56mkHz的RF双极或三极电源产生的电浆)去除位于第一沟槽11底部的有机硅薄膜层102,使第一沟槽11与第二沟槽12形成整体呈双沟槽结构,即成型完成。
综上所述,本发明通过使用双次蚀刻的步骤利用氮化硅隔离层工艺,在单沟槽晶体管内再增加沟槽,双沟槽设计结构在同样封装体积取得更大的晶体管面积,使得双沟槽的静态电流通过以及承载高电压能力均得以增加,从而使晶体管材的整体性能得到较大提成,其极大化有效的电晶体面积能够提升1.5~2倍。
在本说明书的描述中,参考术语“一个实施例”、“示例”、“具体示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本发明的至少一个实施例或示例中。在本说明书中,对上述术语的示意性表述不一定指的是相同的实施例或示例。而且,描述的具体特征、结构、材料或者特点可以在任何的一个或多个实施例或示例中以合适的方式结合。
以上显示和描述了本发明的基本原理、主要特征和本发明的优点。本行业的技术人员应该了解,本发明不受上述实施例的限制,上述实施例和说明书中描述的只是说明本发明的原理,在不脱离本发明精神和范围的前提下,本发明还会有各种变化和改进,这些变化和改进都落入要求保护的本发明范围内。
Claims (5)
1.一种利用聚合物隔离层生成双沟槽晶体管的工艺方法,其特征在于,包括以下步骤:
S1、选用硅片基板,并在硅片基板上蚀刻出第一沟槽(11),形成初加工晶体管(1),同时清洗去除第一沟槽(11)侧壁的杂质;
S3、以化学气相沉积法使用有机前驱物,在第一沟槽(11)的氧化硅保护层(101)上均匀覆盖形成有机硅薄膜层(102);
S4、以含氟气体进行电浆化处理,并提供偏压电位,形成侧壁,此时蚀刻停止在氧化硅保护层(101)上;
S5、以第一沟槽(11)侧壁蚀刻出的有机硅薄膜层(102)作为硬掩模,随后在第一沟槽(11)的底部以干蚀刻工艺继续蚀刻硅片基板的Si层,形成第二沟槽(12),并清洗去除第二沟槽(12)侧壁的杂质;
S6、在400kHz-13.56MHz的RF双极或三极电源产生的电浆,去除位于第一沟槽(11)底部的有机硅薄膜层(102),使第一沟槽(11)与第二沟槽(12)形成整体呈双沟槽结构,即成型完成。
2.根据权利要求1所述的利用聚合物隔离层生成双沟槽晶体管的工艺方法,其特征在于,所述S2中采用的氧化炉管中氧化操作的温度为900-1050℃。
3.根据权利要求1所述的利用聚合物隔离层生成双沟槽晶体管的工艺方法,其特征在于,所述S3中所述有机硅薄膜层(102)与氧化硅保护层(101)的蚀刻比大于10:1。
4.根据权利要求1所述的利用聚合物隔离层生成双沟槽晶体管的工艺方法,其特征在于,所述S3中采用的化学气相沉积工艺是在400-800℃温度下,以SiH2Cl2+NH3为原料进行沉积操作。
5.根据权利要求1所述的利用聚合物隔离层生成双沟槽晶体管的工艺方法,其特征在于,所述S3中形成有机硅薄膜层(102)的方法采用旋转涂布方式形成。
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JP2001085387A (ja) * | 1999-09-13 | 2001-03-30 | Toshiba Corp | 半導体装置の製造方法 |
US20020059899A1 (en) * | 1999-03-12 | 2002-05-23 | Kabushiki Kaisha Toshida, Of Japan. | Manufacturing method of semiconductor devices by using dry etching technology |
CN104051263A (zh) * | 2013-03-11 | 2014-09-17 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件的制备方法 |
CN104485286A (zh) * | 2014-12-29 | 2015-04-01 | 上海华虹宏力半导体制造有限公司 | 包含中压sgt结构的mosfet及其制作方法 |
US20180166293A1 (en) * | 2016-12-13 | 2018-06-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming deep trench structure |
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US20020059899A1 (en) * | 1999-03-12 | 2002-05-23 | Kabushiki Kaisha Toshida, Of Japan. | Manufacturing method of semiconductor devices by using dry etching technology |
JP2001085387A (ja) * | 1999-09-13 | 2001-03-30 | Toshiba Corp | 半導体装置の製造方法 |
CN104051263A (zh) * | 2013-03-11 | 2014-09-17 | 中芯国际集成电路制造(上海)有限公司 | 一种半导体器件的制备方法 |
CN104485286A (zh) * | 2014-12-29 | 2015-04-01 | 上海华虹宏力半导体制造有限公司 | 包含中压sgt结构的mosfet及其制作方法 |
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