CN111446166A - Process method for generating double-groove transistor by utilizing polymer isolation layer - Google Patents
Process method for generating double-groove transistor by utilizing polymer isolation layer Download PDFInfo
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- CN111446166A CN111446166A CN202010181944.9A CN202010181944A CN111446166A CN 111446166 A CN111446166 A CN 111446166A CN 202010181944 A CN202010181944 A CN 202010181944A CN 111446166 A CN111446166 A CN 111446166A
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- 238000000034 method Methods 0.000 title claims abstract description 39
- 238000002955 isolation Methods 0.000 title claims abstract description 11
- 229920000642 polymer Polymers 0.000 title claims abstract description 9
- 239000010410 layer Substances 0.000 claims abstract description 34
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 23
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 23
- 239000010703 silicon Substances 0.000 claims abstract description 23
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 15
- 238000005530 etching Methods 0.000 claims abstract description 13
- 230000003647 oxidation Effects 0.000 claims abstract description 12
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 239000011241 protective layer Substances 0.000 claims abstract description 10
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 6
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims abstract description 4
- 229910052731 fluorine Inorganic materials 0.000 claims abstract description 4
- 239000011737 fluorine Substances 0.000 claims abstract description 4
- 238000009832 plasma treatment Methods 0.000 claims abstract description 4
- 238000000151 deposition Methods 0.000 claims abstract description 3
- 239000010409 thin film Substances 0.000 claims description 8
- 238000004140 cleaning Methods 0.000 claims description 5
- 239000012535 impurity Substances 0.000 claims description 5
- 239000010408 film Substances 0.000 claims description 4
- 239000002243 precursor Substances 0.000 claims description 4
- 238000004528 spin coating Methods 0.000 claims description 3
- 230000008021 deposition Effects 0.000 claims description 2
- 238000001312 dry etching Methods 0.000 claims description 2
- 238000012545 processing Methods 0.000 claims description 2
- 239000002994 raw material Substances 0.000 claims description 2
- 229920001296 polysiloxane Polymers 0.000 claims 1
- 238000013461 design Methods 0.000 abstract description 4
- 230000003068 static effect Effects 0.000 abstract description 3
- 238000004806 packaging method and process Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 4
- 239000000463 material Substances 0.000 description 3
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- ZMJOVJSTYLQINE-UHFFFAOYSA-N Dichloroacetylene Chemical compound ClC#CCl ZMJOVJSTYLQINE-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229920006268 silicone film Polymers 0.000 description 1
- 125000006850 spacer group Chemical group 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
- H01L21/30655—Plasma etching; Reactive-ion etching comprising alternated and repeated etching and passivation steps, e.g. Bosch process
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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Abstract
The invention discloses a process method for generating a double-groove transistor by utilizing a polymer isolation layer, which comprises the following steps of: s1, etching a first groove on the silicon wafer substrate; s2, placing the preliminary processed transistor in an oxidation furnace tube for oxidation operation, and generating a silicon oxide protective layer on the inner side wall of the first groove; s3, depositing an organic silicon film layer on the silicon oxide protective layer of the first groove by a chemical vapor deposition process; s4, forming a sidewall by plasma treatment with a fluorine-containing gas; s5, etching Si layer of the silicon wafer substrate downwards at the bottom of the first trench to form the second trenchTwo grooves; s6, with O2And (3) removing the organic silicon film layer at the bottom of the first groove by using a plasma process to form a double-groove structure. The double-groove design structure obtains larger transistor area in the same packaging volume, so that the static current passing and high voltage bearing capacity of the double grooves are increased, and the maximization effective transistor area can be improved by 1.5-2 times.
Description
Technical Field
The invention belongs to the technical field of wafer production, and particularly relates to a process method for generating a double-groove transistor by utilizing a polymer isolation layer.
Background
The semiconductor Integrated Circuit (IC) industry has experienced rapid growth. In the development of ICs, functional density (i.e., the number of interconnected devices per chip area) is typically increased, while geometry size (i.e., the smallest device or interconnect line that can be fabricated using a fabrication process) is reduced. Improvements in IC performance have been achieved primarily by the ever shrinking dimensions of integrated circuit devices to increase their speed. This scaled down process has the advantage of improving production efficiency and reducing associated costs. At the same time, this scaling down process also increases the complexity of handling and manufacturing the ICs.
At present, MOS-FET and IGBT methods are generally adopted to groove transistors, such as MOS-FET andIGBT, and the current process only completes etching a single shallow groove. As shown in fig. 1, for a single-trench transistor produced in the prior art, when the thickness of a transistor tube is fixed, the design width of a single trench of the single-trench transistor is made by a process method (the existing MOS-FET and IGBT method is already a limit width), and thus the number of shallow trenches that can be etched per unit area of a single-crystal silicon surface is limited. The effective contact area of the wall of the single trench formed on the surface of the whole monocrystalline silicon is limited, so that the static current passing through the single trench and the capacity of bearing high voltage are limited, and the overall performance of the transistor is poor.
Disclosure of Invention
In view of the defects in the prior art, an object of the present invention is to provide a process for forming a double-trench transistor using a polymer isolation layer, which solves the technical problem in the prior art that the power-on capability and the high voltage carrying capability of a single-trench transistor are limited.
The purpose of the invention can be realized by the following technical scheme:
a process for forming a double trench transistor using a polymer spacer, comprising the steps of:
s1, selecting a silicon wafer substrate, etching a first groove on the silicon wafer substrate to form a primary processing transistor, and cleaning to remove impurities on the side wall of the first groove;
s2, placing the transistor in the oxidation furnace tube to perform oxidation operation, so as to form a thickness of the first groove on the inner side wall
A silicon oxide protective layer of (a);
s3, uniformly covering the silicon oxide protective layer of the first groove with an organic silicon thin film layer by using an organic precursor through a chemical vapor deposition method;
s4, using fluorine-containing gas to perform plasma treatment and providing bias voltage potential to form sidewall, at this time, the etching stops on the silicon oxide protection layer;
s5, using the side wall of the silicon nitride as a hard mask, then continuing to etch the Si layer of the silicon wafer substrate at the bottom of the first groove by a dry etching process to form a second groove, and cleaning and removing impurities on the side wall of the second groove;
s6, removing the organic silicon film layer at the bottom of the first trench by plasma generated by RF bipolar or tripolar power supply at 400kHz-13.56mkHz, so that the first trench and the second trench form a whole double-trench structure, thus completing the forming.
Further, the temperature of the oxidation operation in the oxidation furnace tube adopted in the S2 is 900-1050 ℃.
Further, the etching ratio of the organic silicon thin film layer to the silicon oxide protective layer in the step S3 is greater than 10: 1.
Further, the chemical vapor deposition process adopted in S3 is performed by SiH at a temperature of 400-800 DEG C2Cl2+NH3A deposition operation is performed for the raw material.
Further, the method for forming the silicone film layer in S3 is formed by spin coating.
The invention has the beneficial effects that:
this application utilizes silicon nitride isolation layer technology through the step that uses the two-time etching, increases the slot again in single trench transistor, and the bigger transistor area is obtained at same encapsulation volume to two slot design structures for the quiescent current of two slots passes through and bears the high voltage ability and all can increase, thereby makes the wholeness ability of transistor material obtain great improvement, and its maximization effectual transistor area can promote 1.5 ~ 2 times.
Drawings
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained based on these drawings without creative efforts.
FIG. 1 is a schematic diagram of a conventional single trench transistor structure according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of the forming structure of step S1 according to the embodiment of the present invention;
FIG. 3 is a schematic diagram of the forming structure of step S2 according to the embodiment of the present invention;
FIG. 4 is a schematic diagram of the forming structure of step S3 according to the embodiment of the present invention;
FIG. 5 is a schematic diagram of the forming structure of step S5 according to the embodiment of the present invention;
fig. 6 is a schematic diagram of the forming structure of step S6 according to the embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment provides a process method for generating a double-groove transistor by using a silicon nitride isolation layer, which comprises the following steps:
s1, as shown in fig. 2, a silicon substrate is selected, and a first trench 11 is etched (etch) in the silicon substrate to form the transistor 1.
S2, as shown in FIG. 3, the preliminary processed transistor 1 is placed in an oxidation furnace tube at a temperature of 900-1050 ℃ to perform an oxidation operation so as to form a thickness of the first trench on the inner sidewall
And the thickness x of the silicon oxide protective layer 101 is smaller than 1/10 of the width y of the first trench 11 on the second trench 12, and the silicon oxide protective layer 101 is also formed above the first trench 11 in the first fabricated transistor 1.
S3, as shown in fig. 4, forming an organic silicon thin film layer 102 (i.e. a polymer isolation layer) on the silicon oxide protection layer 101 of the first trench 11 by using an organic precursor (organic precursor) or by using a spin coating method through a chemical vapor deposition method; wherein the etching ratio of the organic silicon film layer 102 to the silicon oxide protective layer 101 is more than 10:1, so as to achieve the aim of
S4, plasma treatment is performed by using gas containing fluorine, and bias voltage is applied to form sidewall, at which time the etching stops on the silicon oxide protection layer 101.
S5, as shown in fig. 5, using the organic silicon thin film layer 102 etched from the sidewall of the first trench 11 as a hard mask (hardmark), then continuing to etch (etch) the Si layer of the silicon wafer substrate downwards at the bottom of the first trench to form a second trench, and cleaning to remove the impurities on the sidewall of the second trench 12.
S6, as shown in FIG. 6, with O2The plasma process (plasma generated by RF bipolar or tripolar power source of 400kHz-13.56 mkHz) removes the organic silicon thin film layer 102 at the bottom of the first trench 11, so that the first trench 11 and the second trench 12 form an integral double-trench structure, thus completing the molding.
In summary, the present invention utilizes the silicon nitride isolation layer process by using the double etching step, and adds the trench in the single trench transistor, and the double trench design structure obtains a larger transistor area in the same package volume, so that the static current passing and high voltage carrying capability of the double trench can be increased, thereby greatly improving the overall performance of the transistor, and increasing the effective transistor area by 1.5-2 times.
In the description herein, references to the description of "one embodiment," "an example," "a specific example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The foregoing shows and describes the general principles, essential features, and advantages of the invention. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, which are described in the specification and illustrated only to illustrate the principle of the present invention, but that various changes and modifications may be made therein without departing from the spirit and scope of the present invention, which fall within the scope of the invention as claimed.
Claims (5)
1. A process for forming a double trench transistor using a polymer isolation layer, comprising the steps of:
s1, selecting a silicon wafer substrate, etching a first groove (11) on the silicon wafer substrate to form a primary processing transistor (1), and cleaning and removing impurities on the side wall of the first groove (11);
s2, placing the preliminary processed transistor (1) in an oxidation furnace tube for oxidation operation, so that the inner side wall of the first groove (11) is formed to be as thick as
A silicon oxide protective layer (101);
s3, uniformly covering and forming an organic silicon thin film layer (102) on the silicon oxide protection layer (101) of the first groove (11) by using an organic precursor through a chemical vapor deposition method;
s4, using fluorine-containing gas to perform plasma treatment and providing bias voltage potential to form sidewall, at this time, the etching stops on the silicon oxide protection layer (101);
s5, taking the organic silicon film layer (102) etched from the side wall of the first groove (11) as a hard mask, then continuing to etch the Si layer of the silicon wafer substrate at the bottom of the first groove (11) by a dry etching process to form a second groove (12), and cleaning and removing impurities on the side wall of the second groove (12);
s6, removing the organic silicon film layer (102) at the bottom of the first trench (11) by plasma generated by RF bipolar or tripolar power supply at 400kHz-13.56MHz, so that the first trench (11) and the second trench (12) form a whole and form a double-trench structure, i.e. the forming is completed.
2. The method as claimed in claim 1, wherein the temperature of the oxidation operation in the oxidation furnace employed in S2 is 900-1050 ℃.
3. The process of claim 1, wherein an etching ratio of the organosilicon thin film layer (102) to the silicon oxide protective layer (101) in S3 is greater than 10: 1.
4. The method as claimed in claim 1, wherein the chemical vapor deposition process used in S3 is SiH at a temperature of 400-2Cl2+NH3A deposition operation is performed for the raw material.
5. The process of forming a double trench transistor with a polymer isolation layer as claimed in claim 1, wherein the method of forming the silicone thin film layer (102) in S3 is formed by spin coating.
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| CN202010181944.9A CN111446166A (en) | 2020-03-16 | 2020-03-16 | Process method for generating double-groove transistor by utilizing polymer isolation layer |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115223862A (en) * | 2022-08-22 | 2022-10-21 | 北京北方华创微电子装备有限公司 | Groove etching method |
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|---|---|---|---|---|
| JP2001085387A (en) * | 1999-09-13 | 2001-03-30 | Toshiba Corp | Manufacture of semiconductor device |
| US20020059899A1 (en) * | 1999-03-12 | 2002-05-23 | Kabushiki Kaisha Toshida, Of Japan. | Manufacturing method of semiconductor devices by using dry etching technology |
| CN104051263A (en) * | 2013-03-11 | 2014-09-17 | 中芯国际集成电路制造(上海)有限公司 | Preparation method of semiconductor device |
| CN104485286A (en) * | 2014-12-29 | 2015-04-01 | 上海华虹宏力半导体制造有限公司 | MOSFET comprising medium voltage SGT structure and manufacturing method thereof |
| US20180166293A1 (en) * | 2016-12-13 | 2018-06-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming deep trench structure |
-
2020
- 2020-03-16 CN CN202010181944.9A patent/CN111446166A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020059899A1 (en) * | 1999-03-12 | 2002-05-23 | Kabushiki Kaisha Toshida, Of Japan. | Manufacturing method of semiconductor devices by using dry etching technology |
| JP2001085387A (en) * | 1999-09-13 | 2001-03-30 | Toshiba Corp | Manufacture of semiconductor device |
| CN104051263A (en) * | 2013-03-11 | 2014-09-17 | 中芯国际集成电路制造(上海)有限公司 | Preparation method of semiconductor device |
| CN104485286A (en) * | 2014-12-29 | 2015-04-01 | 上海华虹宏力半导体制造有限公司 | MOSFET comprising medium voltage SGT structure and manufacturing method thereof |
| US20180166293A1 (en) * | 2016-12-13 | 2018-06-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming deep trench structure |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN115223862A (en) * | 2022-08-22 | 2022-10-21 | 北京北方华创微电子装备有限公司 | Groove etching method |
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Application publication date: 20200724 |