CN111446157A - Shielded gate field effect transistor and method of forming the same - Google Patents
Shielded gate field effect transistor and method of forming the same Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 95
- 230000005669 field effect Effects 0.000 title claims abstract description 34
- 239000003989 dielectric material Substances 0.000 claims abstract description 82
- 238000005530 etching Methods 0.000 claims abstract description 29
- 230000003647 oxidation Effects 0.000 claims abstract description 28
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 28
- 238000002955 isolation Methods 0.000 claims abstract description 19
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- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000002360 preparation method Methods 0.000 abstract description 10
- 230000003071 parasitic effect Effects 0.000 abstract description 5
- 239000011810 insulating material Substances 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 4
- 238000001039 wet etching Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 238000005137 deposition process Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
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- 239000012535 impurity Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
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- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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Abstract
The invention provides a shielded gate field effect transistor and a forming method thereof. The first oxide layer is formed on the top surface of the shielding electrode through the first oxidation process, so that when the etching process is carried out to completely remove the upper part of the dielectric material layer, the first oxide layer can be utilized to resist the etching consumption of the shielding electrode, the problem of the top protrusion of the shielding electrode is effectively solved, and the second oxide layer can be directly formed on the top surface of the shielding electrode through the oxidation process to form the isolation oxide layer. Therefore, the process difficulty can be effectively reduced, the preparation yield of the product is improved, the preparation cost of the product is favorably reduced, and the parasitic capacitance between the gate electrode and the shielding electrode can be effectively reduced.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a shielded gate field effect transistor and a forming method thereof.
Background
Because the Shielded Gate field effect transistor (SGT) has a low Gate-drain capacitance Cgd, a very low on-resistance, and a high withstand voltage, it is more favorable for flexible application of a semiconductor integrated circuit. Particularly, in the shielded gate field effect transistor, the shielding electrode is arranged below the gate electrode, so that the gate-drain capacitance can be greatly reduced, and the drift region of the shielded gate field effect transistor also has higher impurity carrier concentration, so that the shielded gate field effect transistor can provide additional benefits for the breakdown voltage of a device, and correspondingly can reduce the on-resistance.
Although the shielded gate field effect transistor has many performance advantages compared to other trench field effect transistors, the fabrication process is more complicated. Referring specifically to fig. 1a to fig. 1f, the following steps may be referred to in the present method for manufacturing a shielded gate field effect transistor.
In a first step, referring specifically to fig. 1a, a substrate 10 is provided, a gate trench 10a is formed in the substrate 10, and a dielectric material layer 20 and a shield electrode 30 are further formed in the gate trench 10a, where the dielectric material layer 20 covers the sidewalls and the bottom wall of the gate trench 10 a.
In a second step, specifically referring to fig. 1b, the dielectric material layer is etched to form a shielding dielectric layer 20 a. When the dielectric material layer is etched at a portion higher than the shielding electrode 30, the etchant further erodes the dielectric material at the top periphery of the shielding electrode 30, so that the top surface of the shielding electrode 30 is higher than the top surface of the shielding dielectric layer 20 a.
A third step, shown in fig. 1c in particular, is to perform a deposition process to fill the gate trench 10a with an insulating material layer 50a, where the insulating material layer 50a also covers the top surface of the substrate.
A fourth step, specifically referring to fig. 1d, is to perform a planarization process to planarize the insulating material layer 50a and remove the portion of the insulating material layer 50a covering the top surface of the substrate.
A fifth step, shown in particular in fig. 1e, is to perform an etching process to partially remove the layer of insulating material and to form an isolation layer 50 with the remaining layer of insulating material to cover the top surface of the shield electrode 30.
A sixth step, shown with particular reference to fig. 1f, forms a gate electrode 70 in said gate trench 10 a.
Based on the above-mentioned preparation process, at present, when forming the isolation layer between the shield electrode and the gate electrode, a deposition process, a planarization process and an etching process need to be performed in sequence, which not only is the process complicated, but also has a greater process difficulty, a stricter requirement and a higher preparation cost for the gate trench with a high aspect ratio.
Disclosure of Invention
The invention aims to provide a method for forming a shielded gate field effect transistor, which aims to solve the problems of high process difficulty, stricter requirements and higher preparation cost in the existing preparation method.
To solve the above technical problem, the present invention provides a method for forming a shielded gate field effect transistor, comprising:
providing a substrate, wherein a grid groove is formed in the substrate;
forming a dielectric material layer and a shielding electrode in the gate trench, wherein the dielectric material layer covers the bottom wall and the side wall of the gate trench, the shielding electrode is formed on the dielectric material layer, and the top surface of the shielding electrode is lower than the top surface of the substrate so as to expose part of the dielectric material layer;
performing a first oxidation process to form a first oxide layer on a top surface of the shield electrode;
performing an etching process to remove a part of the dielectric material layer higher than the shielding electrode and consume the first oxide layer;
performing a second oxidation process to form a second oxide layer on a top surface of the shield electrode and a gate oxide layer on a sidewall of the trench where the gate trench is higher than the shield electrode; and the number of the first and second groups,
filling a gate electrode in the gate trench, the gate electrode being formed over the second oxide layer.
Optionally, before performing the first oxidation process, the method further includes: and performing a first etching process, wherein the first etching process comprises the step that an etchant partially removes the exposed dielectric material layer along the direction vertical to the side wall of the groove so as to reduce the thickness of the exposed dielectric material layer, and the part with the reduced thickness in the dielectric material layer forms an upper dielectric layer.
Optionally, the thickness of the first oxide layer is greater than or equal to that of the upper dielectric layer.
Optionally, the first etching process includes a wet etching process
Optionally, the part of the dielectric material layer which is not thinned forms a lower dielectric layer, and the bottom of the upper dielectric layer is lower than the top of the shielding electrode, so that the top surface of the shielding electrode is convex relative to the top surface of the lower dielectric layer;
and, after performing the first etching process, further comprising: etching the protruding portion of the shield electrode to lower a top surface of the shield electrode.
Optionally, the protruding portion of the shielding electrode is etched so that the top surface of the shielding electrode is not higher than the top surface of the lower dielectric layer.
Optionally, the sidewall of the first oxide layer is transversely connected to the sidewall of the lower dielectric layer.
Optionally, an etching process is performed to remove a portion of the dielectric material layer that is higher than the shielding electrode, and a shielding dielectric layer is formed by using the remaining dielectric material layer, where a top surface of the shielding electrode is not higher than a top surface of the shielding dielectric layer.
Optionally, the sidewall of the second oxide layer is laterally connected to the sidewall of the shielding dielectric layer.
Based on the above forming method, the present invention also provides a shielded gate field effect transistor, including:
a substrate having a gate trench formed therein;
the shielding dielectric layer covers the bottom wall and part of the side wall of the grid groove;
a shield electrode formed on the shield dielectric layer and filling the bottom of the gate trench, and a top surface of the shield electrode is lower than a top surface of the shield dielectric layer;
an isolation oxide layer formed on the top surface of the shield electrode, and the side wall of the isolation oxide layer is transversely connected with the side wall of the shield dielectric layer;
the grid oxidation layer is formed on the side wall of the groove of which the grid groove is higher than the shielding electrode; and the number of the first and second groups,
and the gate electrode is formed above the isolation oxide layer and fills the gate groove.
In the method for forming the shielded gate field effect transistor, before the upper part of the dielectric material layer higher than the shielding electrode is completely removed, the first oxidation layer is formed on the top surface of the shielding electrode through the first oxidation process, so that when the etching process is carried out to completely remove the upper part of the dielectric material layer, the first oxidation layer can be consumed downwards at the same time, the shielding electrode and the dielectric material on the periphery of the top part are prevented from being corroded by undercutting, and the problem that the top part of the shielding electrode protrudes can be effectively solved. Based on this, the second oxide layer may be formed on the top surface of the shield electrode directly using an oxidation process to constitute an isolation oxide layer, so that the gate electrode and the shield electrode may be spaced up and down by the isolation oxide layer. Namely, the top of the shielding electrode is not protruded to a large extent, so that the lateral wall of the shielding electrode is greatly reduced or even prevented from being exposed out of the shielding dielectric layer, and accordingly, after the isolation oxide layer is formed by directly utilizing an oxidation process, the lateral wall of the shielding electrode can be correspondingly prevented from being protruded out of the shielding dielectric layer, at the moment, the gate electrode can only be opposite to the top surface of the shielding electrode, and the parasitic capacitance between the gate electrode and the shielding electrode is effectively reduced. Therefore, in the forming method provided by the invention, the process difficulty can be effectively reduced, the preparation yield of the shielded gate field effect transistor is improved, the preparation cost of the product is favorably reduced, and the device performance of the formed shielded gate field effect transistor can be effectively ensured.
Drawings
FIGS. 1a to 1f are schematic structural diagrams of a conventional method for forming a shielded gate field effect transistor during a manufacturing process thereof;
FIG. 2 is a flow chart illustrating a method of forming a shielded gate field effect transistor according to an embodiment of the invention;
fig. 3a to fig. 3g are schematic structural diagrams of a method for forming a shielded gate field effect transistor in a manufacturing process according to an embodiment of the invention.
Wherein the reference numbers are as follows:
10/100-a substrate;
10a/100 a-gate trench;
20/200-a layer of dielectric material;
210-an upper dielectric layer;
220-lower dielectric layer;
20a/200 a-shielding dielectric layer;
30/300-shielding electrode;
400-a first oxide layer;
50 a-a layer of insulating material;
50-an isolation layer;
500-a second oxide layer;
600-a gate oxide layer;
70/700-gate electrode.
Detailed Description
The shielded gate field effect transistor and the method for forming the same according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Fig. 2 is a schematic flow chart of a method for forming a shielded gate field effect transistor according to an embodiment of the invention, and fig. 3a to 3g are schematic structural diagrams of the method for forming a shielded gate field effect transistor according to an embodiment of the invention in a manufacturing process thereof. The forming method in the present embodiment will be described in detail below with reference to the drawings.
In step S100, specifically referring to fig. 3a, a substrate 100 is provided, wherein a gate trench 100a is formed in the substrate 100. In the subsequent process, the gate trench 100a is used to sequentially accommodate the shield electrode and the gate electrode from bottom to top.
The substrate 100 includes, for example, a base and an epitaxial layer formed on the base, and the gate trench 100a is formed in the epitaxial layer.
Further, the method for forming the gate trench 100a includes: firstly, forming a mask layer on the top surface of the substrate 100 to define a pattern of the gate trench by using the mask layer; next, the substrate 100 is etched using the mask layer as a mask to form the gate trench 100 a.
In this embodiment, the sidewall of the gate trench 100a may be a vertical sidewall or a slightly inclined sidewall. That is, in the present embodiment, the inclination angle of the sidewall of the gate trench 100a with respect to the height direction is small. Note that the "inclination angle of the sidewall of the gate trench 100a with respect to the height direction" described here is: the angle between the sidewall of the gate trench 100a and the height direction.
In step S200, with continued reference to fig. 3a, a dielectric material layer 200 and a shield electrode 300 are sequentially formed in the gate trench 100 a. Wherein the dielectric material layer 200 covers the bottom wall and the sidewall of the gate trench 100a, the shielding electrode 300 is formed on the dielectric material layer 200, and the top of the shielding electrode 300 is lower than the top of the gate trench 100a to expose a portion of the dielectric material layer 200.
Specifically, the dielectric material layer 200 may be formed by a thermal oxidation process, for example. And, the material of the dielectric material layer 200 includes, for example, silicon oxide (SiO).
Further, the thickness of the dielectric material layer 200 may be adjusted according to the voltage endurance of the formed shielded gate field effect transistor, and is not limited herein. For example, when the formed shielded gate field effect transistor is a high-voltage transistor, a dielectric material layer with a larger thickness (for example, the thickness of the dielectric material layer is greater than or equal to 3000 angstroms) can be formed to realize the voltage withstanding performance of the high-voltage transistor; alternatively, when the formed shielded gate field effect transistor is a low voltage transistor, a dielectric material layer with a smaller thickness may be formed (for example, the thickness of the dielectric material layer is greater than or equal to 1000 angstroms).
With continued reference to fig. 3a, after forming the dielectric material layer 200, i.e., forming a shield electrode 300 on the dielectric material layer 200, the shield electrode 300 correspondingly fills the gate trench 100 a. The shielding electrode 300 may be formed, for example, by using an etch-back process, so that the top position of the shielding electrode 300 is lowered, and the top position of the shielding electrode 300 is lower than the top position of the gate trench 100 a. At this time, the portion of the dielectric material layer 200 higher than the shielding electrode 300 is exposed.
It should be noted that, in the subsequent process, a portion of the dielectric material layer 200 above the shield electrode 300 is usually removed, and a gate oxide layer and a gate electrode are sequentially formed in the space above the gate trench 100a above the shield electrode 300.
However, if the portion of the dielectric material layer 200 higher than the shielding electrode 300 is directly etched to completely remove the portion of the dielectric material layer 200 higher than the shielding electrode 300, the etchant may also attack the dielectric material on the top periphery of the shielding electrode 300, so that the top surface of the shielding electrode 300 is protruded. At this time, the oxidation process is further performed to form an isolation oxide layer on the exposed surface of the shield electrode 300, and after the gate electrode is further prepared, the gate electrode may not only have a portion facing each other with the top surface of the shield electrode, but also have a portion facing each other with the sidewalls of the gate electrode and the shield electrode, thereby causing an excessive parasitic capacitance between the gate electrode and the shield electrode. It should be appreciated that after the portions of the dielectric material layer above the shield electrode are completely removed, the top portion of the shield electrode is directly etched back to avoid protruding the top surface of the shield electrode, which may also damage the exposed trench sidewalls.
Based on this, in this embodiment, before removing the portion of the dielectric material layer 200 higher than the shielding electrode 300, a first oxide layer is further formed on the top surface of the shielding electrode 300, so that when the dielectric material layer 200 is partially removed, the first oxide layer can be used to form a consumable material, and the consumable material and the dielectric material on the periphery of the first oxide layer can be consumed at the same time, thereby effectively improving the problem of the protrusion of the top of the shielding electrode 300. Specific reference is made to steps S300 to S400 described below.
Specifically, step S300 is performed first, a first oxidation process is performed to form a first oxide layer on the top surface of the shield electrode 300; next, step S400 is performed to perform an etching process to remove a portion of the dielectric material layer 200 higher than the shielding electrode 300 and consume the first oxide layer, wherein the remaining dielectric material layer may form a shielding dielectric layer. That is, due to the existence of the first oxide layer, the problem of protrusion of the top of the shielding electrode 300 can be effectively improved, for example, the protrusion height of the shielding electrode 300 can be reduced, and even the top surface of the shielding electrode 300 can be made not higher than the top surface of the shielding dielectric layer.
In addition, in an alternative scheme, when the thickness of the dielectric material layer 200 is relatively thin, the steps S300 and S400 may be directly performed to remove the portion of the dielectric material layer 200 higher than the shielding electrode 300 to form a shielding dielectric layer, and effectively improve the problem that the top surface of the shielding electrode 300 protrudes relative to the top surface of the shielding dielectric layer. However, in other schemes, when the thickness of the dielectric material layer 200 is thicker, the upper portion of the dielectric material layer 200 may be partially removed to thin the upper portion of the dielectric material layer 200 before performing steps S300 and S400; then, when performing the steps S300 and S400, the thickness of the formed first oxide layer can be allowed to be thinner, and at this time, when the thinned upper portion is removed, the first oxide layer is sufficiently consumed even if the thickness of the first oxide layer is thinner.
The following is an explanation taking as an example that the upper portion of the dielectric material layer 200 is partially removed before the steps S300 and S400 are performed.
Referring specifically to fig. 3b, a first etching process is performed, which includes an etchant to partially remove the exposed dielectric material layer 200 along a direction perpendicular to the trench sidewalls, so as to reduce the thickness of the exposed dielectric material layer 200. The part of the dielectric material layer 200 with reduced thickness forms an upper dielectric layer 210, and the part of the dielectric material layer 200 without reduced thickness forms a lower dielectric layer 220.
Specifically, the first etching process may include a wet etching process, so as to implement uniform etching of the exposed dielectric material layer 200 along a direction perpendicular to the trench sidewall by using the isotropic etching performance of the wet etching process, and accordingly, the thickness of the dielectric material layer (i.e., the upper dielectric layer 210) with a reduced thickness after etching is uniform. In addition, compared with a dry etching process, the damage of the exposed shielding electrode 300 caused by the etchant can be further alleviated by using the wet etching process.
In a further aspect, the bottom of the upper dielectric layer 210 is lower than the top of the shielding electrode 300, such that the top surface of the shielding electrode 300 is protruded relative to the top surface of the lower dielectric layer 220.
Specifically, when the first etching process is performed on the dielectric material layer 200, the etchant etches a portion of the dielectric material layer 200 that is higher than the shielding electrode 300, and the etchant further undercuts a portion of the dielectric material layer 200 that borders the shielding electrode 300. That is, the etchant also etches the portion of the dielectric material layer 200 surrounding the top periphery of the shielding electrode 300, so that the bottom of the reduced thickness portion (i.e., the upper dielectric layer 210) in the dielectric material layer 200 is lower than the top of the shielding electrode 300, and accordingly, the top surface of the lower dielectric layer 220 is lowered, and the top surface of the shielding electrode 300 is protruded relative to the top surface of the lower dielectric layer 220.
Referring next to fig. 3c, the protruding portion of the shielding electrode 300 is etched to lower the top surface of the shielding electrode 300. Specifically, the protruding portion of the shielding electrode 300 may be etched by a dry etching process, and the top surface of the shielding electrode 300 may be not higher than the top surface of the lower dielectric layer 220.
In this embodiment, when the protruding portion of the shielding electrode 300 is etched, the upper dielectric layer 210 is still covered on the sidewall of the gate trench 100a, so as to avoid etching damage to the sidewall of the gate trench 100a, which is beneficial to ensuring the device performance of the finally formed shielded gate field effect transistor.
Further, after removing the protruding portion of the shielding electrode 300, the top surface of the remaining shielding electrode 300 and the top surface of the lower dielectric layer 220 may be made flush; alternatively, the top surface of the remaining shield electrode 300 may be lower than the top surface of the lower dielectric layer 220.
It should be noted that, by removing the protruding portion of the shielding electrode 300 to lower the top surface of the shielding electrode 300 to the lower dielectric layer 220, the first oxide layer whose sidewalls are connected to the dielectric material layer 200 can be formed on the top surface of the shielding electrode 300 by directly using an oxidation process in step S300. In this way, in step S400, when the upper dielectric layer 210 of the dielectric material layer 200 is removed, the problem of the protrusion of the top of the shielding electrode 300 can be solved based on the first oxide layer. This will be explained in detail in the subsequent steps.
Specifically, in step S300, specifically referring to fig. 3d, a first oxidation process is performed to form a first oxidation layer 400 on the top surface of the shield electrode. Wherein the material of the shielding electrode 300 comprises, for example, polysilicon, and based on this, a silicon oxide layer may be formed on the top surface of the shielding electrode 300 in a self-aligned manner by a first oxidation process to form the first oxide layer 400.
Specifically, since the top surface of the shielding electrode 300 is not higher than the top surface of the lower dielectric layer 220, and the first oxide layer 400 formed on the top surface of the shielding electrode 300 by the oxidation process can extend down into the shielding electrode 300, the first oxide layer 400 is correspondingly connected to the lower dielectric layer 220. It is understood that the top of the shield electrode 300 can be oxidized to form the first oxide layer 400 by the first oxidation process, and the first oxide layer 400 correspondingly extends downward such that the bottom of the first oxide layer 400 is lower than the top of the lower dielectric layer 220. At this time, the first oxide layer 400 and the lower dielectric layer 220 can be laterally connected to each other on the same horizontal plane, so that when the upper dielectric layer 210 is subsequently removed, the etchant can be prevented from further undercutting the dielectric material on the sidewalls of the non-oxidized shielding electrode 300, and the remaining shielding electrode 300 will not protrude from the lower dielectric layer 220.
In this embodiment, the thickness of the first oxide layer 400 may be greater than the thickness of the upper dielectric layer 210, so that when the upper dielectric layer 210 is subsequently removed and the first oxide layer 400 is consumed at the same time, it may be avoided that the first oxide layer 400 is consumed in advance due to an excessively thin thickness, and further, the shielding electrode 300 may be prevented from being protruded again due to the undercut of the dielectric layer at the top periphery of the shielding electrode 300. Of course, the thickness of the first oxide layer 400 and the thickness of the upper dielectric layer 210 may be equal or nearly equal.
In step S400, specifically referring to fig. 3e, a second etching process is performed to remove the upper dielectric layer in the dielectric material layer and consume the first oxide layer. Specifically, the lower dielectric layer in the dielectric material layer is retained and constitutes the shielding dielectric layer 200 a.
As shown in fig. 3d and fig. 3e, since the sidewalls of the first oxide layer 400 and the sidewalls of the lower dielectric layer 220 are in contact connection, which is equivalent to that the top and the sidewalls of the shielding electrode 300 are covered by the first oxide layer 400 and the lower dielectric layer 220, so that, when the upper dielectric layer 210 is removed, the etchant simultaneously consumes the first oxide layer 400 and the portion of the lower dielectric layer 220 connected thereto downward, at this time, the etchant is prevented from underetching the dielectric material on the periphery of the top of the shielding electrode 300, the problem of the protrusion of the top of the shielding electrode 300 is effectively solved, and accordingly, the sidewalls of the shielding electrode 300 are prevented from being laterally exposed out of the shielding dielectric layer 200 a.
In this embodiment, the upper dielectric layer is removed to expose the trench sidewall of the gate trench 100a higher than the shield electrode 300. In this embodiment, the top surface of the shielding electrode 300 is also exposed, and the top surface of the shielding electrode 300 may not be higher than the top surface of the remaining shielding dielectric layer 200 a.
In step S500, referring specifically to fig. 3f, a second oxidation process is performed to form a second oxide layer 500 on the top surface of the shield electrode 300 and a gate oxide layer 600 on the sidewalls of the gate trench 100 a. Specifically, the second oxide layer 500 may constitute an isolation oxide layer for isolating the shielding electrode 300 from a gate electrode formed later.
Similar to the first oxide layer, since the top surface of the shielding electrode 300 is not higher than the top surface of the shielding dielectric layer 200a, and the second oxide layer 500 formed on the top surface of the shielding electrode 300 by the oxidation process can extend down into the shielding electrode 300, the second oxide layer 500 is laterally connected to the shielding dielectric layer 200a, respectively. That is, the second oxide layer 500 and the shielding dielectric layer 200a can be laterally connected to each other on the same horizontal plane, and thus the shielding electrode 300 can be effectively isolated.
In step S600, referring specifically to fig. 3g, a gate electrode 700 is filled in the gate trench 100a, and the gate electrode 700 is formed on the second oxide layer 500. At this time, the second oxide layer 500 is spaced apart from the gate electrode 700 and the shield electrode 300.
As described above, since the sidewalls of the shielding electrode 300 do not protrude from the shielding dielectric layer 200a, the gate electrode 700 is only opposite to the top surface of the shielding electrode 300, and the parasitic capacitance between the gate electrode 700 and the shielding electrode 300 is effectively reduced.
Based on the above forming method, the present embodiment further provides a shielded gate field effect transistor, which can be specifically shown in fig. 3g, where the shielded gate field effect transistor includes:
a substrate 100, a gate trench 100a being formed in the substrate 100;
a shielding dielectric layer 200a covering the bottom wall and part of the side wall of the gate trench 100 a;
a shield electrode 300 formed on the shield dielectric layer 200a and filling the bottom of the gate trench 100a, and a top surface of the shield electrode 300 is lower than a top surface of the shield dielectric layer 200 a;
an isolation oxide layer (i.e., a second oxide layer 500) formed on the top surface of the shield electrode 300 and having sidewalls laterally connected to sidewalls of the shield dielectric layer 200 a;
a gate oxide layer 600 formed on a trench sidewall of the gate trench 100a higher than the shield electrode 300; and the number of the first and second groups,
and a gate electrode 700 formed over the isolation oxide layer and filling the gate trench 100 a.
In summary, in the method for forming a shielded gate field effect transistor according to the embodiment, before the upper portion of the dielectric material layer higher than the shield electrode is completely removed, the first oxide layer is formed on the top surface of the shield electrode through the first oxidation process, so that when the etching process is performed to completely remove the upper portion of the dielectric material layer, the first oxide layer can be used to resist the etching consumption of the shield electrode, thereby preventing the shield electrode and the dielectric material on the periphery of the top portion from being undercut, and further effectively improving the problem of the top portion of the shield electrode protruding. Therefore, the gate electrode is only opposite to the top surface of the shielding electrode, and the parasitic capacitance between the gate electrode and the shielding electrode is effectively reduced.
Particularly, the side wall based on the shielding electrode does not protrude out of the shielding dielectric layer, and at the moment, the second oxide layer can be directly formed on the top surface of the shielding electrode by adopting an oxidation process to form an isolation oxide layer, so that the isolation performance between the gate electrode and the shielding electrode can be still ensured, the process difficulty can be effectively reduced, the preparation yield of the product is improved, and the preparation cost of the product is favorably reduced.
It should be noted that, although the present invention has been described with reference to the preferred embodiments, the present invention is not limited to the embodiments. It will be apparent to those skilled in the art from this disclosure that many changes and modifications can be made, or equivalents modified, in the embodiments of the invention without departing from the scope of the invention. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention are still within the protection scope of the technical solution of the present invention, unless the content of the technical solution of the present invention is departed from.
It should be further understood that the terms "first," "second," "third," and the like in the description are used for distinguishing between various components, elements, steps, and the like, and are not intended to imply a logical or sequential relationship between various components, elements, steps, or the like, unless otherwise indicated or indicated.
It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the present invention. It must be noted that, as used herein and in the appended claims, the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. For example, reference to "a step" or "an apparatus" means a reference to one or more steps or apparatuses and may include sub-steps as well as sub-apparatuses. All conjunctions used should be understood in the broadest sense. And, the word "or" should be understood to have the definition of a logical "or" rather than the definition of a logical "exclusive or" unless the context clearly dictates otherwise. Further, implementation of the methods and/or apparatus of embodiments of the present invention may include performing the selected task manually, automatically, or in combination.
Claims (10)
1. A method of forming a shielded gate field effect transistor, comprising:
providing a substrate, wherein a grid groove is formed in the substrate;
forming a dielectric material layer and a shielding electrode in the gate trench, wherein the dielectric material layer covers the bottom wall and the side wall of the gate trench, the shielding electrode is formed on the dielectric material layer, and the top surface of the shielding electrode is lower than the top surface of the substrate so as to expose part of the dielectric material layer;
performing a first oxidation process to form a first oxide layer on a top surface of the shield electrode;
performing an etching process to remove a part of the dielectric material layer higher than the shielding electrode and consume the first oxide layer;
performing a second oxidation process to form a second oxide layer on a top surface of the shield electrode and a gate oxide layer on a sidewall of the trench where the gate trench is higher than the shield electrode; and the number of the first and second groups,
filling a gate electrode in the gate trench, the gate electrode being formed over the second oxide layer.
2. The method of forming a shielded gate field effect transistor according to claim 1, further comprising, prior to performing the first oxidation process:
and performing a first etching process, wherein the first etching process comprises the step that an etchant partially removes the exposed dielectric material layer along the direction vertical to the side wall of the groove so as to reduce the thickness of the exposed dielectric material layer, and the part with the reduced thickness in the dielectric material layer forms an upper dielectric layer.
3. The method of claim 2, wherein the first oxide layer has a thickness greater than or equal to a thickness of the upper dielectric layer.
4. The method of forming a shielded gate field effect transistor according to claim 2 wherein said first etch process comprises a wet etch process.
5. The method of claim 2, wherein the unreduced portion of the dielectric material layer constitutes a lower dielectric layer and a bottom portion of the upper dielectric layer is lower than a top portion of the shield electrode such that a top surface of the shield electrode is raised relative to a top surface of the lower dielectric layer;
and, after performing the first etching process, further comprising: etching the protruding portion of the shield electrode to lower a top surface of the shield electrode.
6. The method of claim 5, wherein the raised portion of the shield electrode is etched such that a top surface of the shield electrode is not higher than a top surface of the lower dielectric layer.
7. The method of claim 5, wherein sidewalls of the first oxide layer laterally connect sidewalls of the lower dielectric layer.
8. The method of claim 1, wherein an etching process is performed to remove portions of the dielectric material layer above the shield electrode and form a shield dielectric layer with a remaining dielectric material layer, wherein a top surface of the shield electrode is not higher than a top surface of the shield dielectric layer.
9. The method of claim 8, wherein sidewalls of the second oxide layer laterally connect sidewalls of the shield dielectric layer.
10. A shielded gate field effect transistor fabricated by the formation method according to any one of claims 1 to 9, comprising:
a substrate having a gate trench formed therein;
the shielding dielectric layer covers the bottom wall and part of the side wall of the grid groove;
a shield electrode formed on the shield dielectric layer and filling the bottom of the gate trench, and a top surface of the shield electrode is lower than a top surface of the shield dielectric layer;
an isolation oxide layer formed on the top surface of the shield electrode, and the side wall of the isolation oxide layer is transversely connected with the side wall of the shield dielectric layer;
the grid oxidation layer is formed on the side wall of the groove of which the grid groove is higher than the shielding electrode; and the number of the first and second groups,
and the gate electrode is formed above the isolation oxide layer and fills the gate groove.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111681962A (en) * | 2020-07-30 | 2020-09-18 | 上海华虹宏力半导体制造有限公司 | Shielding grid power device and manufacturing method thereof |
| CN113066860A (en) * | 2021-02-10 | 2021-07-02 | 华为技术有限公司 | Manufacturing method of dielectric layer of shielded gate field effect transistor and related product |
| CN113299557A (en) * | 2021-06-24 | 2021-08-24 | 绍兴中芯集成电路制造股份有限公司 | Shielded gate field effect transistor and method of forming the same |
| CN116895691A (en) * | 2023-05-31 | 2023-10-17 | 海信家电集团股份有限公司 | Semiconductor device and method for manufacturing the same |
| CN117219500A (en) * | 2023-11-09 | 2023-12-12 | 绍兴中芯集成电路制造股份有限公司 | Integrated structure of transistor device and flash memory and integrated method thereof |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102034712A (en) * | 2009-09-23 | 2011-04-27 | 万国半导体股份有限公司 | Direct contact in trench with three-mask shield gate process |
| CN105244374A (en) * | 2015-08-31 | 2016-01-13 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of groove gate MOSFET possessing shielding gate |
| CN105355548A (en) * | 2015-10-27 | 2016-02-24 | 上海华虹宏力半导体制造有限公司 | Manufacturing method for trench gate MOSFET with shield gate |
| CN105355560A (en) * | 2015-10-27 | 2016-02-24 | 上海华虹宏力半导体制造有限公司 | Manufacturing method for trench gate MOSFET with shield gate |
| CN105702736A (en) * | 2016-01-29 | 2016-06-22 | 上海华虹宏力半导体制造有限公司 | A shield grid oxide layer of a shield grid-deep groove MOSFET and a formation method thereof |
| CN108364870A (en) * | 2018-01-23 | 2018-08-03 | 西安龙腾新能源科技发展有限公司 | Improve the shield grid groove MOSFET manufacturing method of grid oxic horizon quality |
| US20190273157A1 (en) * | 2018-03-01 | 2019-09-05 | Hamza Yilmaz | Self-aligned trench mosfet structures and methods |
-
2020
- 2020-04-07 CN CN202010265601.0A patent/CN111446157A/en not_active Withdrawn
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102034712A (en) * | 2009-09-23 | 2011-04-27 | 万国半导体股份有限公司 | Direct contact in trench with three-mask shield gate process |
| CN105244374A (en) * | 2015-08-31 | 2016-01-13 | 上海华虹宏力半导体制造有限公司 | Manufacturing method of groove gate MOSFET possessing shielding gate |
| CN105355548A (en) * | 2015-10-27 | 2016-02-24 | 上海华虹宏力半导体制造有限公司 | Manufacturing method for trench gate MOSFET with shield gate |
| CN105355560A (en) * | 2015-10-27 | 2016-02-24 | 上海华虹宏力半导体制造有限公司 | Manufacturing method for trench gate MOSFET with shield gate |
| CN105702736A (en) * | 2016-01-29 | 2016-06-22 | 上海华虹宏力半导体制造有限公司 | A shield grid oxide layer of a shield grid-deep groove MOSFET and a formation method thereof |
| CN108364870A (en) * | 2018-01-23 | 2018-08-03 | 西安龙腾新能源科技发展有限公司 | Improve the shield grid groove MOSFET manufacturing method of grid oxic horizon quality |
| US20190273157A1 (en) * | 2018-03-01 | 2019-09-05 | Hamza Yilmaz | Self-aligned trench mosfet structures and methods |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111681962A (en) * | 2020-07-30 | 2020-09-18 | 上海华虹宏力半导体制造有限公司 | Shielding grid power device and manufacturing method thereof |
| CN111681962B (en) * | 2020-07-30 | 2023-06-09 | 上海华虹宏力半导体制造有限公司 | Shielded gate power device and manufacturing method thereof |
| CN113066860A (en) * | 2021-02-10 | 2021-07-02 | 华为技术有限公司 | Manufacturing method of dielectric layer of shielded gate field effect transistor and related product |
| CN113299557A (en) * | 2021-06-24 | 2021-08-24 | 绍兴中芯集成电路制造股份有限公司 | Shielded gate field effect transistor and method of forming the same |
| CN116895691A (en) * | 2023-05-31 | 2023-10-17 | 海信家电集团股份有限公司 | Semiconductor device and method for manufacturing the same |
| CN117219500A (en) * | 2023-11-09 | 2023-12-12 | 绍兴中芯集成电路制造股份有限公司 | Integrated structure of transistor device and flash memory and integrated method thereof |
| CN117219500B (en) * | 2023-11-09 | 2024-04-05 | 绍兴中芯集成电路制造股份有限公司 | Integrated structure of transistor device and flash memory and integrated method thereof |
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