CN111430454B - 一种低饱和电流的绝缘体上硅横向绝缘栅双极型晶体管 - Google Patents
一种低饱和电流的绝缘体上硅横向绝缘栅双极型晶体管 Download PDFInfo
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Abstract
一种低饱和电流的绝缘体上硅横向绝缘栅双极型晶体管,该半导体具备:在P型衬底上设有有埋氧层,在埋氧层上方设有N型漂移区,其上有P型体区、场氧层和集电极区,在P型体区内设有相连的P阱,在P阱内设有P型发射极区,在P型发射极区上设有N型发射极区,在P型体区、P阱、P型发射极区、场氧层和集电极区上方设有氧化层,在场氧层与氧化层之间设有多晶硅栅且延伸至P阱的上方,在P阱、P型体区与多晶硅栅之间设有栅氧化层,所述集电极区包括设在N型漂移区内且被N型漂移区隔离的重掺杂的N型集电极区和轻掺杂的N型集电极区,在重掺杂的N型集电极区内设有轻掺杂的P型集电极区,在轻掺杂的N型集电极区内设有重掺杂的P型集电极区。
Description
技术领域
本发明主要涉及功率半导体器件技术领域,是一种低饱和电流的绝缘体上硅横向绝缘栅双极型晶体管,适用于开关电源、家用电器等诸多集成功率芯片中。
背景技术
绝缘栅双极型晶体管是MOS结构与双极型晶体结构相结合而成的复合型半导体功率器件,它较好结合了MOS管和双极型晶体管的优点。在开关电源、家用电器、智能电网和交通传输等领域应用广泛。其中,绝缘体上硅横向绝缘栅双极型晶体管(SOI-LateralInsulated Gate Bipolar Transistor,SOI-LIGBT)是一种典型的基于SOI工艺的结构,具有易于集成、耐压高、驱动电流能力强、开关速度快等优点,在功率集成电路中得到了广泛应用。
SOI-LIGBT常作为单片集成功率芯片中的核心器件。由于SOI-LIGBT通常在单片集成功率芯片中用作功率开关器件,当SOI-LIGBT工作在开关状态时,如果漂移区中存储的少数载流子抽取速度过慢,会产生拖尾电流,导致器件较大的开关损耗,随着开关频率的增加,开关损耗也会随之增大,导致器件的工作效率降低。此外,当功率器件处于导通状态下,当器件想获得较低的导通电压降Von,则需要增强载流子的注入效率,但是这样会减小安全工作区SOA(Safety Operating Area),同时载流子浓度增大会导致器件开关切换时转换速度降低,进而导致关断损耗增大。所以降低高压器件的导通压降和关断损耗是降低芯片整体功耗的重要措施之一。因此需要少数载流子的阳极注入在通电状态下增强,在关断或短路切换时减弱或理想地消除。这已经在DB-IGBT(Dynamic N-buffer Insulated GateBipolar Transistor)和DT-IGBT(Double Trench Insulated Gate Bipolar Transistor)中实现。然而,这两种器件都需要两个栅极,在关断过程和短路切换过程中,需要对两个栅极的开关信号的时间相位进行精确控制,以获得理想的性能,这使得驱动电路变得复杂。比如在阳极增加额外沟槽的器件,这类结构能有效的缩短关断时间,减少关断损耗,但因为减小了阳极面积,导致注入效率降低,从而增大了导通压降,使得导通压降和关断损耗的折中关系变差。
因此控制SOI-LIGBT的载流子注入效率,使得器件具有较低的导通压降和较小的饱和电流对改善器件性能具有重大意义。
发明内容
本发明针对上述问题,提出了一种低饱和电流的绝缘体上硅横向绝缘栅双极型晶体管,增大了线性电流,降低了饱和电流,改善了器件的导通特性。
本发明采用如下技术方案:
一种低饱和电流的绝缘体上硅横向绝缘栅双极型晶体管,包括:P型衬底,在P型衬底上方设有埋氧层,在埋氧层上方设有N型漂移区,在N型漂移区内设有P型体区、场氧层和集电极区,场氧层位于P型体区和集电极区之间,在P型体区内设有相连的P阱,在P阱内设有P型发射极区,在P型发射极区上设有N型发射极区,在P型体区、P阱、P型发射极区、场氧层和集电极区上方设有氧化层,在场氧层与氧化层之间设有多晶硅栅且多晶硅栅延伸至P阱的上方,在P阱、P型体区与多晶硅栅之间设有栅氧化层,所述集电极区包括设在N型漂移区内且被N型漂移区隔离的重掺杂的N型集电极区和轻掺杂的N型集电极区,在重掺杂的N型集电极区内设有轻掺杂的P型集电极区,在轻掺杂的N型集电极区内设有重掺杂的P型集电极区。
与现有技术相比,本发明具有以下优点:
(1)本发明具有较大的线性电流。传统结构在线性区时,线性电流上升较慢,在相同条件下,本发明结构的线性电流上升较快。本发明的创新点在于将N型集电极区替换成了重掺杂的N型集电极区和轻掺杂的N型集电极区。在器件的栅电极加正压,P型体区和P阱出现反型层,形成电子导电沟道。对集电极加正压时,N型发射极区的电子电流经过电子导电沟道,从N型发射极区流向N型漂移区,到达N型集电极区。电子电流作为PNP晶体管的基极驱动电流,促使空穴从P型集电极区注入N型漂移区,注入的空穴由此形成PNP晶体管的发射极电流。由于重掺杂的P型集电极区下方是轻掺杂的N型集电极区,为了达到载流子的平衡,注入的空穴与轻掺杂的N型集电极区中的电子复合较少,大部分空穴注入漂移区。当电子电流流向集电极时,重掺杂的P型集电极区吸引更多的空穴注入。而重掺杂的N型集电极区使得轻掺杂的P型集电极区的空穴注入效率较低,N型集电极区的轻重掺杂浓度变化使得总的空穴注入增加。线性区时,本发明器件与传统器件相比,因为有轻掺杂的N型集电极区,使得晶体管基极驱动电流增大,能吸引的空穴数目增多,电子-空穴对的产生率大于复合率,注入N型漂移区的空穴数目增多,线性电流上升较快。
(2)本发明具有较小的饱和电流。传统结构在饱和区时,电流较大,在相同条件下,本发明结构的饱和电流较小。本发明的创新点在于将P型集电极区替换成了重掺杂的P型集电极区和轻掺杂的P型集电极区。对集电极加正压时,N型发射极区的电子经过电子导电沟道流向N型集电极区,当器件的电子电流增大到一定程度时,经过沟道的电子数不再增加,轻掺杂的N型集电极区的电子数较多,因此重掺杂的P型集电极区空穴与轻掺杂的N型集电极区的电子复合率增大,导致空穴的注入效率下降,而重掺杂的N型集电极区上方的轻掺杂的P型集电极区的空穴注入效率一直较低,因此总的空穴注入效率较低。本发明器件的饱和电流得到抑制,小于传统结构器件的饱和电流。
(3)本发明的创新点在于将原来的P型集电极区和N型集电极区构成的集电极,换成了由重掺杂的P型集电极区和轻掺杂的N型集电极区构成的第一集电极区、轻掺杂的P型集电极区和重掺杂的N型集电极区构成的第二集电极区。
附图说明
图1所示为传统结构的三维图。
图2所示为传统结构去掉金属电极和氧化层结构的三维图。
图3所示为本发明结构的三维图。
图4所示为本发明结构去掉金属电极和氧化层结构三维图。
图5所示为本发明结构等效图。
图6所示为本发明与传统结构IV对比图。
图7所示为本发明结构去掉金属电极和氧化层的俯视图。
图8所示为本发明与传统结构在VCE=3V时空穴浓度对比图。
图9所示为本发明与传统结构在VCE=10.5V时刻空穴浓度对比图。
图10所示为本发明与传统结构静态BV对比图。
具体实施方式
下面结合图3和图4,对本发明做详细说明,一种低饱和电流的绝缘体上硅横向绝缘栅双极型晶体管,包括:P型衬底1,在P型衬底1上方设有埋氧层2,在埋氧层2上方设有N型漂移区3,在N型漂移区3内的上表面发射极一侧下方设有P型体区4、场氧层9和集电极区,场氧层9位于P型体区4和集电极区之间,在P型体区4内设有相连的P阱5,在P阱5内设有P型发射极区6,在P型发射极区6上设有N型发射极区7,在P型体区4、P阱5、P型发射极区6、场氧层9和集电极区上方设有氧化层12,在场氧层9与氧化层12之间设有多晶硅栅10且多晶硅栅10延伸至P阱5的上方,在P阱5、P型体区4与多晶硅栅10之间设有栅氧化层,所述集电极区包括设在N型漂移区3内且被N型漂移区3隔离的重掺杂的N型集电极区15和轻掺杂的N型集电极区16,在重掺杂的N型集电极区15内设有轻掺杂的P型集电极区8,在轻掺杂的N型集电极区16内设有重掺杂的P型集电极区17。
本实施例还进一步采用以下技术措施:
重掺杂的N型集电极区15的掺杂浓度高于轻掺杂的N型集电极区16,轻掺杂的N型集电极区16的掺杂浓度高于N型漂移区3;轻掺杂的P型集电极区8的掺杂浓度低于P型发射极区6;重掺杂的P型集电极区17的掺杂浓度高于P型发射极区6。例如:重掺杂的N型集电极区15的掺杂浓度为5*1019/cm3,轻掺杂的N型集电极区16的掺杂浓度为3*1017/cm3,N型漂移区的掺杂浓度为8.3*1014/cm3;P型发射极区6的掺杂浓度为2.6*1019/cm3,重掺杂的P型集电极区17的掺杂浓度为5*1019/cm3,轻掺杂的P型集电极区8的掺杂浓度为8*1018/cm3。
在场氧层9上设有多晶硅场板11,在P型发射极区6和N型发射极区7上连接有发射极金属场板13,在P型集电极区8和多晶硅场板11上连接有集电极金属场板14。
本发明的工作原理:
在器件的栅电极加固定的正电压,在正电压作用下,P型体区和P阱出现反型层,形成电子导电沟道。对集电极加正压时,N型发射极区的电子电流经过电子导电沟道,从N型发射极区流向N型漂移区,到达N型集电极区。电子电流作为PNP晶体管的基极驱动电流,促使空穴从P型集电极区注入N型漂移区,注入的空穴由此形成PNP晶体管的发射极电流。本发明器件与传统器件相比,因为N型集电极区分为重掺杂的N型集电极区和轻掺杂的N型集电极区两个区域,使得基极驱动电流改变,能吸引的空穴数目发生变化,注入N型漂移区的空穴数目改变,改变了PNP晶体管的发射极电流。从集电极到发射极的电流由两部分组成,包括经过MOSFET区沟道的单极电子电流部分和流经PNP管的双极电子空穴电流部分,本发明器件使得PNP管的双极电子空穴电流部分发生变化,本发明器件的总电流相对于传统器件先增大后减小。因此本发明器件的线性电流比传统器件大,饱和电流比传统器件小。
如图3所示,本发明将N型集电极区分为重掺杂的N型集电极区和轻掺杂的N型集电极区两个区域。由于新增了轻掺杂的N型集电极区,重掺杂的P型集电极区的空穴注入效率会增加;由于新增了重掺杂的N型集电极区,轻掺杂的P型集电极区的空穴注入效率会减小。如图5所示,本发明中的PNP晶体管由两个PNP晶体管构成,其中重掺杂的P型集电极区、轻掺杂的N型集电极区/N型漂移区和P型体区/P阱形成PNP1,轻掺杂的P型集电极区、重掺杂的N型集电极区/N型漂移区和P型体区/P阱形成PNP2。在集电极电压较小时(线性电流区域),由于PNP2的空穴注入效率低于PNP1,集电极电流主要流过PNP1。由于重掺杂的P型集电极区下方的的轻掺杂的N型集电极区浓度较低,重掺杂的P型集电极区的注入效率高于传统结构,因而本发明结构的导通电压较低。随着集电极电流电压的增大(饱和电流区域),PNP1空穴的注入效率下降,更多的电流流过PNP2,而PNP2管注入效率较低,因此本发明器件的饱和电流得到抑制,小于传统结构器件的饱和电流。
为了验证本发明的好处,本专利通过半导体器件仿真软件Sentaurus Tcad对结构进行了对比仿真,如图6所示。在固定的栅压下,在器件的集电极加正压,得到器件的IV曲线。随着电压的增大,可以看到本发明器件的线性电流大于传统结构的线性电流,当继续增加电压至器件电流达到饱和状态时,本发明器件的饱和电流小于传统结构的饱和电流。图7为本发明结构去掉金属电极和氧化层的俯视图,图7中有两条截线,分别是距离器件下边缘0.5μm的A截线和距离器件上边缘0.5μm的B截线。图8为VCE=3V时,沿器件表面A截线和B截线的空穴浓度对比图。从图8中可看出VCE=3V时,即线性电流时,对于本发明器件的集电极一侧,在B截线处的空穴浓度比A截线处高,即PNP1的空穴注入大于PNP2。并且同一位置,本发明器件的空穴浓度高于传统器件,即本发明的线性电流更大。图9为VCE=10.5V时,沿器件表面A截线和B截线的空穴浓度对比图。从图9中可看出VCE=10.5V时,即饱和电流时,PNP1空穴的注入效率下降,更多的电流流过PNP2,而PNP2管注入效率较低,因此本发明器件的饱和电流得到抑制,而传统器件的A截线和B截线空穴浓度基本一致,总体上本发明器件的饱和电流小于传统结构。图10为本发明器件与传统结构的静态BV对比图,由图可见本发明器件的静态BV大于传统结构,因此能承受更大的击穿电压。
综上所述,本发明器件能够在线性电流区域提高注入效率,获得更低的导通压降;并且在饱和电流区域降低饱和电流,提高器件的性能。
Claims (4)
1.一种低饱和电流的绝缘体上硅横向绝缘栅双极型晶体管,包括:P型衬底(1),在P型衬底(1)上方设有埋氧层(2),在埋氧层(2)上方设有N型漂移区(3),在N型漂移区(3)内设有P型体区(4)、场氧层(9)和集电极区,场氧层(9)位于P型体区(4)和集电极区之间,在P型体区(4)内设有相连的P阱(5),在P阱(5)内设有P型发射极区(6),在P型发射极区(6)上设有N型发射极区(7),在P型体区(4)、P阱(5)、P型发射极区(6)、场氧层(9)和集电极区上方设有氧化层(12),在场氧层(9)与氧化层(12)之间设有多晶硅栅(10)且多晶硅栅(10)延伸至P阱(5)的上方,在P阱(5)、P型体区(4)与多晶硅栅(10)之间设有栅氧化层,其特征在于,所述集电极区包括设在N型漂移区(3)内且被N型漂移区(3)隔离的重掺杂的N型集电极区(15)和轻掺杂的N型集电极区(16),在重掺杂的N型集电极区(15)内设有轻掺杂的P型集电极区(8),在轻掺杂的N型集电极区(16)内设有重掺杂的P型集电极区(17)。
2.根据权利要求1所述的一种低饱和电流的绝缘体上硅横向绝缘栅双极型晶体管,其特征在于,重掺杂的N型集电极区(15)的掺杂浓度高于轻掺杂的N型集电极区(16),轻掺杂的N型集电极区(16)的掺杂浓度高于N型漂移区(3);轻掺杂的P型集电极区(8)的掺杂浓度低于P型发射极区(6);重掺杂的P型集电极区(17)的掺杂浓度高于P型发射极区(6)。
3.根据权利要求1所述的一种低饱和电流的绝缘体上硅横向绝缘栅双极型晶体管,其特征在于,在场氧层(9)上设有多晶硅场板(11)。
4.根据权利要求3所述的一种低饱和电流的绝缘体上硅横向绝缘栅双极型晶体管,其特征在于,在P型发射极区(6)和N型发射极区(7)上连接有发射极金属场板(13),在轻掺杂的P型集电极区(8)和多晶硅场板(11)上连接有集电极金属场板(14)。
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Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015192121A (ja) * | 2014-03-28 | 2015-11-02 | ローム株式会社 | 半導体装置およびその製造方法 |
CN105826367A (zh) * | 2016-03-18 | 2016-08-03 | 东南大学 | 一种大电流绝缘体上硅横向绝缘栅双极型晶体管器件 |
CN107293585A (zh) * | 2017-06-30 | 2017-10-24 | 东南大学 | 一种快关断绝缘体上硅横向绝缘栅双极型晶体管器件 |
CN110034176A (zh) * | 2019-04-22 | 2019-07-19 | 东南大学 | 解决反向恢复失效的逆导型横向绝缘栅双极型晶体管 |
CN110190120A (zh) * | 2019-05-05 | 2019-08-30 | 东南大学 | 一种具有低开启过冲电流的横向绝缘栅双极型晶体管 |
CN110190113A (zh) * | 2019-05-16 | 2019-08-30 | 东南大学 | 一种消除负阻效应的阳极短路型横向绝缘栅双极型晶体管 |
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Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2015192121A (ja) * | 2014-03-28 | 2015-11-02 | ローム株式会社 | 半導体装置およびその製造方法 |
CN105826367A (zh) * | 2016-03-18 | 2016-08-03 | 东南大学 | 一种大电流绝缘体上硅横向绝缘栅双极型晶体管器件 |
CN107293585A (zh) * | 2017-06-30 | 2017-10-24 | 东南大学 | 一种快关断绝缘体上硅横向绝缘栅双极型晶体管器件 |
CN110034176A (zh) * | 2019-04-22 | 2019-07-19 | 东南大学 | 解决反向恢复失效的逆导型横向绝缘栅双极型晶体管 |
CN110190120A (zh) * | 2019-05-05 | 2019-08-30 | 东南大学 | 一种具有低开启过冲电流的横向绝缘栅双极型晶体管 |
CN110190113A (zh) * | 2019-05-16 | 2019-08-30 | 东南大学 | 一种消除负阻效应的阳极短路型横向绝缘栅双极型晶体管 |
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