CN111429954B - Voltage calibration circuit, semiconductor memory structure and voltage calibration method thereof - Google Patents
Voltage calibration circuit, semiconductor memory structure and voltage calibration method thereof Download PDFInfo
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Abstract
The invention provides a voltage calibration circuit, a semiconductor memory structure and a voltage calibration method thereof, wherein the voltage output by the output end of an operational amplifier can be calibrated to an ideal voltage range by adjusting the resistance values of a first adjustable resistor and a second adjustable resistor, and the adjustment mode is simple and controllable; the first adjustable resistor and the second adjustable resistor are adjusted in two steps, and the first signal and the second signal are respectively used as the standard for ending adjustment, so that the judgment is simple; for products produced in large scale, the output voltage of the products can be adjusted in advance before leaving the factory according to different process environments, so that the output function of the products can be always in a reasonable range, and the design pressure of other circuit modules in the products on process drift is eliminated.
Description
Technical Field
The present invention relates to the field of integrated circuit design, and more particularly, to a voltage calibration circuit, a semiconductor memory structure and a voltage calibration method thereof.
Background
The development of artificial intelligence has put higher and higher demands on the computing capability, and the scale and precision and power consumption requirements of the processing data of various artificial intelligence algorithms and architectures such as the existing deep neural network (Deep Neural Networks, DNN), convolutional neural network (ConVolutional Neural Networks, CNN) and impulse neural network (Spiking Neuron Networks, SNN) are higher and higher. To improve the accuracy of the operation, multiple bits of data are often required for storing a single input signal. In the neural network, the operations of multiplying signals and weights and then summing occupy a relatively high proportion of the whole operation, which means that if the multiplication and addition operations are processed in the traditional computing system architecture, a great deal of repeated call of data and weights exists due to separation of the operations and storage, and the operations are lost in time and power consumption.
In recent years, with the development of a novel memory for storing data based on resistance, under the input condition of an analog signal, the conductance of the memory is taken as weight, the input voltage is taken as an input data signal, and finally, a summed current value is obtained on a unified output line, so that the current output value is in linear proportion to the final result of the multiply-add operation, and the multiply-add output value can be obtained through reasonable circuit processing. If this is done, a large number of operations can be performed within the array, i.e., a memory-operation integration is achieved, the speed of the neural network can be significantly increased and power consumption can be reduced.
Fig. 1 is a partial circuit diagram of a conventional integrated semiconductor memory structure. As shown in fig. 1, the semiconductor memory structure includes a memory array and an operational amplifier, where the memory array includes at least one column of memory cells, and each column of memory cells includes a plurality of memory cells. The storage unit comprises a resistance change memory R1 and a switching tube Q1, wherein one end of the resistance change memory Q1 is used for inputting a corresponding input voltage V1, and the other end of the resistance change memory Q1 is connected with one end of the switching tube Q1; the other ends of all the switching tubes Q1 of one row of memory cells are connected and then connected to the reverse input end of the operational amplifier OTA1, and the forward input end of the operational amplifier OTA1 is used for inputting the reference voltage Vref1. And a feedback resistor Rf is connected with the inverting input end and the output end of the operational amplifier OTA1 so as to form negative feedback, the operational amplifier OTA1 converts the current value output by a column of memory cells into a voltage value according to a linear relation through the adjustment of a reference voltage Vrefl, and finally the voltage value is taken as output to participate in calculation. If the memory array is ideal, there will be a common maximum and minimum value for the voltage output by the operational amplifier OTA1 connected to each column of memory cells, and this maximum and minimum value can be taken as the ideal output range. However, in the process manufacturing of an actual memory array, the performance of the memory cells in a region may be guaranteed to be consistent, and there may be a deviation in performance for different chips or memory arrays on different wafers. The output voltage of the memory array on a different chip may deviate from the intended ideal voltage range, which may lead to saturation or distortion of the output result. Therefore, to solve the voltage offset problem, an additional voltage calibration circuit is required to be designed in the semiconductor memory structure, so that the voltage output by the memory array can be maintained in the ideal voltage range.
Disclosure of Invention
The invention aims to provide a voltage calibration circuit, a semiconductor memory structure and a voltage calibration method thereof, which can calibrate the voltage output by a memory array so that the output voltage of the memory array is always in an ideal voltage range.
In order to achieve the above purpose, the invention provides a voltage calibration circuit, which is connected with a column of memory cells, wherein the column of memory cells comprises a plurality of memory cells, the memory cells comprise a resistive random access memory and a switching tube, one end of the resistive random access memory is used for inputting corresponding input voltage, the other end of the resistive random access memory is connected with one end of the switching tube, and the voltage calibration circuit comprises an operational amplifier, a first adjustable resistor, a second adjustable resistor and a protection resistor;
the other ends of all the switching tubes in one row of storage units are connected and then connected to the reverse input end of the operational amplifier, one end of the first adjustable resistor is connected with the reverse input end of the operational amplifier, the other end of the first adjustable resistor is connected with the output end of the operational amplifier, one end of the protection resistor is used for inputting reference voltage, the other end of the protection resistor is connected with the forward input end of the operational amplifier, and one end of the second adjustable resistor is connected with the forward input end of the operational amplifier; and adjusting the resistance values of the first adjustable resistor and the second adjustable resistor to calibrate the voltage output by the output end of the operational amplifier to an ideal voltage range.
Optionally, the memory cells in a column of memory cells are numbered sequentially as 1..n, N is an integer greater than 1, and the voltage V output by the output terminal of the operational amplifier O The following formula is satisfied:
wherein i is the number of the storage unit, i e [1, N ]]，R i Resistance value R of resistive random access memory for memory cell with number i f_bank R is the resistance value of the first adjustable resistor r2_bank R is the resistance value of the second adjustable resistor r1 For the resistance value of the protection resistor, V ref V is the voltage value of the reference voltage i The input voltage corresponding to the memory cell numbered i.
Optionally, the desired voltage range is (V O_Min ～V O_Max ) The resistance value of the first adjustable resistor is adjusted to ensure that the difference value between the maximum value and the minimum value of the voltage output by the output end of the operational amplifier is equal to V O_Max -V O_Min The method comprises the steps of carrying out a first treatment on the surface of the Adjusting the resistance value of the second adjustable resistor to make the maximum value of the voltage output by the output end of the operational amplifier equal to V O_Max And the minimum value of the voltage output by the output end of the operational amplifier is equal to V O_Min 。
The invention also provides a semiconductor memory structure, comprising:
the memory array comprises a plurality of columns of memory cells, wherein each column of memory cells comprises at least two columns of first memory cells and at least one column of second memory cells;
The voltage calibration circuits are correspondingly connected with the first storage units in each row and the second storage units in each row;
the first comparison circuit is used for comparing the difference value of the voltages output by the voltage calibration circuits corresponding to the two columns of first storage units with a first set value and outputting a first signal;
the second comparison circuit is used for comparing the voltage output by the voltage calibration circuit corresponding to any column of the first storage units with a second set value and outputting a second signal;
the logic processing circuit is used for inputting a third signal and a fourth signal into the voltage calibration circuit corresponding to the first storage unit, and inputting the corresponding third signal and fourth signal into the voltage calibration circuit corresponding to the second storage unit when the first signal and the second signal are overturned, wherein the third signal is used for adjusting the resistance value of the first adjustable resistor, and the fourth signal is used for adjusting the resistance value of the second adjustable resistor.
Optionally, the first comparing circuit includes a first comparator, a first resistor, a second resistor, a third resistor and a fourth resistor;
the positive input end of the first comparator is connected with one ends of the first resistor and the second resistor, the other end of the first resistor is connected with the output end of a voltage calibration circuit corresponding to a row of first memory cells, and the other end of the second resistor is grounded;
The reverse input end of the first comparator is connected with one ends of the third resistor and the fourth resistor, the other end of the third resistor is connected with the output end of the voltage calibration circuit corresponding to the other row of first memory cells, and the other end of the fourth resistor is used for inputting the first set voltage.
Optionally, the second comparing circuit includes a second comparator, a positive input end of the second comparator is connected to an output end of the voltage calibration circuit corresponding to any column of the first memory cells, and a negative input end of the second comparator is used for inputting the second set voltage.
Optionally, the second memory cell outputs a desired voltage in the range (V O_Min ～V O_Max ) The first set voltage is equal to V O_Max -V O_Min The method comprises the steps of carrying out a first treatment on the surface of the The second set voltage is V O_Min Or V O_Max 。
Optionally, the logic processing circuit includes a logic controller and a memory;
the logic controller sequentially inputs different third signals and fourth signals to the voltage calibration circuit corresponding to the first storage unit until the first signals and the second signals are overturned, the memory stores the third signals and the fourth signals corresponding to the first signals and the second signals when the first signals and the second signals are overturned, and the third signals and the fourth signals are input to the voltage calibration circuit corresponding to the second storage unit.
The invention also provides a voltage calibration method of the semiconductor memory structure, which comprises the following steps:
the resistance values of a first adjustable resistor and a second adjustable resistor in a voltage calibration circuit corresponding to the first memory unit are adjusted to be minimum, the resistance value of a resistance change memory in one row of the first memory units is adjusted to be maximum, and the resistance value of a resistance change memory in the other row of the first memory units is adjusted to be minimum;
the first comparison circuit is started and the second comparison circuit is closed, the first comparison circuit outputs a first signal, the logic processing circuit outputs different third signals to gradually increase the resistance value of the first adjustable resistor until the first signal is overturned;
the second comparison circuit is started and the first comparison circuit is closed, the second comparison circuit outputs a second signal, and the logic processing circuit outputs a different fourth signal to gradually increase the resistance value of the second adjustable resistor until the second signal is overturned;
and inputting the third signal corresponding to the first signal when the first signal is inverted and the fourth signal corresponding to the second signal when the second signal is inverted into a voltage calibration circuit corresponding to the second memory unit.
Optionally, the third signal and the fourth signal are digital codes corresponding to different resistance values;
The logic processing circuit outputs a third different signal to gradually increase the resistance value of the first adjustable resistor until the first signal is inverted, and the step of inverting the first signal comprises:
the logic processing circuit inputs a digital code to the first adjustable resistor, and when the first signal is not overturned, the logic processing circuit changes the value of the digital code and inputs the value into the first adjustable resistor again until the first signal is overturned;
the logic processing circuit outputs a fourth different signal to gradually increase the resistance value of the second adjustable resistor until the second signal is inverted, and the step of inverting the second signal comprises:
the logic processing circuit inputs a digital code to the second adjustable resistor, and when the second signal is not flipped, the logic processing circuit changes the value of the digital code and inputs the value into the second adjustable resistor again until the first signal is flipped.
The invention has the following beneficial effects:
(1) The voltage output by the output end of the operational amplifier can be calibrated to an ideal voltage range by adjusting the resistance values of the first adjustable resistor and the second adjustable resistor, and the adjusting mode is simple and controllable;
(2) The first adjustable resistor and the second adjustable resistor are adjusted in two steps, and the first signal and the second signal are respectively used as the standard for ending adjustment, so that the judgment is simple;
(3) For products produced in large scale, the output voltage of the products can be adjusted in advance before leaving the factory according to different process environments, so that the output function of the products can be always in a reasonable range, and the design pressure of other circuit modules in the products on process drift is eliminated.
Drawings
FIG. 1 is a partial circuit diagram of a conventional memory cell semiconductor memory structure;
FIG. 2 is a circuit diagram of a voltage calibration circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of an overall semiconductor memory structure according to an embodiment of the present invention;
FIG. 4 is a partial circuit diagram of a semiconductor memory structure provided by an embodiment of the present invention;
FIG. 5a is a circuit diagram of a first comparison circuit according to an embodiment of the present invention;
FIG. 5b is a circuit diagram of a second comparison circuit according to an embodiment of the present invention;
FIG. 6 is a flowchart of a voltage calibration method of a semiconductor memory structure according to an embodiment of the present invention;
wherein, the reference numerals are as follows:
v1-input voltage; r1-a resistance change memory; q1-a switching tube; OTA 1-operational amplifier; rf-feedback resistance; vref1—a reference voltage;
v2-input voltage; r2-resistance random access memory; q2-switching tube; an OTA 2-operational amplifier; r3 is a first adjustable resistor; r4 is a second adjustable resistor; vref 2-reference voltage; r5-protection resistor; the output voltage of the Vo-operational amplifier; r6-a first resistor; r7-a second resistor; r8-a third resistor; r9-fourth resistance;
COMP 1-a first amplifier; COMP 2-second amplifier; a Cell-memory Cell; logical Processor-logic controller; memory-storage; s1-a first signal; s2-a second signal; s3-a third signal; s4-a fourth signal; v (V) Δ -a first set voltage; v (V) a -a second set voltage; mea 1-a first voltage calibration circuit; mea 2-a second voltage calibration circuit; mea 3-third voltage calibration circuit.
Detailed Description
Specific embodiments of the present invention will be described in more detail below with reference to the drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
The terms "first," "second," and the like in the description are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other sequences than described or illustrated herein. Similarly, if a method described herein comprises a series of steps, and the order of the steps presented herein is not necessarily the only order in which the steps may be performed, and some of the described steps may be omitted and/or some other steps not described herein may be added to the method. If a component in one drawing is identical to a component in another drawing, the component will be easily recognized in all drawings, but in order to make the description of the drawings clearer, the specification does not refer to all the identical components in each drawing.
Fig. 2 is a circuit diagram of a voltage calibration circuit according to an embodiment of the invention. As shown in fig. 2, the voltage calibration circuit is connected to a column of memory cells, where a column of memory cells includes a plurality of memory cells (one, two or more memory cells may be all used), each memory cell includes a resistive random access memory R2 and a switching tube Q2, one end of the resistive random access memory R2 is used for inputting a corresponding input voltage V2, and the other end is connected to one end of the switching tube Q2. The voltage calibration circuit comprises an operational amplifier OTA2, a first adjustable resistor R3, a second adjustable resistor R4 and a protection resistor R5, wherein the other ends of all switch tubes Q2 in a row of memory cells are connected and then connected to the reverse input end of the operational amplifier OTA2, so that currents output by all memory cells in the row of memory cells are superposed and then input to the reverse input end of the operational amplifier OTA 2. One end of the first adjustable resistor R3 is connected to the inverting input end of the operational amplifier OTA2, and the other end is connected to the output end of the operational amplifier OTA2, so as to be used as a feedback resistor of the operational amplifier OTA 2. One end of the protection resistor R5 is used for inputting a reference voltage Vref2, the other end of the protection resistor R5 is connected with the positive input end of the operational amplifier OTA2, one end of the second adjustable resistor R4 is connected with the positive input end of the operational amplifier OTA2, and the other end of the second adjustable resistor R4 is grounded.
It should be understood that, in general, a memory cell has a memory area and a peripheral area for controlling the memory area, and the memory area and the peripheral area each have a switching transistor, which in this embodiment is a switching transistor located in the memory area.
The resistive random access memory R2 is provided with a positive end and a negative end, and when current flows from the positive end to the negative end of the resistive random access memory R2, the resistive random access memory R2 is converted from a high-resistance state to a low-resistance state; conversely, when current flows from the negative terminal to the positive terminal of the resistive random access memory R2, the resistive random access memory R2 is switched from a low resistance state to a high resistance state. In this embodiment, the positive terminal of the resistive random access memory R2 is used for inputting a corresponding input voltage V2, and the negative terminal is connected with one terminal of the switching tube Q2. It should be understood that the positive terminal and the negative terminal of the resistive random access memory R2 are not limited to the connection manner in fig. 2, but the positive terminal of the resistive random access memory R2 may be connected to one terminal of the switching tube Q2, and the negative terminal is used for inputting the corresponding input voltage V2.
In this embodiment, the voltage value of the input voltage V2 input at one end of the resistive random access memory R2 may be different.
For ease of description, a number of memory cells in a column of memory cells are numbered 1..N (N is an integer greater than 1) in sequence from left to right, with the memory cells numbered 1, 2, and N being schematically illustrated in FIG. 2. With this connection, the output voltage of the voltage calibration circuit (i.e. the voltage V output at the output of the operational amplifier OTA2 O ) The following formula is satisfied:
wherein i is the number of the storage unit, i e [1, N ]]，R i Resistance value R2 of resistive random access memory R2 of memory cell with number i f_bank For the resistance value of the first adjustable resistor R3, R r2_bank For the resistance value of the second adjustable resistor R4, R r1 The resistance value of the protection resistor R5, V ref V is the voltage value of the reference voltage Vref2 i The input voltage corresponding to the memory cell numbered i.
For process reasons, there may be some deviation in the parameters of the resistive random access memory R2, resulting in the output voltage of the voltage calibration circuit having a voltage range (V OL ～V OH ) And (3) inner part. While the ideal voltage range of the output voltage of the voltage calibration circuit is (V O_Min ～V O_Max ) This voltage range (V OL ～V OH ) May not be in the desired voltage range (V O_Min ～V O_Max ) In, calibration is required.
In this embodiment, as can be seen from the analysis formula (1), when the resistance value of the resistive random access memory, the input voltage V2, and the resistance value of the protection resistor are fixed, the voltage Vo output by the output terminal of the operational amplifier OTA2 is related to the resistance values of the first adjustable resistor R3 and the second adjustable resistor R4. It can be seen that by adjusting the first adjustable resistor R3 and the first adjustable resistor The resistance value of the two adjustable resistors R4 can be used for outputting the voltage V output by the output end of the operational amplifier OTA2 O Calibrated to the desired voltage range.
Specifically, a two-step adjustment method may be adopted, where the first adjustment step is: in the case where the resistance value of the second adjustable resistor R4 is fixed, the resistance value of the first adjustable resistor R3 is adjusted so that the voltage range (V OL ～V OH ) Is of a width (V) to the ideal voltage range (V O_Min ～V O_Max ) Is uniform in width, V after adjustment OH And V is equal to OL The difference being equal to V O_Max And V is equal to O_Min Is the difference of V OH ～V OL ＝V O_Max -V O_Min . The second step of adjusting comprises the following steps: in the case where the resistance value of the first adjustable resistor R3 is fixed, the resistance value of the second adjustable resistor R4 is adjusted so that the voltage range (V OL ～V OH ) Is in a voltage range (V) O_Min ～V O_Max ) Corresponding end points of the V are equal, and after adjustment OH Equal to V O_Max ，V OL Equal to V O_Min In this way, the voltage range (V OL ～V OH ) Calibrated to said ideal voltage range (V O_Min ～V O_Max )。
Based on this, fig. 3 is an overall circuit diagram of the semiconductor memory structure provided in the present embodiment. As shown in fig. 3, the present embodiment provides a semiconductor memory structure, which includes a memory array, a plurality of voltage calibration circuits, a first comparison circuit, a second comparison circuit, and a logic processing circuit. The memory array comprises a plurality of columns of memory cells, wherein each column of memory cells is provided with a plurality of memory cells Cell, and one column of memory cells is correspondingly connected with one voltage calibration circuit.
Specifically, the multi-column memory cell includes two columns of first memory cells (the first column and the second column in fig. 3) and four columns of second memory cells (the third column to the sixth column in fig. 3), where the first memory cells are used for calibration, and the second memory cells are used for storage. Each column of first memory cells includes four memory cells Cell, and each column of second memory cells includes four memory cells Cell. It should be understood that the first memory cell in the present invention is not limited to only two columns, but may be four columns, six columns, eight columns, etc.; the second memory cell is not limited to only four columns, but may be one column, two columns, three columns, five columns, or the like; the memory cells in each column are not limited to four memory cells, but may include one, two, three, five, and so on.
The other ends of all the switching tubes of each column of storage units are connected and then connected to the corresponding voltage calibration circuits, so that the currents output by one column of storage units are superposed and then input into the voltage calibration circuits, and are converted into voltage output by the voltage calibration circuits. For convenience of description, the voltage calibration circuit connected to the first memory cell in the first column of the two columns of the first memory cells is called a first voltage calibration circuit Mea1, the second voltage calibration circuit Mea connected to the first memory cell in the second column of the first memory cells is called a third voltage calibration circuit Mea.
Fig. 4 is a circuit diagram of the whole semiconductor memory structure according to the present embodiment, and fig. 5a is a circuit diagram of a first comparing circuit according to the present embodiment. As shown in fig. 4 and 5a, the first comparing circuit includes a first comparator COMP1, a first resistor R6, a second resistor R7, a third resistor R8, and a fourth resistor R9. The positive input end of the first comparator COMP1 is connected to one ends of the first resistor R6 and the second resistor R7, the other end of the first resistor R6 is connected to the output end of the second voltage calibration circuit Mea, and the other end of the second resistor R7 is grounded; the inverting input terminal of the first comparator COMP1 is connected to one ends of the third resistor R8 and the fourth resistor R9, the other end of the third resistor R8 is connected to the output terminal of the first voltage calibration circuit Mea1, and the other end of the fourth resistor R9 is used for inputting the first set voltage V Δ . The first comparator COMP1 can be used for comparing the difference between the voltages output by the first voltage calibration circuit Mea and the second voltage calibration circuit Mea1 and the first set voltage V Δ A magnitude, and outputs a first signal S1, the first signal S1 being indicative of the first voltage calibration circuit M The voltage output by ea1 and the voltage output by the second voltage calibration circuit Mea2 are different from the first set voltage V Δ Is a size relationship of (a). Specifically, under this connection, the difference between the voltage output by the first voltage calibration circuit Mea and the voltage output by the second voltage calibration circuit Mea is smaller than the first set voltage V Δ When the first signal S1 is low, the resistance of the first adjustable resistor R3 gradually increases, and finally the difference between the voltage output by the first voltage calibration circuit Mea1 and the voltage output by the second voltage calibration circuit Mea is greater than the first set voltage V Δ At this time, the first signal S1 is inverted to a high level.
In this embodiment, the first set voltage V Δ For the width of the desired voltage range, i.e. V Δ ＝V O_Max -V O_Min 。
As an alternative embodiment, the inverting input terminal of the first comparator COMP1 is connected to one ends of the first resistor R6 and the second resistor R7, the other end of the first resistor R6 is connected to the output terminal of the second voltage calibration circuit Mea2, and the other end of the second resistor R7 is grounded; the positive input end of the first comparator COMP1 is connected to one end of the third resistor R8 and one end of the fourth resistor R9, the other end of the third resistor R8 is connected to the output end of the first voltage calibration circuit Mea1, and the other end of the fourth resistor R9 is used for inputting the first set voltage V Δ . At this time, the difference between the voltage output by the first voltage calibration circuit Mea1 and the voltage output by the second voltage calibration circuit Mea is smaller than the first set voltage V Δ When the first signal S1 is at a high level, the resistance value of the first adjustable resistor R3 gradually increases, and finally the difference between the voltage output by the first voltage calibration circuit Mea1 and the voltage output by the second voltage calibration circuit Mea is greater than the first set voltage V Δ At this time, the first signal S1 is inverted to a low level.
Fig. 5b is a circuit diagram of a second comparing circuit according to the present embodiment. As shown in fig. 4 and 5b, the second comparing circuit comprises a second comparator COMP2, theThe positive input end of the second comparator COMP2 is connected to the output end of the first voltage calibration circuit Mea1, and the negative input end of the second comparator is used for inputting the second set voltage V a . The second comparator COMP2 can be used to compare the voltage output by the first voltage calibration circuit Mea1 with the second set voltage V a And outputs a second signal S2, the second signal S2 being indicative of the voltage output by the first voltage calibration circuit Mea2 and the second set voltage V a Is a size relationship of (a). Specifically, under this connection, the voltage output by the first voltage calibration circuit Mea is smaller than the second set voltage V a When the second signal S2 is low, the resistance of the second adjustable resistor R4 gradually increases, and finally the voltage output by the second voltage calibration circuit Mea2 is greater than the second set voltage V a At this time, the second signal S2 is inverted to a high level.
In this embodiment, the second set voltage V a For the end of the desired voltage range, i.e. V a ＝V O_Max 。
It should be understood that the present invention is not limited to connecting the positive input terminal of the second comparator COMP2 to the output terminal of the first voltage calibration circuit Mea1, but the positive input terminal of the second comparator COMP2 may also be connected to the output terminal of the second voltage calibration circuit Mea, and the second set voltage V a ＝V O_Max 。
As an alternative embodiment, the inverting input terminal of the second comparator COMP2 is connected to the output terminal of the first voltage calibration circuit Mea1, and the positive input terminal of the second comparator COMP2 is used for inputting the second set voltage V a . At this time, the voltage output by the first voltage calibration circuit Mea1 is smaller than the second set voltage V a When the second signal S2 is at a high level, the resistance value of the second adjustable resistor R4 gradually increases, and finally the voltage output by the first voltage calibration circuit Mea1 is greater than the second set voltage V a At this time, the second signal S2 is inverted to a low-high level.
With continued reference to fig. 3 and 4, the logic processing circuit includes a logic controller Logical Processor and a Memory, and the logic controller Logical Processor can sequentially input a third signal S3 and a fourth signal S4 to the first voltage calibration circuit Mea1 and the second voltage calibration circuit Mea2, respectively. Specifically, the voltage calibration circuit, the semiconductor memory structure, and the voltage calibration method thereof are input to the first adjustable resistor R3 in the first voltage calibration circuit Mea or the second voltage calibration circuit Mea for adjusting the resistance value of the first adjustable resistor R3, and the fourth signal S4 is input to the second adjustable resistor R4 in the first voltage calibration circuit Mea or the second voltage calibration circuit Mea2 for adjusting the resistance value of the second adjustable resistor R4. The logic controller Logical Processor can adjust the first and second adjustable resistors R3 and R4 to different resistance values each time the third and fourth signals S3 and S4 are different. When the first signal S1 and the second signal S2 are inverted, the Memory stores the third signal S3 and the fourth signal S4 for inverting the first signal S1 and the second signal S2, and inputs the third signal S3 and the fourth signal S4 to the third voltage calibration circuit Mea3 for controlling the resistance values of the first adjustable resistor R3 and the second adjustable resistor R4 in the third voltage calibration circuit Mea to be the same as the resistance values of the first adjustable resistor R3 and the second adjustable resistor R4 for inverting the first signal S1 and the second signal S2.
In this embodiment, the Memory is a register, but the logic processing circuit should not be limited to this, and the logic processing circuit may be replaced by one device capable of implementing the logic controller Logical Processor and the Memory, for example, a flip-flop, etc., and of course, the invention is not limited to the logic processing circuit including two devices, but may be built by three or more logic devices.
Alternatively, the logic controller Logical Processor may be constructed by several logic devices, and the third signal S3 and the fourth signal S4 output by the logic controller may be multi-bit digital codes, where different digital codes correspond to different resistance values. The first adjustable resistor R3 and the second adjustable resistor R4 may be formed by a plurality of sub-resistors and a plurality of switching devices, so that after the first adjustable resistor R3 and the second adjustable resistor R4 receive digital codes, the resistance value can be changed by changing the conduction of a plurality of switches through word transmission codes. Of course, the logic controller Logical Processor, the first resistor R3 and the second resistor R4 may also have other structures and operation modes, which are not illustrated herein.
Fig. 6 is a flowchart of a voltage calibration method of the semiconductor memory structure according to the present embodiment. As shown in fig. 6, the present embodiment further provides a voltage calibration method of the semiconductor memory structure, including:
step L1: the resistance values of a first adjustable resistor and a second adjustable resistor in a voltage calibration circuit corresponding to the first memory unit are adjusted to be minimum, the resistance value of a resistance change memory in one row of the first memory units is adjusted to be maximum, and the resistance value of a resistance change memory in the other row of the first memory units is adjusted to be minimum;
step L2: starting a first comparison circuit, outputting a first signal by the first comparison circuit, and outputting a different third signal by a logic processing circuit to gradually increase the resistance value of the first adjustable resistor until the first signal is overturned;
step L3: starting a second comparison circuit, outputting a second signal by the second comparison circuit, and outputting a different fourth signal by a logic processing circuit to gradually increase the resistance value of the second adjustable resistor until the second signal is overturned;
step L4: and inputting the third signal corresponding to the first signal when the first signal is inverted and the fourth signal corresponding to the second signal when the second signal is inverted into a voltage calibration circuit corresponding to the second memory unit.
Specifically, referring to fig. 2, 3 and 4, step L1 is first performed. The resistance values of the first adjustable resistor R3 and the second adjustable resistor R4 in the first voltage calibration circuit Mea and the second voltage calibration circuit Mea are both adjusted to be minimum (within an adjustable range). Then the resistance change memories R2 in all the memory cells of the first column of the first memory cells are all programmed to a high resistance state, so thatThe resistance of each memory cell in the first column of the first memory cells is the highest, and at this time, the output current is the smallest due to the highest resistance value of each memory cell, the voltage V output by the first voltage calibration circuit Mea1 O Reaching a minimum, i.e. V O ＝V OL The method comprises the steps of carrying out a first treatment on the surface of the The resistance change memories R2 in all the memory cells of the first memory cells of the second column are all programmed to be in a low resistance state, so that the resistance of each memory cell in the first memory cells of the second column is the lowest, at this time, the output current is the largest due to the lowest resistance value of each memory cell, and the voltage output by the second voltage calibration circuit Mea2 is the highest, namely V O ＝V OH 。
Step L2 is then performed. Turning on the first comparator COMP1 and turning off the second comparator COMP2, the first comparator COMP1 starts comparing (V OH -V OL ) With the first set voltage V Δ Thereby outputting the first signal S1, at which time the first signal S1 must be at a low level (according to the wiring method of fig. 4). The logic controller Logical Processor then begins to output a different third signal S3 to successively increase the resistance value of the first resistor R3 (the resistance value of the second resistor R4 remains unchanged) until the first signal S1 toggles high. When the first signal S1 is inverted to a high level, the (V OH -V OL )＝V Δ That is, V OH And V is equal to OL The difference being equal to V O_Max And V is equal to O_Min Is the difference between the voltage range (V OL ～V OH ) Is of a width (V) to the ideal voltage range (V O_Min ～V O_Max ) Is uniform in width. Then, the Memory stores the third signal S3 corresponding to the first signal S1 when it is inverted. Step L3 is then performed. Turning on the second comparator COMP2 and turning off the first comparator COMP1, the second comparator COMP2 will start comparing V OL And the second set voltage V a Thereby outputting the second signal S2. This time take the second set voltage V a Is V (V) O_MIN At this timeThe second signal S2 must be low (according to the wiring method of fig. 4). The logic controller Logical Processor then begins to output a different fourth signal S4 to successively increase the resistance value of the second resistor R4 (the resistance value of the first resistor R3 remains unchanged) until the second signal S2 toggles high. When the second signal S2 is turned to a high level, the voltage V OL ＝V O_MIN . Then, the Memory stores the fourth signal S4 corresponding to the second signal S2 when it is inverted.
In this embodiment, the third signal S3 is a digital code for controlling the resistance value of the first adjustable resistor R3, and the fourth signal S4 is a digital code for controlling the resistance value of the second adjustable resistor R4. Taking 3-bit digital codes as an example, the resistance values of the first adjustable resistor R3 and the second adjustable resistor R4 have eight shift positions, the resistance values of the first adjustable resistor R3 and the second adjustable resistor R4 corresponding to the digital codes 000 are set to be minimum, the resistance values of the first adjustable resistor R3 and the second adjustable resistor R4 corresponding to the digital codes 111 are set to be maximum, and the resistance values of the first adjustable resistor R3 and the second adjustable resistor R4 corresponding to the digital codes 000-111 are set to be gradually increased. In step L1, when the resistance values of the first adjustable resistor R3 and the second adjustable resistor R4 are adjusted to be minimum values, the third signal S3 and the fourth signal S4 are the digital codes 000, and when the resistance values of the first adjustable resistor R3 and the second adjustable resistor R4 are gradually increased, the logic processing circuit Logical Processor increases 1 on the basis of the original digital codes each time until the first signal S1 and the second signal S2 are inverted. Taking the first adjustable resistor R3 as an example, in the step L1, after the digital code 000 is input into the first adjustable resistor R3, the resistance value of the first adjustable resistor R3 is the lowest, in the step L2, the logic processing circuit Logical Processor inputs the digital code 001 into the first adjustable resistor R3, the resistance value of the first adjustable resistor R3 is increased to the resistance value corresponding to the digital code 001, and at this time, if the first signal S1 is turned over, the Memory stores the digital code 001; if the first signal S1 is not inverted, the logic processing circuit Logical Processor inputs the digital code 010 to the first resistor R3 and then checks whether the first signal S1 is inverted. Different digital codes are sequentially input to the first adjustable resistor R3, so that the digital codes turned over by the first signal S1 are stored, and the adjustment of the second adjustable resistor R4 is also referred to the adjustment of the first adjustable resistor R3, and will not be repeated here.
Of course, the correspondence between the digital code and the resistance value of the first adjustable resistor R3 or the second adjustable resistor R4 is not limited thereto, and may be designed according to practical situations.
It will be appreciated that when the second comparator COMP2 is connected to the second voltage calibration circuit Mea2, the second comparator COMP2 is used to compare V OH And the second set voltage V a At this time, the second set voltage V is taken a Is V (V) O_Max . When the second signal S2 is inverted to a high level, V OH ＝V O_Max The same effect can be achieved.
After two adjustments, the voltage output by the first voltage calibration circuit Mea1 and the voltage range (V) output by the second voltage calibration circuit Mea2 OL ～V OH ) I.e. the ideal voltage range (V O_Min ～V O_Max )。
It should be understood that, in this embodiment, the resistance values of the first adjustable resistor R3 and the second adjustable resistor R4 are both found in a small-to-large manner to control the third signal S3 and the fourth signal S4 that the first signal S1 and the second signal S2 turn over, but as an alternative embodiment, the resistance values of the first adjustable resistor R3 and the second adjustable resistor R4 may be in a small-to-large manner, or one of the first adjustable resistor R3 and the second adjustable resistor R4 is in a small-to-large manner, and at this time, the logic and the direction of the circuit may be redesigned as needed, which is not illustrated herein.
Finally, step L4 is performed. A third signal S3 and a fourth signal S stored in the Memory4 are input into the third voltage calibration circuit Mea3 such that the resistance value of the first adjustable resistor R3 and the resistance value of the second adjustable resistor R4 in the third voltage calibration circuit Mea3 are identical to the resistance value of the first adjustable resistor R3 and the resistance value of the second adjustable resistor R4 of the first voltage calibration circuit Mea1 (and the second voltage calibration circuit Mea 2), thereby making the voltage range (V OL ～V OH ) Is also within the desired voltage range (V O_Min ～V O_Max ) Calibration of the output voltage of the memory array is achieved.
In summary, the voltage calibration circuit, the semiconductor memory structure and the voltage calibration method thereof provided by the embodiment can calibrate the voltage output by the output end of the operational amplifier to an ideal voltage range by adjusting the resistance values of the first adjustable resistor and the second adjustable resistor, and the adjustment mode is simple and controllable; the first adjustable resistor and the second adjustable resistor are adjusted in two steps, and the first signal and the second signal are respectively used as the standard for ending adjustment, so that the judgment is simple; for products produced in large scale, the output voltage of the products can be adjusted in advance before leaving the factory according to different process environments, so that the output function of the products can be always in a reasonable range, and the design pressure of other circuit modules in the products on process drift is eliminated.
The foregoing is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any person skilled in the art will make any equivalent substitution or modification to the technical solution and technical content disclosed in the invention without departing from the scope of the technical solution of the invention, and the technical solution of the invention is not departing from the scope of the invention.
Claims (9)
1. A semiconductor memory structure, comprising:
the storage array comprises a plurality of columns of storage units, each column of storage units comprises a plurality of storage units, each storage unit comprises a resistance change memory and a switch tube, one end of the resistance change memory is used for inputting corresponding input voltage, the other end of the resistance change memory is connected with one end of the switch tube, and each column of storage units comprises at least two columns of first storage units and at least one column of second storage units;
the voltage calibration circuits are correspondingly connected with each column of first storage units and each column of second storage units, each voltage calibration circuit comprises an operational amplifier, a first adjustable resistor, a second adjustable resistor and a protection resistor, the other ends of all switch tubes in one column of storage units are connected and then connected to the reverse input end of the operational amplifier, one end of each first adjustable resistor is connected with the reverse input end of the operational amplifier, the other end of each first adjustable resistor is connected with the output end of the operational amplifier, one end of each protection resistor is used for inputting a reference voltage, the other end of each protection resistor is connected with the positive input end of the operational amplifier, one end of each second adjustable resistor is connected with the positive input end of the operational amplifier, the other end of each second adjustable resistor is grounded, and the voltage output by the output end of the operational amplifier is calibrated into an ideal voltage range by adjusting the resistance values of the first adjustable resistor and the second adjustable resistor;
The first comparison circuit is used for comparing the difference value of the voltages output by the voltage calibration circuits corresponding to the two columns of first storage units with a first set value and outputting a first signal;
the second comparison circuit is used for comparing the voltage output by the voltage calibration circuit corresponding to any column of the first storage units with a second set value and outputting a second signal;
the logic processing circuit is used for inputting a third signal and a fourth signal into the voltage calibration circuit corresponding to the first storage unit, and inputting the corresponding third signal and fourth signal into the voltage calibration circuit corresponding to the second storage unit when the first signal and the second signal are overturned, wherein the third signal is used for adjusting the resistance value of the first adjustable resistor, and the fourth signal is used for adjusting the resistance value of the second adjustable resistor.
2. The semiconductor memory structure according to claim 1, wherein memory cells in a column of memory cells are numbered in order of 1 … N, N being an integer greater than 1, and the voltage Vo output from the output terminal of the operational amplifier satisfies the following formula:
wherein i is the number of the storage unit, i e [1, N ] ]，R i Resistance value R of resistive random access memory for memory cell with number i f_bank R is the resistance value of the first adjustable resistor r2_bank R is the resistance value of the second adjustable resistor r1 For the resistance value of the protection resistor, V ref V is the voltage value of the reference voltage i The input voltage corresponding to the memory cell numbered i.
3. The semiconductor memory structure according to claim 1 or 2, wherein the ideal voltage range is (V O_Min ～V O_Max ) The resistance value of the first adjustable resistor is adjusted to ensure that the difference value between the maximum value and the minimum value of the voltage output by the output end of the operational amplifier is equal to V O_Max -V O_Min The method comprises the steps of carrying out a first treatment on the surface of the Adjusting the resistance value of the second adjustable resistor to make the maximum value of the voltage output by the output end of the operational amplifier equal to V O_Max And the minimum value of the voltage output by the output end of the operational amplifier is equal to V O_Min 。
4. The semiconductor memory structure according to claim 1, wherein the first comparison circuit includes a first comparator, a first resistor, a second resistor, a third resistor, and a fourth resistor;
the positive input end of the first comparator is connected with one ends of the first resistor and the second resistor, the other end of the first resistor is connected with the output end of a voltage calibration circuit corresponding to a row of first memory cells, and the other end of the second resistor is grounded;
The reverse input end of the first comparator is connected with one ends of the third resistor and the fourth resistor, the other end of the third resistor is connected with the output end of the voltage calibration circuit corresponding to the other row of first storage units, and the other end of the fourth resistor is used for inputting a first set voltage.
5. The semiconductor memory structure according to claim 4, wherein the second comparator circuit includes a second comparator, a positive input terminal of the second comparator is connected to an output terminal of the voltage calibration circuit corresponding to any one of the first memory cells, and a negative input terminal of the second comparator is used for inputting a second set voltage.
6. The semiconductor memory structure according to claim 5, wherein the second memory cell outputs an ideal voltage in the range of (V O_Min ～V O_Max ) The first set voltage is equal to V O_Max -V O_Min The method comprises the steps of carrying out a first treatment on the surface of the The second set voltage is V O_Min Or V O_Max 。
7. The semiconductor memory structure of claim 1, wherein the logic processing circuit comprises a logic controller and a memory;
the logic controller sequentially inputs different third signals and fourth signals to the voltage calibration circuit corresponding to the first storage unit until the first signals and the second signals are overturned, the memory stores the third signals and the fourth signals corresponding to the first signals and the second signals when the first signals and the second signals are overturned, and the third signals and the fourth signals are input to the voltage calibration circuit corresponding to the second storage unit.
8. A voltage calibration method of a semiconductor memory structure according to any one of claims 1 to 7, comprising:
the resistance values of a first adjustable resistor and a second adjustable resistor in a voltage calibration circuit corresponding to the first memory unit are adjusted to be minimum, the resistance value of a resistance change memory in one row of the first memory units is adjusted to be maximum, and the resistance value of a resistance change memory in the other row of the first memory units is adjusted to be minimum;
the first comparison circuit is started and the second comparison circuit is closed, the first comparison circuit outputs a first signal, the logic processing circuit outputs different third signals to gradually increase the resistance value of the first adjustable resistor until the first signal is overturned;
the second comparison circuit is started and the first comparison circuit is closed, the second comparison circuit outputs a second signal, and the logic processing circuit outputs a different fourth signal to gradually increase the resistance value of the second adjustable resistor until the second signal is overturned;
and inputting the third signal corresponding to the first signal when the first signal is inverted and the fourth signal corresponding to the second signal when the second signal is inverted into a voltage calibration circuit corresponding to the second memory unit.
9. The method of voltage calibration of a semiconductor memory structure according to claim 8, wherein the third signal and the fourth signal are each digital codes corresponding to different resistance values;
the logic processing circuit outputs a third different signal to gradually increase the resistance value of the first adjustable resistor until the first signal is inverted, and the step of inverting the first signal comprises:
the logic processing circuit inputs a digital code to the first adjustable resistor, and when the first signal is not overturned, the logic processing circuit changes the value of the digital code and inputs the value into the first adjustable resistor again until the first signal is overturned;
the logic processing circuit outputs a fourth different signal to gradually increase the resistance value of the second adjustable resistor until the second signal is inverted, and the step of inverting the second signal comprises:
the logic processing circuit inputs a digital code to the second adjustable resistor, and when the second signal is not flipped, the logic processing circuit changes the value of the digital code and inputs the value into the second adjustable resistor again until the first signal is flipped.
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| CN105976022A (en) * | 2016-04-27 | 2016-09-28 | 清华大学 | Circuit structure, artificial neural network and method of simulating synapse using circuit structure |
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| JP2015115083A (en) * | 2013-12-12 | 2015-06-22 | マイクロン テクノロジー， インク． | Semiconductor device |
| CN105976022A (en) * | 2016-04-27 | 2016-09-28 | 清华大学 | Circuit structure, artificial neural network and method of simulating synapse using circuit structure |
| CN107919154A (en) * | 2017-12-11 | 2018-04-17 | 睿力集成电路有限公司 | A kind of input/output driver calibration circuit, method and semiconductor memory |
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