CN114330694A - Circuit and method for realizing convolution operation - Google Patents
Circuit and method for realizing convolution operation Download PDFInfo
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Abstract
The invention provides a circuit for realizing convolution operation, which comprises a coding module, a digital-to-analog conversion module, a memory array, a reference array, an adjusting module, a symbol column processing module and a calculating module, wherein the coding module is used for coding a code sequence; the coding module is used for acquiring sign bit and weight coding; the digital-to-analog conversion module is used for converting an input digital signal into a voltage signal; the memory array is used for mapping the weight codes and outputting a first current signal; the adjusting module is used for acquiring the first current signal according to the first current signal; the symbol column processing module is used for acquiring a symbol column and outputting a symbol column output value; the calculation module is used for acquiring a convolution output value. The circuit for realizing the convolution operation saves the number of memories, reduces the complexity of the convolution operation and improves the efficiency and the accuracy of the convolution operation. The invention also provides a method for realizing convolution operation.
Description
Technical Field
The invention relates to the field of digital circuits and analog circuits, in particular to a circuit and a method for realizing convolution operation.
Background
A convolutional neural network is implemented by a Resistive Random Access Memory (RRAM) circuit, and input and weight (weight) of the neural network need to be quantized. The input of the RRAM circuit is generally a positive number, and the upper layer thereof is an activation function, and can be first quantized into a positive integer, and then converted into a voltage through a digital-to-analog converter to be used as the input of the circuit. weight generally has a positive or negative value, and the methods for mapping to the conductivity of RRAM generally have the following: firstly, an asymmetric quantization algorithm is adopted, weight is quantized into a positive integer and then is directly mapped into RRAM conductivity, an additional circuit is required to be added to process a shift factor, and the circuit complexity is increased; secondly, a symmetric quantization algorithm is adopted to quantize the weight into an integer (positive or negative), and a RRAM pair method is used for representing positive and negative values, so that the method needs a large number of memories, and the circuit complexity and the circuit cost are increased.
Therefore, it is necessary to provide a circuit and a method for implementing convolution operation to solve the above-mentioned problems in the prior art.
Disclosure of Invention
The invention aims to provide a circuit and a method for realizing convolution operation, which are used for solving the problem that a circuit for realizing the convolution neural network operation needs more memories.
In order to achieve the above object, the circuit for implementing convolution operation of the present invention includes an encoding module, a digital-to-analog conversion module, a memory array, an adjustment module, a symbol column processing module and a calculation module;
the coding module is used for acquiring sign bits according to the range of the quantized weight signals and coding the quantized weight signals to obtain weight codes;
the digital-to-analog conversion module is used for converting an externally input digital signal into a voltage signal and transmitting the voltage signal to the memory array to be used as the input of the memory array;
the memory array is used for mapping the weight codes, and after receiving the voltage signals, each column of the memory array outputs a first current signal;
the adjusting module is used for acquiring a first output signal according to the first current signal;
the symbol column processing module is used for acquiring a symbol column according to the symbol bit, wherein the symbol column is a column where the symbol bit is located in the memory array, and outputting a symbol column output value according to the symbol column and the first output signal;
and the calculation module is used for acquiring a convolution output value according to the symbol column output value and the first output signal.
The circuit for realizing convolution operation has the advantages that:
coding the quantized weight signal through the coding module to obtain weight codes and obtain sign bits; the adjusting module is used for obtaining a first output signal, the symbol column processing module is used for obtaining a symbol column, and a symbol column output value is output according to the symbol column and the first output signal, so that the memory array can map positive integer weights and negative integer weights, the method of a resistance variable memory pair is not needed for representing the positive and negative values of the weights, the number of memories is saved, the problem that a circuit for realizing convolutional neural network operation needs more resistance variable memories is solved, the complexity of convolutional operation is reduced, and the efficiency and the accuracy of the convolutional operation are improved.
Optionally, the memory array includes a plurality of convolution kernel mapping units, each convolution kernel mapping unit maps one of the weight codes, each convolution kernel mapping unit includes one of the symbol columns and a plurality of non-symbol columns, and the symbol columns and the non-symbol columns respectively output the first current signals.
Optionally, the symbol column processing module is connected to an output end of the symbol column, and configured to perform an inverse number operation on the first output signal output by the symbol column to output the symbol column output value. The method has the advantages that after the symbol column is obtained through the symbol column processing module, the first output signal output by the symbol column is subjected to inverse number taking operation to output the output value of the symbol column, so that the memory array can map positive integer weight and negative integer weight, the number of memories is saved, the complexity of convolution operation is reduced, the efficiency and accuracy of convolution operation are improved, and the area and cost of a circuit board are saved.
Optionally, the symbol column and the non-symbol column each include m first storage units, and m is a positive integer;
all the first storage units in the same row are connected and receive the input voltage signal;
all the first memory cells of the same column are connected.
Optionally, the circuit for implementing convolution operation further includes a reference array, the reference array is connected to the output end of the digital-to-analog conversion module to receive the voltage signal, the output end of the reference array is connected to the adjustment module, and the output end of the adjustment module is connected to the symbol column processing module;
the adjusting module adjusts the first current signal through the reference current signal to obtain the first output signal.
Optionally, the reference array includes m second storage units distributed in a column, where m is a positive integer, and each second storage unit is connected to the first storage unit in the same row.
Optionally, the adjusting module includes a current subtraction circuit, a first current-to-voltage conversion unit, and a first analog-to-digital conversion unit;
the input end of the current subtraction circuit is connected with the current output end of the memory array and the current output end of the reference array, and the current subtraction circuit is used for respectively performing subtraction operation on the first current signal output by each column of the memory array and the reference current signal so as to output a plurality of second current signals;
the input end of the first current-to-voltage conversion unit is connected with the output end of the current subtraction circuit, and the first current-to-voltage conversion unit is used for converting the second current signal into a first voltage signal;
the input end of the first analog-to-digital conversion unit is connected with the output end of the first current-to-voltage conversion unit, and the first analog-to-digital conversion unit is used for performing analog-to-digital signal conversion on the first voltage signal to output the first output signal. The method has the advantages that as the first current signal output by each column of the memory array is equal to the multiply-add result of the voltage and the conductivity of the memory cells in the current column, the first current signal influences the first output signal, and the first output signal influences the final output value of the convolution operation, the leakage current generated by the memory array influences the final output value of the convolution operation, and the leakage current is the current generated by the high-resistance memory cells in the memory array; the current subtraction circuit respectively performs subtraction on the first current signal output by each column of the memory array and the reference current signal to output a plurality of second current signals, so that leakage current in the memory array is reduced, and the influence of the leakage current on the first output signal is weakened, thereby avoiding the influence of the leakage current generated in the memory array on a convolution operation result, and improving the accuracy of the convolution operation.
Optionally, the adjusting module includes a second current to voltage converting unit, a third current to voltage converting unit, a second analog-to-digital converting unit, a third analog-to-digital converting unit, and a digital domain subtractor;
the input end of the second current-to-voltage conversion unit is connected with the current output end of the memory array, the output end of the second current-to-voltage conversion unit is connected with the input end of the second analog-to-digital conversion unit, the second current-to-voltage conversion unit is used for converting the first current signal into a second voltage signal, and the second analog-to-digital conversion unit is used for converting the second voltage signal into a first digital signal;
the input end of the third current-to-voltage conversion unit is connected with the current output end of the reference array, the output end of the third current-to-voltage conversion unit is connected with the input end of the third analog-to-digital conversion unit, the third current-to-voltage conversion unit is used for converting the reference current signal into a third voltage signal, and the third analog-to-digital conversion unit is used for converting the third voltage signal into a second digital signal;
the output end of the second analog-to-digital conversion unit is connected with the first input end of the digital domain subtracter, the output end of the third analog-to-digital conversion unit is connected with the second input end of the digital domain subtracter, and the digital domain subtracter is used for performing subtraction operation on the first digital signal and the second digital signal to output the first output signal. The voltage converter has the advantages that the first current signal and the reference current signal are converted into a second voltage signal and a third voltage signal through the second current-to-voltage conversion unit and the third current-to-voltage conversion unit respectively, and the second voltage signal and the third voltage signal are converted into a first digital signal and a second digital signal through the second analog-to-digital conversion unit and the third analog-to-digital conversion unit respectively; and performing subtraction operation on the first digital signal and the second digital signal through the digital domain subtracter to output the first output signal, so that leakage current in the memory array is reduced, the influence of the leakage current on a final result of convolution operation is weakened, and the accuracy of the convolution operation is improved.
The invention also provides a method for realizing convolution operation, which comprises the following steps:
acquiring sign bits according to the range of the quantized weight signals, and coding the quantized weight signals to obtain weight codes;
mapping the weight encodings through a memory array;
converting an input digital signal into a voltage signal to serve as an input voltage signal of the memory array, so that each column of the memory array outputs a first current signal;
acquiring a first output signal according to the first current signal;
obtaining a symbol column according to the symbol bit, wherein the symbol column is a column in which the symbol bit is positioned in the memory array, and outputting a symbol column output value according to the symbol column and the first output signal;
and acquiring a convolution output value according to the symbol column output value and the first output signal.
The method for realizing the convolution operation has the advantages that:
obtaining a weight code by encoding the quantized weight signal and obtaining a sign bit, and mapping the weight code through a memory array; causing each column of the memory array to output a first current signal by converting an input digital signal to a voltage signal as an input voltage signal of the memory array; acquiring a first output signal according to the first current signal; acquiring a symbol column according to the symbol bit, and outputting a symbol column output value according to the symbol column and the first output signal; obtaining a convolution output value according to the symbol column output value and the first output signal; the positive integer weight and the negative integer weight are mapped through the memory array, so that the number of memories is saved, and the convolution operation efficiency and accuracy are improved.
Optionally, the step of obtaining a first output signal according to the first current signal includes:
setting a reference current signal to adjust the first current signal to obtain the first output signal.
Optionally, the step of setting a reference current signal to adjust the first current signal to obtain a first output signal includes:
respectively performing subtraction operation on the first current signal output by each column of the memory array and the reference current signal to obtain a plurality of second current signals;
converting the second current signal into a first voltage signal;
performing analog-to-digital signal conversion on the first voltage signal to output the first output signal. The method has the advantages that the influence of the leakage current on the convolution operation result is weakened, and the accuracy of the convolution operation is improved.
Optionally, the step of setting a reference current signal to adjust the first current signal to obtain a first output signal includes:
converting the first current signal into a second voltage signal, and converting the second voltage signal into a first digital signal;
converting the reference current signal into a third voltage signal, and converting the third voltage signal into a second digital signal;
performing a subtraction operation on the first digital signal and the second digital signal to output the first output signal.
Drawings
FIG. 1 is a block diagram of a circuit for performing convolution operations according to an embodiment of the present invention;
FIG. 2 is a circuit diagram of a circuit for performing convolution operations according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating a convolution operation according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of an adjustment module in a first implementation manner according to an embodiment of the present disclosure;
FIG. 5 is a schematic diagram of a current subtraction circuit according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of an adjustment module in a second implementation manner of the embodiment of the present invention;
FIG. 7 is a flowchart of a method for performing convolution operations according to an embodiment of the present invention;
FIG. 8 is a flowchart of obtaining a first output signal according to a first implementation of an embodiment of the invention;
fig. 9 is a flowchart of acquiring a first output signal in a second implementation manner of the embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below, and it is obvious that the described embodiments are a part of the embodiments of the present invention, but not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and similar words are intended to mean that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items.
To solve the problems in the prior art, an embodiment of the present invention provides a circuit for implementing convolution operation, and fig. 1 is a block diagram of the circuit for implementing convolution operation according to the embodiment of the present invention.
Referring to fig. 1, the circuit for implementing convolution operation of the present invention includes an encoding module 1, a digital-to-analog conversion module 5, a memory array 2, an adjustment module 4, a symbol column processing module 6, and a calculation module 7;
the coding module 1 is configured to obtain a sign bit according to a range of a quantized weight signal, and code the quantized weight signal to obtain a weight code;
the digital-to-analog conversion module 5 is configured to convert an externally input digital signal into a voltage signal, and transmit the voltage signal to the memory array 2 to serve as an input voltage signal of the memory array 2;
the memory array 2 is used for mapping the weight codes, and after receiving the input voltage signal, each column of the memory array 2 outputs a first current signal;
the adjusting module 4 is configured to obtain a first output signal according to the first current signal;
the symbol column processing module 6 is configured to obtain a symbol column according to the symbol bit and the first output signal, where the symbol column is a column in which the symbol bit is located in the memory array 2, and output a symbol column output value according to the symbol column and the first output signal;
the calculation module 7 is configured to obtain a convolution output value according to the symbol column output value and the first output signal.
The circuit for realizing convolution operation has the advantages that: the quantized weight signal is coded through the coding module 1 to obtain weight codes, and sign bits are obtained; the adjustment module 4 is used for obtaining a first output signal, the symbol column processing module 6 is used for obtaining a symbol column, and a symbol column output value is output according to the symbol column and the first output signal, so that the memory array 2 can map positive integer weights and negative integer weights, the positive and negative values of the weights are represented by a method without using a resistance variable memory pair, the number of memories is saved, the problem that a circuit for realizing convolutional neural network operation needs more resistance variable memories is solved, the complexity of convolutional operation is reduced, and the efficiency and accuracy of convolutional operation are improved.
Fig. 2 is a circuit diagram of a circuit for implementing convolution operation according to an embodiment of the present invention.
In some embodiments, referring to fig. 1 and fig. 2, the encoding module 1 is configured to encode the quantized weight signal to obtain a weight code, and the step of obtaining a sign bit according to the range of the quantized weight signal includes:
the quantized integer weight (weight) is coded as:
wherein: w is quantized weight, k is the number of resistance states of RRAM, Wi∈[0,k-1]W is to beiMapping to corresponding resistance values so that weight is represented by RRAM, n represents the number of RRAM needed for mapping one weight, then m weight needs RRAM of m rows and n columns to represent, and m is a positive integer; determining the value of u (i) according to the value of i, wherein the calculation formula of u (i) is as follows:
else indicates that i is an integer other than j, j is a designated sign bit, and the position of the sign bit is determined according to the range of the weight signal.
In some embodiments, the step of determining the sign bit according to the range of the weight signal comprises:
when the quantization precision of the weight signal is 8 bits (i.e. 8 RRAMs are used to map one weight, n is 8) and the number of resistance states of the RRAM is 2 (i.e. k is 2), the original range of the weight signal can be considered as [0, 28-1]Shifting the data range of the weight signal to a data range having a positive integer and a negative integer;
if W ∈ [ -127, 128], the step size is calculated as: 0- (-127) ═ 255-;
obviously 127 ═ 27-1＝28-129，27Since the number is closest to 127 and greater than 127, the sign bit j equals 7, and the specific value can be expressed as:
-127＝(-1)0×1×20+(-1)0×0×21+(-1)0×0×22+(-1)0×0×23+(-1)0×0×24+(-1)0×0×25+(-1)0×0×26+(-1)1×1×27；
40＝(-1)0×0×20+(-1)0×0×21+(-1)0×0×22+(-1)0×1×23+(-1)0×0×24+(-1)0×1×25+(-1)0×0×26+(-1)1×0×27；
similarly, if W ∈ [ -6, 249], the sign bit j ═ 3 can be calculated, and 40 can be expressed as:
40＝(-1)0×0×20+(-1)0×0×21+(-1)0×0×22+(-1)1×1×23+(-1)0×1×24+(-1)0×1×25+(-1)0×0×26+(-1)0×0×27。
as an alternative embodiment of the present invention, referring to fig. 2, the memory array 2 includes a plurality of convolution kernel mapping units 20, each convolution kernel mapping unit 20 maps one of the weight codes, each convolution kernel mapping unit 20 includes one of the symbol columns 201 and a plurality of non-symbol columns, and the symbol columns 201 and the non-symbol columns output the first current signals respectively, where the non-symbol columns are columns of the convolution kernel mapping units 20 except the symbol columns 201.
As an optional implementation manner of the present invention, each of the symbol column 201 and the non-symbol column includes m first storage units 202, where m is a positive integer;
all the first memory cells 202 in the same row are connected and receive the input voltage signal;
all the first memory cells 202 of the same column are connected.
In some embodiments, the first memory cell 202 is an RRAM, and the resistance state of the RRAM is not limited to two resistance states, i.e., high resistance and low resistance, and may be a multi-resistance state RRAM. For example, a binary RRAM has only two states of high resistance and low resistance, which can represent 0 and 1, and the number of resistance states of the RRAM at this time is 2;
the multi-level RRAM has intermediate states in addition to the high resistance state and the low resistance state, for example, resistance values of one multi-level RRAM are 6000 Ω, 600 Ω, 300 Ω, and 200 Ω, which may respectively represent 0, 1, 2, and 3 in sequence, and the number of resistance states of the multi-level RRAM is 4.
In some embodiments, the conductivity of the RRAM is related to the input voltage and output current as follows:
wherein R is the resistance value of the RRAM, G is the conductivity of the RRAM, I is the output current of the RRAM, and U is the input voltage of the RRAM;
as can be seen from the above formula, after the conversion of the memory array 2, the final output current of each row of RRAM is the first current signal, and the final output current value of each convolution kernel mapping unit 20 is equal to the result of the multiplication and addition of the input voltages of all rows of RRAM and the conductivity of the current row of RRAM; because the input voltage of the RRAM corresponds to the input digital signal and the first current signal is converted by the analog-to-digital converter and corresponds to the convolution output value, different positive integer weights and negative integer weights can be mapped through RRAM arrays with different conductivities.
In this application, a coding rule is further set, where the coding rule is: the mapping range of all the RRAMs in the symbol column is larger than the range of the weight signal, so that one weight signal can be mapped by an array formed by fewer RRAMs, namely one weight signal can be represented by fewer RRAMs, the number of the RRAMs and the chip area are saved, and the power consumption is saved.
Fig. 3 is a schematic diagram of convolution operation according to an embodiment of the present invention, where Input is a convolution Input digital signal, weight is a weight signal, and output is a convolution output digital signal.
In some embodiments, referring to fig. 2 and 3, the weights of the convolutions are 1 and-2, j is 0, k is 2, and 1 is encoded: 1 (-4) × 0+2 × 0+1 × 1, and-2 is encoded: -2 ═ 4 × 1+2 × 1+1 × 0;
mapping the weight to an RRAM array, wherein m is 2, n is 3, mapping the weight through a memory array 2, wherein the memory array 2 comprises a plurality of rows of RRAMs, and each RRAM comprises a high-resistance RRAM and a low-resistance RRAM; setting the conductivity of the low-resistance RRAM to be 1, and mapping a number 1 through the low-resistance RRAM; setting the conductivity of the high-resistance RRAM to be 0.1, and mapping a number 0 through the high-resistance RRAM;
convolution Input digital signals Input are 1 and 2, and 1 is converted into a voltage signal through a digital-to-analog conversion module 5 and then Input into all the first storage units 202 in the first row to serve as Input voltages of the first storage units 202 in the first row; the voltage signal 2 is converted into a voltage signal by the digital-to-analog conversion module 5 and then input to the first memory cell 202 in the second row, where the voltage signal is used as the input voltage of the first memory cell 202 in the second row.
In some embodiments, the Digital-to-Analog Converter module 5 of the present invention is a Digital-to-Analog Converter (DAC), and converts an externally input Digital signal into a voltage signal through the DAC, so as to serve as an input of the memory array 2.
In some embodiments, referring to fig. 1 and fig. 2, the circuit for implementing convolution operation further includes a reference array 3, the reference array 3 is connected to the output end of the digital-to-analog conversion module 5 to receive the voltage signal, the output end of the reference array 3 is connected to the adjustment module 4, and the output end of the adjustment module 4 is connected to the symbol column processing module;
the adjusting module 4 adjusts the first current signal by the reference current signal to obtain the first output signal.
As an alternative embodiment of the present invention, the reference array 3 includes m second memory units 30 distributed in a column, and the number of rows of the first memory units 202 is the same as the number of rows of the second memory units 30, and is m rows. M is a positive integer, and each of the second memory cells 30 is connected to the first memory cell 202 in the same row.
In some embodiments, the second memory cell 30 is a RRAM, specifically, the second memory cell 30 is a high resistance RRAM with a conductivity of 0.1.
In the existing RRAM technology, the current output by the high-resistance RRAM cannot be reduced to 0, so that the reference current generated by the high-resistance RRAM of the reference array 3 reduces the leakage current output in the memory array 1, and weakens the influence of the leakage current on the convolution output result, so as to better map the weight signal, thereby improving the accuracy of the mapped weight signal.
Fig. 4 is a schematic structural diagram of an adjustment module in a first implementation manner according to an embodiment of the present invention, and fig. 5 is a schematic structural diagram of a current subtraction circuit 40 according to an embodiment of the present invention; i in FIGS. 4 and 5 is the second current signal, IsingalA first current signal, I, output for each column of first memory cells output by the memory array 2refIs the reference current signal output by the reference array 3.
In some alternative embodiments of the present invention, referring to fig. 4, the adjusting module 4 includes a current subtraction circuit 40, a first current-to-voltage unit 41, and a first analog-to-digital conversion unit 42;
the input end of the current subtraction circuit 40 is connected to the current output end of the memory array 2 and the current output end of the reference array 3, and the current subtraction circuit 40 is configured to perform subtraction on the first current signal output by each column of the memory array 2 and the reference current signal output by the reference array 3 respectively to output a plurality of second current signals;
an input end of the first current-to-voltage unit 41 is connected to an output end of the current subtraction circuit 40, and the first current-to-voltage unit 41 is configured to convert the second current signal into a first voltage signal;
an input end of the first analog-to-digital conversion unit 42 is connected to an output end of the first current-to-voltage conversion unit 41, and the first analog-to-digital conversion unit 42 is configured to perform analog-to-digital signal conversion on the first voltage signal to output the first output signal. The method has the advantages that because the convolution input digital signal is converted into a voltage signal to be used as the voltage input of the memory array 2, and because the first current signal output by each column of the memory array 2 is equal to the multiplication and addition result of the voltage and the conductivity of the memory cells of the current column, the first current signal influences the first output signal, and the first output signal influences the final output value of the convolution operation, the leakage current generated by the memory array 2 influences the final output value of the convolution operation, and the leakage current is the current generated by the high-resistance memory cells in the memory array; the current subtraction circuit 40 performs subtraction on the first current signal output by each column of the memory array 2 and the reference current signal to output a plurality of second current signals, so as to reduce the influence of leakage current on the first output signal, thereby avoiding the influence of leakage current generated in the memory array 2 on the convolution operation result, and improving the accuracy of the convolution operation.
As an alternative embodiment of the present invention, referring to fig. 5, the current subtraction circuit 40 includes a current mirror, the current mirror includes an adjustment current output terminal, a first NMOS transistor 411 and a second NMOS transistor 412, a drain of the first NMOS transistor 411 is connected to the current output terminal of the memory array 2 to receive the first current signal, a node between the drain of the first NMOS transistor 411 and the current output terminal of the memory array 2 is connected to the adjustment current output terminal, a current mirror output terminal is further disposed between the drain of the first NMOS transistor 411 and the current output terminal of the memory array 2 to output the second current signal, a gate of the first NMOS transistor 411 is connected to a gate of the second NMOS transistor 412, and a source of the first NMOS transistor 411 is connected to a source of the second NMOS transistor 412;
the drain of the second NMOS transistor 412 is connected to the current output terminal of the reference array 3 to receive the reference current signal, and the drain of the second NMOS transistor 412 is shorted to the gate;
the first NMOS transistor 411 is controlled to operate in a saturation region, so that the second current signal is output from the regulated current output terminal.
In some embodiments, referring to fig. 5, the drain of the first NMOS transistor 411 receives the first current signal I output by each column in the memory array 2singalThe drain of the second NMOS transistor 412 receives the reference current signal I output by the reference array 3refThe calculation formula of the second current signal I output by the adjustment current output end is as follows:
I＝Isingal-Iref
wherein I is a second current signal, IsingalA first current signal, I, output for each column of first memory cells output by the memory array 2refIs the reference current signal output by the reference array 3.
FIG. 6 is a structural schematic diagram of an adjustment module in a second implementation manner of the embodiment of the present invention; in the figure IsingalA first current signal, I, output for each column of first memory cells output by the memory array 2refIs the reference current signal output by the reference array 3.
In further alternative embodiments of the present invention, referring to fig. 6, the adjusting module includes a second current to voltage unit 43, a third current to voltage unit 44, a second analog-to-digital conversion unit 45, a third analog-to-digital conversion unit 46, and a digital domain subtractor 47;
the input end of the second current-to-voltage conversion unit 43 is connected to the current output end of the memory array 2, the output end of the second current-to-voltage conversion unit 43 is connected to the input end of the second analog-to-digital conversion unit 45, and the output end of the second analog-to-digital conversion unit 45 is connected to the first input end of the digital domain subtractor 47;
the input end of the third current-to-voltage conversion unit 44 is connected to the current output end of the reference array 3, the output end of the third current-to-voltage conversion unit 44 is connected to the input end of the third analog-to-digital conversion unit 46, and the output end of the third analog-to-digital conversion unit 46 is connected to the second input end of the digital domain subtractor 47.
As an alternative embodiment of the present invention, referring to fig. 6, the second current-to-voltage converting unit 43 is configured to convert the first current signal into a second voltage signal, and the second analog-to-digital converting unit 45 is configured to convert the second voltage signal into a first digital signal;
the third current-to-voltage unit 44 is configured to convert the reference current signal into a third voltage signal, and the third analog-to-digital conversion unit 46 is configured to convert the third voltage signal into a second digital signal;
the digital domain subtractor 47 is configured to perform a subtraction operation on the first digital signal and the second digital signal to output the first output signal. The first current signal and the reference current signal are converted into a second voltage signal and a third voltage signal by the second current-to-voltage converting unit 43 and the third current-to-voltage converting unit 44, respectively, and the second voltage signal and the third voltage signal are converted into a first digital signal and a second digital signal by the second analog-to-digital converting unit 45 and the third analog-to-digital converting unit 46, respectively; the digital domain subtracter 47 performs subtraction operation on the first digital signal and the second digital signal to output the first output signal, so that the leakage current in the memory array 2 is removed, the influence of the leakage current on the final result of the convolution operation is weakened, and the accuracy of the convolution operation is improved.
It can be said that the present invention provides two embodiments of the adjusting module, and in actual operation, if circuit performance is not considered, any one circuit of the two adjusting modules can be selected;
the adjusting module can also be selected in a compromise mode according to the requirements of the energy consumption, the area and the like of the circuit, so that the performance of the circuit for realizing the convolution operation is improved.
In some embodiments, referring to fig. 4 and fig. 6, the first current-to-voltage unit 41, the second current-to-voltage unit 43, and the third current-to-voltage unit 44 may adopt a current-to-voltage circuit, specifically, by controlling a current to charge and discharge a capacitor, so as to convert the current into a voltage across the capacitor, and achieve the purpose of converting a current signal into a voltage signal, where the calculation formula of the conversion is as follows:
where I is the current to be switched, T is the time to charge the capacitive device, and C is the capacitance value.
In some embodiments, referring to fig. 4 and 6, the first Analog-to-Digital conversion unit 42, the second Analog-to-Digital conversion unit 45, and the third Analog-to-Digital conversion unit 46 are all Analog-to-Digital converters (ADCs) for converting voltage signals into Digital signals.
As an alternative embodiment of the present invention, referring to fig. 2, the symbol column processing module 6 is connected to the output end of the symbol column 201, and is configured to perform an inverse operation on the first output signal output by the symbol column 201 to output the output value of the symbol column 201. The method has the advantages that after the symbol column 201 is obtained through the symbol column processing module 6, the first output signal output by the symbol column 201 is subjected to inverse number taking operation to output the output value of the symbol column 201, so that the memory array 2 can map positive integer weight and negative integer weight, the number of memories is saved, the complexity of convolution operation is reduced, the convolution operation efficiency and accuracy are improved, and the area and cost of a circuit board are saved.
In some embodiments, the step of performing an inverse operation on the first output signal output by the symbol column 201 to output the output value of the symbol column 201 comprises:
the value of the first output signal is often expressed in a complementary form in a computer, and performing an inverse operation on the first output signal is equivalent to multiplying the first output signal by-1; when the first output signal corresponding to the symbol row 201 is subjected to the inverse number operation by the binary logic operation circuit, it is equivalent to calculate the complement of the inverse number of the first output signal corresponding to the symbol row 201, that is, the inverse code is taken and 1 is added on the basis of the complement of the first output signal corresponding to the symbol row 201.
In some embodiments, the symbol column processing module 6 includes a verilog language generation circuit in a digital domain, which is configured to perform an inverse number operation on the first output signal output by the symbol column 201 to output the output value of the symbol column 201.
In some embodiments, referring to fig. 2, the calculation module 7 includes several first adders 71 and second adders 72, and each convolution kernel mapping unit 20 corresponds to one of the first adders 71;
the first adder 71 is connected to the output end of the symbol column processing module 6, and is configured to perform a weighted sum operation on the symbol column 201 output value and the first output signal corresponding to each convolution kernel mapping unit 20 to obtain a weighted value;
the second adder 72 is connected to all the first adders 71, and configured to sum the weighted values output by all the first adders 71 to obtain the convolution output value. The method has the advantages that the calculation module 7 performs weighted summation operation on the symbol column 201 output value and the first output signal corresponding to each convolution kernel mapping unit 20 to obtain a weighted value, and performs summation operation on the weighted values output by all the first adders 71 to obtain the convolution output value, so that the complete convolution calculation of the circuit for realizing convolution operation of the invention is realized.
In other embodiments, referring to fig. 2, the calculating module 7 may further include a total adder (not shown in the figure), which is connected to the output terminals of all the symbol column processing modules 6, and configured to receive all the output values of the symbol columns 201 and the first output signal to perform weighted summation, although one total adder for performing the weighted summation calculation may increase the pressure of the calculating module 7 to prolong the calculation time, but may save the chip area and the cost. One or more adders may be provided to calculate the final convolution output value according to actual needs.
FIG. 7 is a flowchart of a method for performing convolution operations according to an embodiment of the present invention.
Referring to fig. 7, the present invention further provides a method for implementing convolution operation, including the steps of:
s1: acquiring sign bits according to the range of the quantized weight signals, and coding the quantized weight signals to obtain weight codes;
s2: mapping the weight encodings through a memory array;
s3: converting an input digital signal into a voltage signal to serve as an input voltage signal of the memory array, so that each column of the memory array outputs a first current signal;
s4: acquiring a first output signal according to the first current signal;
s5: obtaining a symbol column according to the symbol bit, wherein the symbol column is a column in which the symbol bit is positioned in the memory array, and outputting a symbol column output value according to the symbol column and the first output signal;
s6: and acquiring a convolution output value according to the symbol column output value and the first output signal.
The method for realizing the convolution operation has the advantages that: obtaining a weight code by encoding the quantized weight signal and obtaining a sign bit, and mapping the weight code through a memory array; causing each column of the memory array to output a first current signal by converting an input digital signal to a voltage signal as an input voltage signal of the memory array; adjusting the first current signal by setting a reference current signal to obtain a first output signal; acquiring a symbol column according to the symbol bit, and outputting a symbol column output value according to the symbol column and the first output signal; obtaining a convolution output value according to the symbol column output value and the first output signal; the positive integer weight and the negative integer weight are mapped through the memory array, so that the number of memories is saved, and the convolution operation efficiency and accuracy are improved.
In step S2, the memory array includes t convolution kernel mapping units, each convolution kernel mapping unit maps a weight using n resistive random access memory units, where t and n are positive integers;
the resistive random access memory unit comprises a high resistance RRAM and a low resistance RRAM, wherein the conductivity of the high resistance RRAM is smaller than that of the low resistance RRAM, the high resistance RRAM is used for mapping a number 0, and the low resistance RRAM is used for mapping a number 1.
In some embodiments, in step S1, the obtaining sign bits according to the range of the quantized weight signals, and the encoding the quantized weight signals to obtain the weight codes includes:
the quantized integer weight (weight) is coded as follows:
wherein: w is quantized weight, k is the number of resistance states of RRAM, i is a positive integer, Wi∈[0,k-1]W is to beiMapping to a corresponding resistance value so that weight is expressed by RRAM, n denotes the number of RRAM required for mapping one weight; determining the value of u (i) according to the value of i, wherein the calculation formula of u (i) is as follows:
else indicates that i takes an integer other than j, j is a designated sign bit, and the position of the sign bit is determined according to the range of W.
In some embodiments, the step of S2 includes:
referring to fig. 1 and 2, weights of convolutions are 1 and-2, where 1 is represented by-1 (-4) × 0+2 × 0+1 × 1, and-2 is represented by-2 (-4) × 1+2 × 1+1 × 0, when a sign bit j is 2;
mapping the weight into an RRAM memory array, wherein m is 2, n is 3, mapping the weight through the RRAM array, and setting the conductivity of the low-resistance RRAM to be 1 through a low-resistance RRAM mapping number 1 with reference to FIG. 1; mapping a digit 0 through a high-resistance RRAM, wherein the conductivity of the high-resistance RRAM is 0.1;
the step of step S3 includes:
convolution Input digital signals Input are 1 and 2, and after the 1 is converted into a voltage signal through a digital-to-analog converter, the voltage signal is Input into the RRAM of the first row and is used as the Input voltage of the RRAM of the first row; converting the voltage signal 2 into a voltage signal through a digital-to-analog converter, and inputting the voltage signal into the RRAM of the second row to be used as the input voltage of the RRAM of the second row;
after the conversion of the memory array, the final output current value of each row of RRAM is equal to the multiplication and addition result of the input voltage of the current row of RRAM and the conductivity of the current row of RRAM, so that the final output current value of each row of RRAM is the first current signal.
In step S4, the step of obtaining a first output signal according to the first current signal includes: setting a reference current signal to adjust the first current signal to obtain a first output signal.
Fig. 8 is a flowchart of acquiring a first output signal in the first implementation manner of the embodiment of the present invention.
In some embodiments, referring to fig. 8, setting the reference current signal to adjust the first current signal to obtain the first output signal includes:
s401: respectively performing subtraction operation on the first current signal output by each column of the memory array and the reference current signal to obtain a plurality of second current signals;
s402: converting the second current signal into a first voltage signal;
s403: performing analog-to-digital signal conversion on the first voltage signal to output the first output signal. The method has the advantages that the influence of the leakage current on the convolution operation result is weakened, and the accuracy of the convolution operation is improved.
Fig. 9 is a flowchart of acquiring a first output signal in a second implementation manner of the embodiment of the invention.
In other embodiments, referring to fig. 9, the step of setting the reference current signal to adjust the first current signal to obtain the first output signal comprises:
s411: converting the first current signal into a second voltage signal, and converting the second voltage signal into a first digital signal;
s412: converting the reference current signal into a third voltage signal, and converting the third voltage signal into a second digital signal;
s413: performing a subtraction operation on the first digital signal and the second digital signal to output the first output signal.
As an alternative embodiment of the present invention, in step S5, the step of outputting a symbol sequence output value according to the symbol sequence and the first output signal includes:
and performing an inverse operation on the first output signal output by the symbol column to output the symbol column output value. The memory array has the advantages that the processing of the output numerical values of the symbol columns is realized, so that the memory array can map positive integer weights and negative integer weights, the requirement on the number of memory cells is reduced, the chip area is saved, and the cost of convolution operation is reduced.
In some embodiments, the step S6 of obtaining the convolution output value according to the symbol column output value and the first output signal includes:
performing a weighted summation operation on the symbol column output values and the first output signal to obtain weighting values, and performing a summation operation on all the weighting values to obtain the convolution output values.
Although the embodiments of the present invention have been described in detail hereinabove, it is apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it is to be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the following claims. Moreover, the invention as described herein is capable of other embodiments and of being practiced or of being carried out in various ways.
Claims (12)
1. A circuit for realizing convolution operation is characterized by comprising a coding module, a digital-to-analog conversion module, a memory array, an adjusting module, a symbol column processing module and a calculating module;
the coding module is used for acquiring sign bits according to the range of the quantized weight signals and coding the quantized weight signals to obtain weight codes;
the digital-to-analog conversion module is used for converting an externally input digital signal into a voltage signal and transmitting the voltage signal to the memory array to be used as the input of the memory array;
the memory array is used for mapping the weight codes, and after receiving the voltage signals, each column of the memory array outputs a first current signal;
the adjusting module is used for acquiring a first output signal according to the first current signal;
the symbol column processing module is used for acquiring a symbol column according to the symbol bit, wherein the symbol column is a column where the symbol bit is located in the memory array, and outputting a symbol column output value according to the symbol column and the first output signal;
and the calculation module is used for acquiring a convolution output value according to the symbol column output value and the first output signal.
2. The circuit for performing convolution operations according to claim 1, wherein the memory array includes a plurality of convolution kernel mapping units, each of the convolution kernel mapping units maps one of the weight codes, each of the convolution kernel mapping units includes one of the symbol columns and a plurality of non-symbol columns, and the symbol columns and the non-symbol columns respectively output the first current signals.
3. The circuit for performing convolution operations of claim 2 wherein the symbol column processing module is coupled to the output of the symbol column for performing an inverse operation on the first output signal output by the symbol column to output the symbol column output value.
4. The circuit for performing convolution operations according to claim 2 wherein said sign column and said non-sign column each include m first storage cells, said m being a positive integer;
all the first storage units in the same row are connected and receive the input voltage signal;
all the first memory cells of the same column are connected.
5. The circuit for performing convolution operations according to claim 4, further comprising a reference array, wherein the reference array is connected to the output of the digital-to-analog conversion module for receiving the voltage signal, the output of the reference array is connected to the adjustment module, and the output of the adjustment module is connected to the symbol column processing module;
the adjusting module adjusts the first current signal through the reference current signal to obtain the first output signal.
6. The circuit for performing convolution operations according to claim 5, wherein the reference array includes m second storage units distributed in a column, wherein m is a positive integer, and each of the second storage units is connected to the first storage unit in the same row.
7. The circuit for performing convolution operations of claim 4 wherein the adjustment module includes a current subtraction circuit, a first current to voltage unit, and a first analog to digital conversion unit;
the input end of the current subtraction circuit is connected with the current output end of the memory array and the current output end of the reference array, and the current subtraction circuit is used for respectively performing subtraction operation on the first current signal output by each column of the memory array and the reference current signal so as to output a plurality of second current signals;
the input end of the first current-to-voltage conversion unit is connected with the output end of the current subtraction circuit, and the first current-to-voltage conversion unit is used for converting the second current signal into a first voltage signal;
the input end of the first analog-to-digital conversion unit is connected with the output end of the first current-to-voltage conversion unit, and the first analog-to-digital conversion unit is used for performing analog-to-digital signal conversion on the first voltage signal to output the first output signal.
8. The circuit for performing convolution operations according to claim 4, wherein the adjustment module comprises a second current-to-voltage unit, a third current-to-voltage unit, a second analog-to-digital conversion unit, a third analog-to-digital conversion unit, and a digital domain subtractor;
the input end of the second current-to-voltage conversion unit is connected with the current output end of the memory array, the output end of the second current-to-voltage conversion unit is connected with the input end of the second analog-to-digital conversion unit, the second current-to-voltage conversion unit is used for converting the first current signal into a second voltage signal, and the second analog-to-digital conversion unit is used for converting the second voltage signal into a first digital signal;
the input end of the third current-to-voltage conversion unit is connected with the current output end of the reference array, the output end of the third current-to-voltage conversion unit is connected with the input end of the third analog-to-digital conversion unit, the third current-to-voltage conversion unit is used for converting the reference current signal into a third voltage signal, and the third analog-to-digital conversion unit is used for converting the third voltage signal into a second digital signal;
the output end of the second analog-to-digital conversion unit is connected with the first input end of the digital domain subtracter, the output end of the third analog-to-digital conversion unit is connected with the second input end of the digital domain subtracter, and the digital domain subtracter is used for performing subtraction operation on the first digital signal and the second digital signal to output the first output signal.
9. A method for performing convolution operations, comprising the steps of:
acquiring sign bits according to the range of the quantized weight signals, and coding the quantized weight signals to obtain weight codes;
mapping the weight encodings through a memory array;
converting an input digital signal into a voltage signal to serve as an input voltage signal of the memory array, so that each column of the memory array outputs a first current signal;
acquiring a first output signal according to the first current signal;
obtaining a symbol column according to the symbol bit, wherein the symbol column is a column in which the symbol bit is positioned in the memory array, and outputting a symbol column output value according to the symbol column and the first output signal;
and acquiring a convolution output value according to the symbol column output value and the first output signal.
10. The method of claim 9, wherein obtaining a first output signal from the first current signal comprises:
setting a reference current signal to adjust the first current signal to obtain the first output signal.
11. The method of claim 10, wherein setting a reference current signal adjusts the first current signal to obtain the first output signal comprises:
respectively performing subtraction operation on the first current signal output by each column of the memory array and the reference current signal to obtain a plurality of second current signals;
converting the second current signal into a first voltage signal;
performing analog-to-digital signal conversion on the first voltage signal to output the first output signal.
12. The method of claim 10, wherein setting a reference current signal adjusts the first current signal to obtain the first output signal comprises:
converting the first current signal into a second voltage signal, and converting the second voltage signal into a first digital signal;
converting the reference current signal into a third voltage signal, and converting the third voltage signal into a second digital signal;
performing a subtraction operation on the first digital signal and the second digital signal to output the first output signal.
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| CN114677548A (en) * | 2022-05-26 | 2022-06-28 | 之江实验室 | Neural network image classification system and method based on resistive random access memory |
| WO2023123973A1 (en) * | 2021-12-31 | 2023-07-06 | 上海集成电路装备材料产业创新中心有限公司 | Circuit and method for realizing convolution operation |
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| CN109460817B (en) * | 2018-09-11 | 2021-08-03 | 华中科技大学 | Convolutional neural network on-chip learning system based on nonvolatile memory |
| CN112686364B (en) * | 2019-10-18 | 2023-12-08 | 华为技术有限公司 | Neural network computing chip and computing method |
| CN112686373B (en) * | 2020-12-31 | 2022-11-01 | 上海交通大学 | Memristor-based online training reinforcement learning method |
| CN113222131B (en) * | 2021-04-30 | 2022-09-06 | 中国科学技术大学 | Synapse array circuit capable of realizing signed weight coefficient based on 1T1R |
| CN114330694A (en) * | 2021-12-31 | 2022-04-12 | 上海集成电路装备材料产业创新中心有限公司 | Circuit and method for realizing convolution operation |
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| WO2023123973A1 (en) * | 2021-12-31 | 2023-07-06 | 上海集成电路装备材料产业创新中心有限公司 | Circuit and method for realizing convolution operation |
| CN114677548A (en) * | 2022-05-26 | 2022-06-28 | 之江实验室 | Neural network image classification system and method based on resistive random access memory |
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