CN111415696A - Method for screening one-time programmable memory chip - Google Patents
Method for screening one-time programmable memory chip Download PDFInfo
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- CN111415696A CN111415696A CN202010196359.6A CN202010196359A CN111415696A CN 111415696 A CN111415696 A CN 111415696A CN 202010196359 A CN202010196359 A CN 202010196359A CN 111415696 A CN111415696 A CN 111415696A
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- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
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Abstract
The invention discloses a method for screening one-time programmable memory chips, and belongs to the technical field of CMOS integrated circuits. Programming and verifying the redundant row of the one-time programmable memory chip through a programmer, and eliminating the chips failed in verification; carrying out empty chip check on the one-time programmable memory chip, and removing chips failed in check; programming and verifying the redundant column of the one-time programmable memory chip through a programmer, and eliminating the chips failed in verification; carrying out empty chip check on the one-time programmable memory chip again, and removing the chip failed in check; dynamically aging the one-time programmable memory chip to induce the chip with potential defects to fail early; and carrying out whole-chip reading and checking, and rejecting the chip with the error. The method provided by the invention can effectively remove the chips with process defects or unqualified parameters, and has high application value.
Description
Technical Field
The invention relates to the technical field of CMOS (complementary metal oxide semiconductor) integrated circuits, in particular to a method for screening one-time programmable memory chips.
Background
In the design of one-time programmable memories, devices are often difficult to test due to the one-time programmable nature of the devices. Therefore, designers usually design built-in test circuits to test the programmability, functions and performance of chips, and hope to reject chips with defects or unqualified parameters early in the screening stage. However, due to the importance of the one-time programmable device in the aerospace field, the one-time programmable device belongs to a device which is strictly prohibited by China and technology abroad, few manufacturers develop the device at home, and no effective screening means exists.
Disclosure of Invention
The invention aims to provide a method for effectively screening one-time programmable memory chips so as to effectively test and screen the one-time programmable memory chips.
In order to solve the above technical problem, the present invention provides a method for screening a one-time programmable memory chip, comprising:
programming and verifying the redundant row of the one-time programmable memory chip through a programmer, and eliminating the chips failed in verification;
carrying out empty chip check on the one-time programmable memory chip, and removing chips failed in check;
programming and verifying the redundant column of the one-time programmable memory chip through a programmer, and eliminating the chips failed in verification;
carrying out empty chip check on the one-time programmable memory chip again, and removing the chip failed in check;
dynamically aging the one-time programmable memory chip to induce the chip with potential defects to fail early;
and carrying out whole-chip reading and checking, and rejecting the chip with the error.
Optionally, the one-time programmable memory chip includes:
a user storage area for user storage information; the storage area comprises word lines, bit lines, storage units, power lines and ground lines;
the test array is used for testing through programming and reading operations; the test array comprises redundant rows and redundant columns; the redundancy row comprises two rows of storage units, word lines, bit lines, power lines and ground lines in a redundancy row area; the redundant column comprises two columns of storage units, word lines, bit lines, power lines and ground lines in a redundant column area;
a programming and reading circuit which is opposite to the redundant row with the user memory area therebetween;
and a word line driver which is opposite to the redundant column through the user memory area.
Optionally, the programming and verifying the redundant row of the one-time programmable memory chip by the programmer includes:
from the column perspective of the redundant row, each column in the redundant row has 2 memory cells, at least 1 of which is programmed, but from the whole redundant row, the memory cells in the redundant row can not be programmed completely; if the verification fails, the chip is removed.
Optionally, the programming and verifying the redundant column of the one-time programmable memory chip by the programmer includes:
from the perspective of the row of the redundant column, each row in the redundant column has 2 memory cells, at least 1 of which is programmed, but from the perspective of the redundant column as a whole, all the memory cells in the redundant column cannot be programmed; if the verification fails, the chip is removed.
Optionally, the dynamically aging the one-time programmable memory chip includes:
periodically reading the user memory area and periodically reading the test array such that the read path has a "0 → 1" or "1 → 0" variation, i.e., the burn-in process covers the read path.
Optionally, performing full-slice read verification includes:
and reading and checking the data of the test array and the data of the user storage area, and if the content is wrong, rejecting the chip.
Optionally, the checking for the empty chip includes checking whether data in the user storage area changes, and if the data in the user storage area changes, the chip is removed.
The invention provides a method for screening a one-time programmable memory chip, which is characterized in that a programmer is used for programming and verifying redundant rows of the one-time programmable memory chip, and chips with failed verification are eliminated; carrying out empty chip check on the one-time programmable memory chip, and removing chips failed in check; programming and verifying the redundant column of the one-time programmable memory chip through a programmer, and eliminating the chips failed in verification; carrying out empty chip check on the one-time programmable memory chip again, and removing the chip failed in check; dynamically aging the one-time programmable memory chip to induce the chip with potential defects to fail early; and carrying out whole-chip reading and checking, and rejecting the chip with the error.
The invention has the following beneficial effects:
(1) the integrity of word lines and column lines in a user storage area is detected by reasonable layout and matching with a specific programming code and a testing means, and circuits with process defects are effectively removed;
(2) the read data has the changes of '0' and '1' when read in the dynamic aging process by matching with a specific programming code, the read access of the chip can be effectively aged, the aging coverage and effectiveness are increased, and the chip with defects in the read access can be removed in time.
Drawings
FIG. 1 is a layout diagram of a one-time programmable memory chip provided by the present invention;
fig. 2 is a schematic diagram of a typical memory cell structure.
Detailed Description
The method for screening the one-time programmable memory chip according to the present invention is further described in detail with reference to the accompanying drawings and the specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Example one
The invention provides a method for screening a one-time programmable memory chip, wherein the layout of the programmable memory chip is shown in figure 1, the programmable memory chip comprises a memory array, a programming and reading circuit and a word line drive, and the memory array is divided into two parts: a user storage area and a test array; the user storage area is an area used by a user to store information, and the test array is an area used for programming, reading and the like, so as to test the chip.
With continued reference to fig. 1, the user storage area includes word lines (W L), bit lines (B L), memory cells (m × N), and possibly required power and ground lines (not shown), the test array includes redundant rows and redundant columns, the redundant rows include two rows of memory cells and word lines, bit lines, and possibly required power and ground lines within the regions, and the redundant columns include two columns of memory cells and word lines, bit lines, and possibly required power and ground lines within the regions, a typical memory cell structure is shown in fig. 2, and is formed by an antifuse N1, which is in a high-resistance state when unprogrammed and represents stored data "0", and a low-resistance connection when programmed and represents "1", or vice versa (all illustrated in the present invention in terms of stored data "0" when a memory cell is unprogrammed and represents "1"), the programming and reading circuitry, the word line driver, the user storage area, the redundant rows, and the redundant columns are arranged in a layout such a way that the user storage area is located opposite the user storage area and the redundant rows are arranged with respect to the user storage area.
The invention provides a method for screening one-time programmable memory chips, which comprises the following steps:
(1) and programming and verifying the redundant row of the one-time programmable memory chip through a programmer, and eliminating the chips failed in verification.
In the view of the columns of the redundant row, each column in the redundant row has 2 memory cells, at least 1 of the memory cells can be programmed, namely 1 memory cell can be programmed, 2 memory cells can also be programmed, but the memory cells in the redundant row can not be completely programmed in the whole view of the redundant row.
(2) Carrying out empty chip check on the one-time programmable memory chip, and removing chips failed in check;
in a possible failure mode, if a source-drain short-circuit defect exists in a MOS tube N1 in a certain memory cell, after the programming of a redundant row is completed, antifuses in memory cells of m +1 rows or m +2 rows of the column are programmed, and the antifuses are changed from high resistance to low resistance, the column data is read to be '1' in the empty chip inspection, the chip considers that the chip is programmed, and the reason is that when the memory cells in the column are read, the reading current from the B L end flows to the ground through the programmed antifuses in the memory cells of the m +1 rows or the m +2 rows of the column, and the current exceeds the 'threshold value', and the column is read to be '1', so that all errors are caused.
(3) Programming and verifying the redundant column of the one-time programmable memory chip through a programmer, and eliminating the chips failed in verification;
in the view of the rows of the redundant columns, each row in the redundant columns has 2 memory cells, at least 1 of the memory cells can be programmed, namely 1 memory cell can be programmed, 2 memory cells can not be programmed, but the whole redundant columns can not be programmed, taking a typical complementary programming code as an example, the redundant column n +1 column is from top to bottom, 0101 … … and the n +2 column is from top to bottom 5391010 2. after the redundant column programming is completed, reading is carried out to check whether the programming content is correctly and completely coded into the redundant column of the chip, if the reading content is not consistent with the programming content, the chip is rejected, and possible failure modes are that the decoding circuit or the word line driving circuit has defects, the word line W L is open in the middle, the W L and the W L are short-circuited, and the W L and the ground line or the power line are short-circuited, so that the programming can fail.
(4) Carrying out empty chip check on the one-time programmable memory chip again, and removing the chip failed in check;
a possible failure mode is a short between the line B L and the line B L, which may cause data that should be programmed into a redundant column to be programmed into the user storage area.
(5) Dynamically aging the one-time programmable memory chip to induce the chip with potential defects to fail early;
in addition to periodic reading of the user memory area during the dynamic burn-in process, periodic reading of the test array is also performed such that there is a "0 → 1" or "1 → 0" change in the read path, i.e., the burn-in process covers the read path. Possible failure modes: at high temperature, some MOS tubes with potential defects are subjected to dynamic aging and then completely lose efficacy, and a data reading channel loses efficacy.
(6) And carrying out whole-chip reading and checking, and rejecting the chip with the error.
And reading and checking the data of the test array and the data of the user storage area, and if the content is wrong, rejecting the chip.
The method provided by the invention can effectively remove the chips with process defects or unqualified parameters, and has high application value.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (7)
1. A method for screening one-time programmable memory chips is characterized by comprising the following steps:
programming and verifying the redundant row of the one-time programmable memory chip through a programmer, and eliminating the chips failed in verification;
carrying out empty chip check on the one-time programmable memory chip, and removing chips failed in check;
programming and verifying the redundant column of the one-time programmable memory chip through a programmer, and eliminating the chips failed in verification;
carrying out empty chip check on the one-time programmable memory chip again, and removing the chip failed in check;
dynamically aging the one-time programmable memory chip to induce the chip with potential defects to fail early;
and carrying out whole-chip reading and checking, and rejecting the chip with the error.
2. The method of screening one-time programmable memory chips of claim 1, wherein the one-time programmable memory chip comprises:
a user storage area for user storage information; the storage area comprises word lines, bit lines, storage units, power lines and ground lines;
the test array is used for testing through programming and reading operations; the test array comprises redundant rows and redundant columns; the redundancy row comprises two rows of storage units, word lines, bit lines, power lines and ground lines in a redundancy row area; the redundant column comprises two columns of storage units, word lines, bit lines, power lines and ground lines in a redundant column area;
a programming and reading circuit which is opposite to the redundant row with the user memory area therebetween;
and a word line driver which is opposite to the redundant column through the user memory area.
3. The method of screening one time programmable memory chips of claim 2, wherein programming and verifying the redundant rows of the one time programmable memory chip by the programmer comprises:
from the column perspective of the redundant row, each column in the redundant row has 2 memory cells, at least 1 of which is programmed, but from the whole redundant row, the memory cells in the redundant row can not be programmed completely; if the verification fails, the chip is removed.
4. The method of screening one time programmable memory chips of claim 2, wherein programming and verifying the redundant columns of one time programmable memory chips by the programmer comprises:
from the perspective of the row of the redundant column, each row in the redundant column has 2 memory cells, at least 1 of which is programmed, but from the perspective of the redundant column as a whole, all the memory cells in the redundant column cannot be programmed; if the verification fails, the chip is removed.
5. The method of screening one-time programmable memory chips of claim 2, wherein dynamically aging one-time programmable memory chips comprises:
periodically reading the user memory area and periodically reading the test array such that the read path has a "0 → 1" or "1 → 0" variation, i.e., the burn-in process covers the read path.
6. The method of screening one time programmable memory chips of claim 2, wherein performing a full slice read verify comprises:
and reading and checking the data of the test array and the data of the user storage area, and if the content is wrong, rejecting the chip.
7. The method of claim 2, wherein the empty check includes checking whether there is a change in the data in the user storage area, and if so, rejecting the chip.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117809702A (en) * | 2024-02-29 | 2024-04-02 | 西安紫光国芯半导体股份有限公司 | Three-dimensional stacking structure and control method |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1383156A (en) * | 2001-04-25 | 2002-12-04 | 日本电气株式会社 | Single chip processor with dynamic ageing testing function and dynamic ageing testing method |
| US20060158933A1 (en) * | 2005-01-14 | 2006-07-20 | Kyung-Won Ryu | NAND flash memory device having security redundancy block and method for repairing the same |
| CN102308338A (en) * | 2009-02-06 | 2012-01-04 | 赛鼎矽公司 | High reliability OTP memory |
| CN105679367A (en) * | 2016-01-14 | 2016-06-15 | 中国电子科技集团公司第五十八研究所 | Programmer for MTM anti-fuse PROM |
| CN106716540A (en) * | 2014-09-27 | 2017-05-24 | 高通股份有限公司 | Method and apparatus for in-system repair of dram in burst refresh by redundancy allocation via OTP elements |
-
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- 2020-03-19 CN CN202010196359.6A patent/CN111415696B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1383156A (en) * | 2001-04-25 | 2002-12-04 | 日本电气株式会社 | Single chip processor with dynamic ageing testing function and dynamic ageing testing method |
| US20060158933A1 (en) * | 2005-01-14 | 2006-07-20 | Kyung-Won Ryu | NAND flash memory device having security redundancy block and method for repairing the same |
| CN102308338A (en) * | 2009-02-06 | 2012-01-04 | 赛鼎矽公司 | High reliability OTP memory |
| CN106716540A (en) * | 2014-09-27 | 2017-05-24 | 高通股份有限公司 | Method and apparatus for in-system repair of dram in burst refresh by redundancy allocation via OTP elements |
| CN105679367A (en) * | 2016-01-14 | 2016-06-15 | 中国电子科技集团公司第五十八研究所 | Programmer for MTM anti-fuse PROM |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117809702A (en) * | 2024-02-29 | 2024-04-02 | 西安紫光国芯半导体股份有限公司 | Three-dimensional stacking structure and control method |
| CN117809702B (en) * | 2024-02-29 | 2024-05-28 | 西安紫光国芯半导体股份有限公司 | Three-dimensional stacking structure and control method |
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