CN111404375B - Inductive current sampling circuit and implementation method thereof - Google Patents
Inductive current sampling circuit and implementation method thereof Download PDFInfo
- Publication number
- CN111404375B CN111404375B CN202010103425.0A CN202010103425A CN111404375B CN 111404375 B CN111404375 B CN 111404375B CN 202010103425 A CN202010103425 A CN 202010103425A CN 111404375 B CN111404375 B CN 111404375B
- Authority
- CN
- China
- Prior art keywords
- circuit
- sampling
- tube
- current
- comparator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
- H02M3/1584—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load with a plurality of power processing stages connected in parallel
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0048—Circuits or arrangements for reducing losses
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Amplifiers (AREA)
Abstract
The invention discloses an inductive current sampling circuit, which mainly solves the problems of poor sampling precision and high circuit cost of the existing inductive current. This circuit of current sampling includes sampling circuit and down-sampling circuit, the output circuit who all links to each other with sampling circuit and down-sampling circuit, comparator E1 that links to each other with the sampling circuit, comparator E2 that links to each other with the down-sampling circuit, the digital signal who all links to each other with comparator E1 and comparator E2 produces the module, the filter circuit who links to each other with the digital signal production module, the negative feedback loop that links to each other with filter circuit, voltage divider module and the operational amplifier circuit that links to each other with the negative feedback loop, and with the operational amplifier circuit, the sampling circuit, the current mirror image circuit that the down-sampling circuit all links to each other. The invention does not generate extra power loss, and simultaneously the current of the upper tube and the lower tube is detected simultaneously and the introduction of the negative feedback loop also ensures the current sampling precision. Therefore, the method is suitable for popularization and application.
Description
Technical Field
The invention relates to the technical field of power management, in particular to an inductive current sampling circuit.
Background
In applications of DC-DC converters in different fields, it is sometimes necessary to detect output or input current while ensuring output voltage accuracy. Taking a buck DC-DC converter as an example, the inductor current is the output current, and accurate sampling of the inductor current becomes a design challenge.
Fig. 1 and 2 illustrate two common methods applied to sampling the output current of a buck DC-DC converter in the prior art, wherein fig. 1 is a method for sampling the inductor current through the DCR of the inductor, which has the advantages of no additional power loss and poor current sampling precision due to poor DCR precision of the inductor; fig. 2 is a circuit diagram of a current detection circuit implemented by connecting a current sampling resistor in series on an output path, which has the advantage of high current sampling precision, but causes extra power loss on the sampling resistor, and the high power sampling resistor leads to high BOM cost.
Disclosure of Invention
The invention aims to provide an inductive current sampling circuit, which mainly solves the problems of poor inductive current sampling precision and high circuit cost in the prior art.
In order to achieve the purpose, the technical scheme adopted by the invention is as follows:
the utility model provides an inductive current sampling circuit, including upsampling circuit and downsampling circuit, the output circuit who all links to each other with upsampling circuit and downsampling circuit, comparator E1 who links to each other with upsampling circuit, comparator E2 who links to each other with downsampling circuit, the digital signal who all links to each other with comparator E1 and comparator E2 produces the module, the filter circuit who links to each other with the digital signal produces the module, the negative feedback loop who links to each other with filter circuit, voltage divider module and operational amplifier circuit that link to each other with the negative feedback loop, and with operational amplifier circuit, upsampling circuit, the current mirror image circuit that downsampling circuit all links to each other.
Furthermore, the up-sampling circuit comprises a power tube Q1 and a sampling tube Q1_ SNS, wherein the grid electrodes of the power tube Q1 and the sampling tube Q1_ SNS are connected and connected with the input end Vin, the source electrode of the sampling tube Q1_ SNS is connected with the anode of the comparator E1 and the current mirror circuit, and the source electrode of the power tube Q1 is connected with the cathode of the comparator E1 and the output circuit; the down-sampling circuit comprises a power tube Q2 and a sampling tube Q2_ SNS, wherein the grid electrodes of the power tube Q2 and the sampling tube Q2_ SNS are connected and connected to the output circuit and the negative electrode of the comparator E2, the source electrode of the sampling tube Q2_ SNS is connected with the positive electrode of the comparator E2 and the current mirror circuit, and the source electrode of the power tube Q1 is connected with the negative electrode of the comparator E1 and grounded.
Further, the digital signal generating module is an RS flip-flop and comprises two nor gate circuits U1 and U2, an input end a of the nor gate circuit U1 is connected to an output end of the comparator E1, an input end B of the nor gate circuit U1 is connected to an output end Q of the nor gate circuit U2, an input end a of the nor gate circuit U2 is connected to an output end of the comparator E2, and an input end B of the nor gate circuit U2 is connected to an output end Q of the nor gate circuit U1; wherein, the output end Q of the NOR gate circuit U2 is connected with the filter circuit.
Further, the filter circuit comprises a resistor R3 with one end connected with the output end Q of the NOR gate circuit U2, and a capacitor C1 with one end connected with the other end of the resistor R3 and the other end grounded.
Further, the voltage division module comprises a resistor R1 with one end connected to the voltage Vcc and a resistor R2 with one end connected to the resistor R1 and the other end grounded; wherein, the connection end of the resistor R1 and the resistor R2 is connected with a negative feedback loop.
Further, the negative feedback loop comprises an amplifier E3 of which the anode is connected with the connection end of the resistor R3 and the capacitor C1 and the cathode is connected with the connection end of the resistor R1 and the resistor R2, and a capacitor C2 of which one end is connected with the output end of the amplifier E3 and the other end is grounded.
Further, the operational amplifier circuit comprises an amplifier E4 of which the anode is connected with the output end of the amplifier E3, and a resistor Rsns of which one end is connected with the cathode of the amplifier E4 and the other end is grounded; the pole and the output end of the amplifier E4 are both connected with a current mirror circuit.
Further, the current mirror circuit comprises an MOS tube Q3, a MOS tube Q4, a MOS tube Q5 and a MOS tube Q6, wherein the grid electrode of the MOS tube Q3 is connected with the output end of the amplifier E4, the source electrode of the MOS tube Q4 is connected with the negative electrode of the amplifier E4, the grid electrodes of the MOS tubes Q4, Q5 and Q6 are connected with the drain electrode of the MOS tube Q3, and the grid electrodes of the MOS tubes Q7 and Q8 are connected with the source electrode of the MOS tube Q5; the source electrodes of the MOS tubes Q4, Q5 and Q6 are connected and then connected with a voltage Vcc, the drain electrode of the MOS tube Q4 is communicated with the grid electrode of the MOS tube Q4, the source electrodes of the MOS tubes Q7 and Q8 are connected and then grounded, the drain electrode of the MOS tube Q8 is connected with the source electrode of the sampling tube Q1_ SNS, and the drain electrode of the MOS tube Q6 is connected with the source electrode of the sampling tube Q2_ SNS.
Based on the inductive current sampling circuit, the invention also provides an implementation method of the inductive current sampling circuit, which comprises the following specific processes:
(S1) acquiring an upper tube current and a lower tube current using an up-sampling circuit and a down-sampling circuit, respectively;
(S2) adjusting the target current value through a negative feedback loop so that the target current is equal to half the power tube current;
(S3) the current mirror circuit controls two paths of target currents, during the conduction time of a tube-in, one path of target current is compared with the tube-in current through a comparator to generate an output signal, and during the conduction time of a tube-out, the other path of target current is compared with the tube-out current through another comparator to generate another output signal;
(S4) generating digital PWM signals by the two paths of output signals through an RS trigger;
(S5) the digital PWM signal is passed through a filter circuit to obtain an average voltage signal;
(S6) integrating the average voltage signal with the reference voltage through the operational amplifier circuit to obtain a voltage signal of the output current information; the reference voltage is obtained by voltage division and is half of the access voltage.
Compared with the prior art, the invention has the following beneficial effects:
the invention utilizes the median comparison of the current of the upper and lower tubes, converts the PWM signal into an analog level through an RC filter, the reference voltage is Vcc/2, and Vsns is Rsns IL/K through a negative feedback loop formed by an integrator. The target current iset1/iset2 is controlled by a negative feedback loop, and the target current is equal to the middle value of the upper and lower tube currents through current comparison, so that the middle value of the upper and lower tube currents, namely the inductance current value, can be indirectly obtained. The invention does not generate extra power loss, and simultaneously the current of the upper tube and the lower tube is detected simultaneously and the introduction of the negative feedback loop also ensures the current sampling precision.
Drawings
Fig. 1 is a schematic diagram of a current sampling method in the prior art.
Fig. 2 is another current sampling schematic of the prior art.
Fig. 3 is a schematic circuit diagram of the present invention.
Fig. 4 is a waveform diagram of a voltage waveform and an inductor current of a SW node of the DC-DC converter of the present invention.
Wherein, the names corresponding to the reference numbers are:
the circuit comprises a 1-up sampling circuit, a 2-down sampling circuit, a 3-output circuit, a 4-digital signal generating module, a 5-voltage division module, a 6-filter circuit, a 7-negative feedback loop, an 8-operational amplifier circuit and a 9-current mirror circuit.
Detailed Description
The present invention will be further described with reference to the following description and examples, which include but are not limited to the following examples.
Examples
As shown in fig. 3 and 4, the inductor current sampling circuit disclosed by the present invention includes an up-sampling circuit 1 and a down-sampling circuit 2, an output circuit 3 connected to both the up-sampling circuit 1 and the down-sampling circuit 2, a comparator E1 connected to the up-sampling circuit 1, a comparator E2 connected to the down-sampling circuit 2, a digital signal generating module 4 connected to both the comparator E1 and the comparator E2, a filter circuit 6 connected to the digital signal generating module 4, a negative feedback loop 7 connected to the filter circuit 6, a voltage dividing module 5 and an operational amplifier circuit 8 connected to the negative feedback loop 7, and a current mirror circuit 9 connected to the operational amplifier circuit 8, the up-sampling circuit 1, and the down-sampling circuit 2.
Specifically, the up-sampling circuit comprises a power tube Q1 and a sampling tube Q1_ SNS, wherein the grid electrodes of the power tube Q1 and the sampling tube Q1_ SNS are connected and connected to an input end Vin, the source electrode of the sampling tube Q1_ SNS is connected with the positive electrode of a comparator E1 and a current mirror circuit, and the source electrode of the power tube Q1 is connected with the negative electrode of the comparator E1 and an output circuit; the down-sampling circuit comprises a power tube Q2 and a sampling tube Q2_ SNS, wherein the grid electrodes of the power tube Q2 and the sampling tube Q2_ SNS are connected and connected to the output circuit and the negative electrode of the comparator E2, the source electrode of the sampling tube Q2_ SNS is connected with the positive electrode of the comparator E2 and the current mirror circuit, and the source electrode of the power tube Q1 is connected with the negative electrode of the comparator E1 and grounded.
Specifically, the digital signal generation module is an RS flip-flop and comprises two nor gate circuits U1 and U2, wherein an input end a of the nor gate circuit U1 is connected with an output end of a comparator E1, an input end B of the nor gate circuit U1 is connected with an output end Q of a nor gate circuit U2, an input end a of a nor gate circuit U2 is connected with an output end of a comparator E2, and an input end B of the nor gate circuit U2 is connected with an output end Q of a nor gate circuit U1; wherein, the output end Q of the NOR gate circuit U2 is connected with the filter circuit.
In this embodiment, the filter circuit includes a resistor R3 having one end connected to the output terminal Q of the nor gate circuit U2, and a capacitor C1 having one end connected to the other end of the resistor R3 and the other end grounded.
In this embodiment, the voltage dividing module includes a resistor R1 having one end connected to the voltage Vcc, and a resistor R2 having one end connected to the resistor R1 and the other end grounded; wherein, the connection end of the resistor R1 and the resistor R2 is connected with a negative feedback loop.
In this embodiment, the negative feedback loop includes an amplifier E3 having a positive terminal connected to the connection terminal of the resistor R3 and the capacitor C1 and a negative terminal connected to the connection terminal of the resistor R1 and the resistor R2, and a capacitor C2 having one terminal connected to the output terminal of the amplifier E3 and the other terminal connected to ground.
In this embodiment, the operational amplifier circuit includes an amplifier E4 having a positive terminal connected to the output terminal of the amplifier E3, and a resistor Rsns having one terminal connected to the negative terminal of the amplifier E4 and the other terminal connected to the ground; the pole and the output end of the amplifier E4 are both connected with a current mirror circuit.
In this embodiment, the current mirror circuit includes a MOS transistor Q3 having a gate connected to the output terminal of the amplifier E4 and a source connected to the cathode of the amplifier E4, MOS transistors Q4, Q5, and Q6 having gates connected to the drain of the MOS transistor Q3, and MOS transistors Q7 and Q8 having gates connected to the source of the MOS transistor Q5; the source electrodes of the MOS tubes Q4, Q5 and Q6 are connected and then connected with a voltage Vcc, the drain electrode of the MOS tube Q4 is communicated with the grid electrode of the MOS tube Q4, the source electrodes of the MOS tubes Q7 and Q8 are connected and then grounded, the drain electrode of the MOS tube Q8 is connected with the source electrode of the sampling tube Q1_ SNS, and the drain electrode of the MOS tube Q6 is connected with the source electrode of the sampling tube Q2_ SNS.
In this embodiment, the output circuit includes an inductor L1 connected to the source of the power transistor Q1 and the drain of the power transistor Q2, a capacitor Cout having one end connected to the other end of the inductor L1 and the other end digitally grounded, and a connection end of the inductor L1 and the capacitor Cout is used as the output terminal Vout. The output circuit is only one topology circuit in DC-DC.
The sampling circuit of the invention is realized by the following steps:
first, Q1, Q1_ SNS are sampling tubes of an upper power tube and an upper tube, respectively, Q2, Q2_ SNS are sampling tubes of a lower power tube and a lower tube, respectively, target currents iset1 and iset2 are controlled by an operational amplifier E4 and a resistor Rsns and a current mirror circuit Q3, Q4, Q5, Q6, Q7, Q8, the target currents iset2 and iset2 are compared by a comparator E2 during the on time of the upper tube, the result Vt2 and the upper tube current are output, the target currents iset2 and the lower tube current are compared by the comparator E2 during the on time of the lower tube, the result Vt2, Vt2 and Vt2 generate digital PWM signals Vt by RS flip-flops U2 & U2, Vt obtains average voltage signals Vt _ lf after filtering Vt by R2 and C2, the operational amplifier E2 integrates Vt _ pf and reference voltage Vref, and the target current is designed so that the target current value of the vslr 2 is equal to a negative feedback loop, so that the target current is equal to Vcc is formed by an automatic regulation loop, Vcc 3, the Vsns voltage thus obtained is a voltage signal containing information of the output current, and Vsns is Rsns IL/K.
As shown in fig. 4, which is a waveform diagram of a voltage waveform and an inductor current of the SW node of the buck DC-DC converter, during the upper-pipe turn-on time, if the inductor current reaches a target current, the comparator E1 outputs Vt1 to flip, and during the lower-pipe turn-on time, if the inductor current drops to the target current, the comparator E2 outputs Vt2 to flip, the RS flip-flop output signal Vt is a PWM signal having a duty ratio of 50% when the loop is stable, and the RC-filtered signal Vt _ lpf is a voltage having an amplitude of Vcc/2. In the process of closed loop, if the output current becomes large, that is, the inductor current is larger than the target current, the output high time of the comparators E1 and E2 becomes long, so that the duty ratio is larger than 50% when Vt is larger than Vref, and the integrator, that is, the amplifier E3 outputs Vsns to be high, so that the target current follows the inductor current to be increased, and vice versa.
Through the design, the target current iset1/iset2 is controlled by a negative feedback loop, and the target current is equal to half of the current of the upper tube and the lower tube through current comparison, so that the median value of the current of the upper tube and the lower tube, namely the inductance current value, can be indirectly obtained. The invention does not generate extra power loss, and simultaneously the current of the upper tube and the lower tube is detected simultaneously and the introduction of the negative feedback loop also ensures the current sampling precision. Therefore, the method has high practical value and popularization value.
The above-mentioned embodiment is only one of the preferred embodiments of the present invention, and should not be used to limit the scope of the present invention, but all the insubstantial modifications or changes made within the spirit and scope of the main design of the present invention, which still solve the technical problems consistent with the present invention, should be included in the scope of the present invention.
Claims (7)
1. An inductive current sampling circuit is characterized by comprising an up-sampling circuit (1) and a down-sampling circuit (2), an output circuit (3) connected with the up-sampling circuit (1) and the down-sampling circuit (2), a comparator E1 connected with the up-sampling circuit (1), a comparator E2 connected with the down-sampling circuit (2), a digital signal generating module (4) connected with the comparator E1 and the comparator E2, a filter circuit (6) connected with the digital signal generating module (4), a negative feedback loop (7) connected with the filter circuit (6), a voltage dividing module (5) and an operational amplifier circuit (8) connected with the negative feedback loop (7), and a current mirror image circuit (9) connected with the operational amplifier circuit (8), the up-sampling circuit (1) and the down-sampling circuit (2);
the up-sampling circuit comprises a power tube Q1 and a sampling tube Q1_ SNS, wherein the grid electrodes of the power tube Q1 and the sampling tube Q1_ SNS are connected and connected with an input end Vin, the source electrode of the sampling tube Q1_ SNS is connected with the anode of a comparator E1 and a current mirror circuit, and the source electrode of the power tube Q1 is connected with the cathode of the comparator E1 and an output circuit; the down-sampling circuit comprises a power tube Q2 and a sampling tube Q2_ SNS, wherein the grid electrodes of the power tube Q2 and the sampling tube Q2_ SNS are connected and connected to the output circuit and the negative electrode of the comparator E2, the source electrode of the sampling tube Q2_ SNS is connected with the positive electrode of the comparator E2 and the current mirror circuit, and the source electrode of the power tube Q1 is connected with the negative electrode of the comparator E1 and grounded;
the negative feedback loop comprises an amplifier E3 with the anode connected with the filter circuit and the cathode connected with the voltage division module, and a capacitor C2 with one end connected with the output end of the amplifier E3 and the other end grounded.
2. The inductor current sampling circuit according to claim 1, wherein the digital signal generating module is an RS flip-flop, and comprises two nor circuits U1 and U2, an input a of a nor circuit U1 is connected to an output terminal of a comparator E1, an input B of the nor circuit U1 is connected to an output terminal Q of a nor circuit U2, an input a of a nor circuit U2 is connected to an output terminal of a comparator E2, and an input B of the nor circuit U2 is connected to an output terminal Q of a nor circuit U1; wherein, the output end Q of the NOR gate circuit U2 is connected with the filter circuit.
3. The inductor current sampling circuit according to claim 2, wherein the filter circuit comprises a resistor R3 connected to the output Q of the nor gate circuit U2 at one end, and a capacitor C1 connected to the other end of the resistor R3 at the other end and grounded at the other end.
4. The inductor current sampling circuit according to claim 3, wherein the voltage divider module comprises a resistor R1 having one end connected to the voltage Vcc, and a resistor R2 having one end connected to the resistor R1 and the other end connected to ground; wherein, the connection end of the resistor R1 and the resistor R2 is connected with a negative feedback loop.
5. The inductor current sampling circuit according to claim 4, wherein said operational amplifier circuit comprises an amplifier E4 having a positive terminal connected to the output terminal of the amplifier E3, and a resistor Rsns having one terminal connected to the negative terminal of the amplifier E4 and the other terminal connected to ground; the pole and the output end of the amplifier E4 are both connected with a current mirror circuit.
6. The inductor current sampling circuit according to claim 5, wherein the current mirror circuit comprises a MOS transistor Q3 having a gate connected to the output terminal of the amplifier E4 and a source connected to the cathode of the amplifier E4, MOS transistors Q4, Q5 and Q6 having gates connected to the drain of the MOS transistor Q3, MOS transistors Q7 and Q8 having gates connected to the source of the MOS transistor Q5; the source electrodes of the MOS tubes Q4, Q5 and Q6 are connected and then connected with a voltage Vcc, the drain electrode of the MOS tube Q4 is communicated with the grid electrode of the MOS tube Q4, the source electrodes of the MOS tubes Q7 and Q8 are connected and then grounded, the drain electrode of the MOS tube Q8 is connected with the source electrode of the sampling tube Q1_ SNS, and the drain electrode of the MOS tube Q6 is connected with the source electrode of the sampling tube Q2_ SNS.
7. The method for implementing the inductor current sampling circuit according to any one of claims 1 to 6, wherein the specific process is as follows:
(S1) acquiring an upper tube current and a lower tube current using an up-sampling circuit and a down-sampling circuit, respectively;
(S2) adjusting the target current value through a negative feedback loop so that the target current is equal to half the power tube current;
(S3) the current mirror circuit controls two paths of target currents, during the conduction time of a tube-in, one path of target current is compared with the tube-in current through a comparator to generate an output signal, and during the conduction time of a tube-out, the other path of target current is compared with the tube-out current through another comparator to generate another output signal;
(S4) generating digital PWM signals by the two paths of output signals through an RS trigger;
(S5) the digital PWM signal is passed through a filter circuit to obtain an average voltage signal;
(S6) integrating the average voltage signal with the reference voltage through the operational amplifier circuit to obtain a voltage signal of the output current information; the reference voltage is obtained by voltage division and is half of the access voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010103425.0A CN111404375B (en) | 2020-02-20 | 2020-02-20 | Inductive current sampling circuit and implementation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010103425.0A CN111404375B (en) | 2020-02-20 | 2020-02-20 | Inductive current sampling circuit and implementation method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111404375A CN111404375A (en) | 2020-07-10 |
| CN111404375B true CN111404375B (en) | 2021-08-10 |
Family
ID=71413877
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010103425.0A Active CN111404375B (en) | 2020-02-20 | 2020-02-20 | Inductive current sampling circuit and implementation method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111404375B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112671206B (en) * | 2020-12-04 | 2022-09-20 | 杰华特微电子股份有限公司 | Switching power supply and manufacturing method thereof |
| CN113037061B (en) * | 2021-03-10 | 2022-04-15 | 杰华特微电子股份有限公司 | Inductive current detection circuit and switching power supply using same |
| CN116995632B (en) * | 2023-09-28 | 2023-12-08 | 江苏帝奥微电子股份有限公司 | PVT insensitive current limiting protection circuit |
| CN118074487B (en) * | 2024-04-19 | 2024-07-12 | 深圳市思远半导体有限公司 | Inductance current sampling circuit and switching power supply |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3023797A1 (en) * | 2014-11-19 | 2016-05-25 | Dialog Semiconductor (UK) Ltd | Output current monitor circuit for switching regulator |
| CN106992681A (en) * | 2017-03-24 | 2017-07-28 | 无锡硅动力微电子股份有限公司 | Conversion switch with multi-mode current constant control |
| CN107482914A (en) * | 2017-08-29 | 2017-12-15 | 成都芯源***有限公司 | Multiphase switching converter, control circuit and current sharing method thereof |
| CN109921639A (en) * | 2019-03-18 | 2019-06-21 | 电子科技大学 | A kind of Buck converter based on the control of variable turn-on time |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3373432B1 (en) * | 2017-03-10 | 2021-05-12 | Rohm Co., Ltd. | Dc-dc converter |
-
2020
- 2020-02-20 CN CN202010103425.0A patent/CN111404375B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP3023797A1 (en) * | 2014-11-19 | 2016-05-25 | Dialog Semiconductor (UK) Ltd | Output current monitor circuit for switching regulator |
| CN106992681A (en) * | 2017-03-24 | 2017-07-28 | 无锡硅动力微电子股份有限公司 | Conversion switch with multi-mode current constant control |
| CN107482914A (en) * | 2017-08-29 | 2017-12-15 | 成都芯源***有限公司 | Multiphase switching converter, control circuit and current sharing method thereof |
| CN109921639A (en) * | 2019-03-18 | 2019-06-21 | 电子科技大学 | A kind of Buck converter based on the control of variable turn-on time |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111404375A (en) | 2020-07-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN111404375B (en) | Inductive current sampling circuit and implementation method thereof | |
| CN105978337B (en) | A kind of offset voltage based on COT control models eliminates circuit | |
| CN102904435B (en) | Modified compensating circuit and switching power supply applying modified compensating circuit | |
| CN206962700U (en) | Buck converter load current detection circuits without external sampling resistance | |
| CN107290581B (en) | Current detection circuit of switch circuit and switch circuit | |
| WO2020061727A1 (en) | Load current detection method and circuit for inductive switching power converter | |
| CN101951149A (en) | Frequency control circuit suitable for fixed off time control mode boost converter | |
| CN110943612A (en) | Load current detection circuit and method for switching power supply converter | |
| CN110957894A (en) | Load current detection method and circuit of inductive switching power converter | |
| CN103401420A (en) | Adaptive turn-on time generation circuit applied to DC-DC converter | |
| CN107656124A (en) | Boost load current detection circuits and method without external sampling resistance | |
| CN104660028A (en) | Power factor correction circuit | |
| CN114977736A (en) | Current detection circuit and controller for switching conversion circuit | |
| CN106026650B (en) | A kind of offset voltage eliminates circuit | |
| CN108768167B (en) | High-voltage input DC-DC converter and control method thereof | |
| CN110470901B (en) | Average value sampling circuit of inductive current in switching power supply circuit | |
| CN114938129B (en) | Self-adaptive high-linearity ramp compensation circuit | |
| CN208608900U (en) | Electric power converter control circuit | |
| CN113422512B (en) | Four-switch control circuit | |
| CN216672860U (en) | Four-switch control circuit | |
| CN102570975A (en) | Frequency self-adjustment oscillator circuit and frequency self-adjustment method | |
| CN210578255U (en) | Control chip, control circuit and power supply circuit | |
| CN103476180B (en) | Transconductance amplifier and LED constant current drive circuit | |
| CN112688559A (en) | Switching power supply circuit | |
| CN218482779U (en) | Follower circuit, PFC circuit and switching power supply |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder | ||
| CP01 | Change in the name or title of a patent holder |
Address after: Room 214, No.1000 Chenhui Road, China (Shanghai) pilot Free Trade Zone, Pudong New Area, Shanghai, 200120 Patentee after: Shanghai Nanxin Semiconductor Technology Co.,Ltd. Address before: Room 214, No.1000 Chenhui Road, China (Shanghai) pilot Free Trade Zone, Pudong New Area, Shanghai, 200120 Patentee before: SOUTHCHIP SEMICONDUCTOR TECHNOLOGY (SHANGHAI) Co.,Ltd. |