CN111384975B

CN111384975B - Optimization method, device and decoder of multi-system LDPC decoding algorithm

Info

Publication number: CN111384975B
Application number: CN201811645882.1A
Authority: CN
Inventors: 朱永辉; 沈梓荣; 文宇波; 高峰; 许祥滨
Original assignee: Techtotop Microelectronics Co Ltd
Current assignee: Techtotop Microelectronics Co Ltd
Priority date: 2018-12-29
Filing date: 2018-12-29
Publication date: 2023-05-26
Anticipated expiration: 2038-12-29
Also published as: CN111384975A

Abstract

The embodiment of the invention is suitable for the technical field of encoding and decoding, and provides a method, a device and a decoder for optimizing a multi-system LDPC decoding algorithm, wherein the method comprises the following steps: receiving an element operation instruction aiming at a finite field, wherein the operation instruction comprises a multiplication and division operator; converting the multiplication and division operation corresponding to the multiplication and division operator into addition and subtraction operation according to a preset element-power table; calculating an operation result of the addition and subtraction operation; determining a target element corresponding to an operation result by inquiring a preset power-element table, and optimizing the space complexity of the multi-system LDPC decoding algorithm; confidence metrics of each code corresponding to different symbols in the multi-system LDPC decoding algorithm are measured as a finite number of bits. In the embodiment, through the optimization processing of converting the multiplication and division operation in the finite field into the addition and subtraction operation and unevenly quantizing the confidence that each code corresponds to different symbols, the space complexity of a decoding algorithm is reduced, and the decoding efficiency is improved.

Description

Optimization method, device and decoder of multi-system LDPC decoding algorithm

Technical Field

The present invention relates to the field of encoding and decoding technologies, and in particular, to a method for optimizing a multilevel LDPC decoding algorithm, an apparatus for optimizing a multilevel LDPC decoding algorithm, a decoder, and a computer readable storage medium.

Background

Binary Low-Density-Parity-Check (B-LDPC) codes are packet error correction codes with sparse Check matrixes, are applicable to almost all channels, can quickly approach the channel capacity of shannon theory in the form of code length indexes, and are research hot spots in recent years of the coding industry. However, when the code length is relatively short, the performance of the B-LDPC code may be degraded to some extent. Therefore, a learner proposes a multi-system LDPC (Non-Binary Low-Density-Party-Check, abbreviated as NB-LDPC) code on the basis of the B-LDPC code. Compared with B-LDPC codes, in particular when the code length is short, NB-LDPC codes have better performance in theory, and at present, NB-LDPC codes are gradually adopted as coding standards by related industries. For example, beidou satellite navigation system (BDS).

The application of NB-LDPC codes also brings about more complex decoding algorithms. Therefore, in order to reduce the complexity of NB-LDPC decoding algorithms, it is necessary to convert probabilities represented in a confidence manner in the decoding algorithm into logarithmic form, thereby quantizing them to a finite number of bits. However, under the condition of high signal-to-noise ratio, the probability of receiving a code word as a certain symbol is very large, and the probability of receiving other symbols is very small, namely the probability distribution of the symbols is very concentrated; the symbol probability distribution is relatively uniform when the signal-to-noise ratio is low. According to the definition of the confidence, the confidence change range is large at high signal-to-noise ratio, and the confidence change range is smaller at low signal-to-noise ratio. Notably, the larger the confidence value, the more abundant the decoding information it provides. In the prior art, confidence degrees of different values are quantized according to the same standard, so that a part with smaller confidence degrees occupies more bits, and the storage space is increased.

On the other hand, NB-LDPC decoding algorithms also involve multiplication and division operations in the finite field. The multiplication and division operation in the finite field is different from the common arithmetic multiplication and division rule, and the common practice is to store multiplication tables and division tables in the finite field in advance, and then perform fast multiplication and division calculation by a table look-up method. The above method is very simple and very efficient when the order of the finite field is low. However, the above-described finite field multiplication table and division table are proportional to their order squares, i.e., the higher-order finite field multiplication table and division table require a very large memory space. The occupation of the storage space is further increased, and the space complexity of the NB-LDPC decoding algorithm is improved.

Disclosure of Invention

In view of this, the embodiments of the present invention provide a method, an apparatus, and a decoder for optimizing a multi-system LDPC decoding algorithm, so as to solve the problem in the prior art that the NB-LDPC decoding algorithm has higher spatial complexity.

A first aspect of an embodiment of the present invention provides a method for optimizing a multi-system LDPC decoding algorithm, including:

receiving an element operation instruction for a finite field, the operation instruction comprising a multiplication and division operator;

converting the multiplication and division operation corresponding to the multiplication and division operator into addition and subtraction operation according to a preset element-power table;

calculating an operation result of the addition and subtraction operation;

determining a target element corresponding to the operation result by inquiring a preset power-element table, and optimizing the space complexity of the multi-system LDPC decoding algorithm;

the step of optimizing the spatial complexity of the multi-system LDPC decoding algorithm further comprises:

and measuring the confidence of each code corresponding to different symbols in the multi-system LDPC decoding algorithm into a finite bit number.

A second aspect of an embodiment of the present invention provides an optimizing apparatus for a multi-system LDPC decoding algorithm, including:

a receiving module for receiving an element operation instruction for a finite field, the operation instruction comprising a multiplication and division operator;

the conversion module is used for converting the multiplication and division operation corresponding to the multiplication and division operator into addition and subtraction operation according to a preset element-power table;

the calculation module is used for calculating the operation result of the addition and subtraction operation;

the determining module is used for inquiring a preset power-element table and determining a target element corresponding to the operation result;

and the quantization module is used for measuring the confidence of each code corresponding to different symbols in the multi-system LDPC decoding algorithm into a finite bit number.

A third aspect of an embodiment of the present invention provides a terminal device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, the processor implementing the steps of the optimization method of the above-mentioned multi-system LDPC decoding algorithm when executing the computer program.

A fourth aspect of the embodiments of the present invention provides a computer readable storage medium storing a computer program which, when executed by a processor, implements the steps of the above-described method of optimizing a multi-system LDPC decoding algorithm.

Compared with the prior art, the embodiment of the invention has the following advantages:

according to the embodiment of the invention, the simple element-power table and the power-element table are preset, so that the multiplication and division operation in the finite field can be converted into the addition and subtraction operation, and the problem that the preset high-order finite field multiplication table and division table occupy a very large storage space is solved; on this basis, by unevenly quantizing the confidence degrees, each confidence degree can be expressed in the form of a finite number of bits, and the storage space for the confidence degrees can be optimized. Through the optimization processing of the two aspects, the occupation of the NB-LDPC decoding algorithm to the storage space is greatly reduced, the space complexity of the NB-LDPC decoding algorithm is reduced, and the decoding efficiency is improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings that are required to be used in the embodiments or the description of the prior art. It is evident that the figures in the following description are only some embodiments of the invention, from which other figures can be obtained without inventive effort for a person skilled in the art.

FIG. 1 is a flow chart illustrating steps of a method for optimizing a multi-system LDPC decoding algorithm according to an embodiment of the present invention;

FIG. 2 is a schematic circuit diagram of finite field multiplication/division according to one embodiment of the present invention;

FIG. 3 is a schematic diagram of an optimization apparatus of a multi-system LDPC decoding algorithm according to an embodiment of the present invention;

fig. 4 is a schematic diagram of a decoder according to an embodiment of the present invention.

Detailed Description

In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, techniques, etc., in order to provide a thorough understanding of the embodiments of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.

The technical scheme of the invention is described below through specific examples.

Referring to fig. 1, a flowchart illustrating steps of an optimization method of a multi-system LDPC decoding algorithm according to an embodiment of the present invention may specifically include the following steps:

s101, receiving an element operation instruction aiming at a finite field, wherein the operation instruction comprises a multiplication and division operator;

it should be noted that the method can be applied to the decoding process of the multi-system LDPC (NB-LDPC) code.

In abstract algebra, a domain is an algebraic structure that can perform addition, subtraction, multiplication, and division operations. If a field contains only a limited number of elements, it is called a finite field (finite).

In the embodiment of the invention, when the operation instruction for each element in the finite field is received, the element can be subjected to multiplication and division operation according to the multiplication and division operation character contained in the operation instruction.

S102, converting the multiplication and division operation corresponding to the multiplication and division operator into addition and subtraction operation according to a preset element-power table;

in general, any non-0 element may be represented as a power of any non-0 element in the finite field. Assuming Ω is any non-0 element in the finite field GF (q), X and Y are any element in GF (q), and can be expressed as:

then the multiplication-division in GF (q) may be expressed as:

wherein, (J+ -K) _q Representing the addition and subtraction result, the finite field order q is left.

Taking the 64-ary finite field as an example, the 64-ary finite field has a total of 64 elements, which can be expressed as a ₀ ,a ₁ ,…,a ₆₃ (or directly 0,1, … 63), except for element 0 (a) ₀ (0) Other elements may be represented as powers of one of the elements (powers of the finite field). For example, a ₁ Can be expressed as a ₁ To the 1 st power, a ₂ Represented as a ₁ …, a) ₆₃ Represented as a ₁ To the power of 17 of the above elements is merely illustrative and not a true power value. In other words, a ₁ -a ₆₃ Can be expressed as a ₁ To the power of (a) to base a ₁ Change to a ₂ ,a ₃ Other non-0 elements are also true.

Therefore, according to the characteristics of the finite field, a simple element-power table and a power-element table can be stored in advance, and the multiplication and division operation in the finite field is converted into addition and subtraction operation, so that the requirement on storage space when decoding is carried out by adopting a multi-system LDPC decoding iterative algorithm can be greatly reduced.

In the embodiment of the invention, the preset element-power table can be recorded with the power value corresponding to each non-0 element according to the selected substrate. That is, each non-0 element may be represented as a power of the base.

For example, if the substrate is a ₁ Then each non-0 element that can be recorded in the element-power table can be expressed as a ₁ Several powers of (a), as in the previous examples [1,5, … 17 ]]。

Therefore, for the first element and the second element in the operation instruction, the power value of the first element and the power value of the second element can be obtained by querying a preset element-power table, so that the multiplication and division operation on the first element and the second element is converted into addition and subtraction operation.

For example, the first element, the second element, and the multiplication and division operator in the finite field may be denoted as X, Y and OP, respectively, that is, the first element X, the second element Y, and the multiplication and division operator OP, which may be further distinguished as a multiplication operator and a division operator.

S103, calculating an operation result of the addition and subtraction operation;

by querying a preset element-power table, the power J of the first element X and the power K of the second element Y can be determined.

Then, for different operators, corresponding calculations are performed.

For example, for the multiplication operator, the sum (J+K) of the power value J of the first element X and the power value K of the second element Y may be calculated _q The method comprises the steps of carrying out a first treatment on the surface of the For the division operator, the difference (J-K) between the power value J of the first element X and the power value K of the second element Y can be calculated _q 。

S104, determining a target element corresponding to the operation result by inquiring a preset power-element table, and optimizing the space complexity of the multi-system LDPC decoding algorithm;

the sum/difference (J + -K) between J and K is calculated based on the operator OP _q The above (J.+ -. K) can then be obtained by looking up a preset power-element table _q A corresponding target element Z.

In the embodiment of the invention, the elements corresponding to any power value of the selected substrate are recorded in the power-element table.

FIG. 2 is a schematic diagram of a finite field multiply/divide circuit according to an embodiment of the present invention; by presetting the element-power table and the power-element table, after finite field elements and corresponding operators are input, multiplication and division operations in the finite field can be converted into addition and subtraction operations according to the operators, so that corresponding target elements are output.

Since finite field multiplication/division is different from ordinary multiplication/division, if a 64-ary finite field element is represented by 0-63, element 2×3 is not equal to 6 elements. The multiplication or division is relatively complex and typically requires a look-up table to implement. Thus, a 64-ary multiplication needs to be accomplished by querying a 64 x 64 table, as does a division. However, if it is converted into a power representation, the power of the multiplication or division result can be calculated by adopting common addition and subtraction, and then the corresponding element is searched according to the power, namely the final result of the multiplication or division. The power table only needs to record 63 elements (except 0 elements), so that a large amount of storage space can be saved relative to two 64×64 lookup tables, and complexity of a multi-system LDPC code iterative algorithm can be reduced.

S105, measuring confidence of each code corresponding to different symbols in the multi-system LDPC decoding algorithm into a finite bit number.

In general, the confidence LDR (Log-Density-Ratio) may be defined as:

wherein p (c=s _n ) Representing codeword c as symbol s _n Is a probability of (2).

In the embodiment of the invention, in order to reduce the space complexity of multi-system LDPC decoding, LDR (Low Density parity check) can be adopted _n Quantization is performed and represented by a limited number. When the signal-to-noise ratio is high, the probability of receiving the codeword c as a certain symbol is very large, and the probability of receiving the codeword c as other symbols is very small, namely the probability distribution of the symbols is very concentrated; the symbol probability distribution is relatively uniform when the signal-to-noise ratio is low. According to the definition of LDR, the LDR variation range is large at high signal-to-noise ratio, and is smaller at low signal-to-noise ratio. Notably, the larger the LDR value, the more rich the decoding information it provides. In other words, more bits must be used to distinguish between the larger LDR value portions during quantization, and fewer bits must be used to distinguish between the smaller LDR value portions, i.e., the larger LDR value portions occupy more bits, the smaller portions occupy fewer bits, and even no bits in the case of a limited number of quantization bits.

Therefore, according to the above-mentioned LDR value distribution characteristics and their physical meanings, the embodiment may perform non-uniform quantization on the confidence level of each symbol of the multi-system LDPC code based on the LDR of the maximum value, and represent the confidence level of each symbol in the form of a finite number of bits.

In the embodiment of the invention, the confidence coefficient sets of the plurality of symbols can be respectively obtained, wherein the confidence coefficient sets comprise a plurality of confidence coefficients corresponding to the plurality of symbols of the multi-system LDPC code one by one. For example, the confidence of multiple symbols may be obtained and represented as a set of confidence.

Taking 64 LDPC as an example, a total of 64 symbols, which can be expressed as S ₀ -S ₆₃ Assuming that there is a multi-system LDPC code denoted Cn, the decoding process is the process of determining which symbol Cn is, and the confidence set is the confidence level of Cn for different symbols.

In a specific implementation, initial confidence of a plurality of symbols may be first obtained, where the initial confidence is Floating Point (Floating Point) or Integer (inter) initial confidence.

Floating point numbers are digital representations of numbers belonging to a particular subset of rational numbers that can be used in a computer to represent any real number in an approximation.

In the embodiment of the invention, the floating point type initial confidence coefficient can be rounded, and the floating point type confidence coefficient is converted into the confidence coefficient in an integer form, so that a confidence coefficient set of a plurality of elements is generated.

The confidence set of the multiple symbols may be expressed as { LDR _k ,β _k (k=1, 2,..k), where β represents the symbol to which the codeword corresponds, i.e., sn in the confidence definition above.

After obtaining the confidence coefficient set, the numerical values of the confidence coefficients can be compared, and the confidence coefficient maximum { LDR } in the confidence coefficient set is identified _max ,β _kmax }。

In the embodiment of the present invention, the confidence maximum may be first quantized to a signed integer maximum of N bits, where the signed integer maximum may be 2 ^N-1 -1。

Taking n=5 as an example, the unsigned numerical range is 0 to 31, and the signed numerical range is-16 to 15.

Therefore, before this step, the number of bits N of the quantization process needs to be determined first, and the number of bits N of the quantization process needs to be determined according to the decoding performance to be achieved and the requirement of the storage space, and needs to be determined by a compromise between the two factors.

After quantizing the confidence maximum to a signed integer maximum of N bits, the quantized elements may be represented as

Then, by determining the numerical differences between the respective confidence degrees in the confidence degree set and the maximum value of the confidence degrees, respectively, the respective confidence degrees can be quantized into a finite number of bits according to the magnitude relation between the numerical differences and the preset threshold value, which is determined by the preset number of bits of the quantization process.

In a specific implementation, each element { LDR } in the confidence coefficient set can be selected one by one _k ,β _k ' calculate LDR _k And the maximum LDR _max Numerical difference DLDR of (2) _k . And then, quantifying each confidence according to the magnitude relation between the numerical value difference and the preset threshold value.

The above-mentioned preset threshold value can be determined according to bit number N of quantization process, i.e. said preset threshold value can be expressed as 1-2 ^N 。

In the embodiment of the present invention, if the numerical difference is greater than or equal to the preset threshold value 1-2 ^N The confidence can be quantized to the value difference and 2 ^N-1 -sum of 1; if the difference is less than 1-2 ^N The confidence can be directly quantized to-2 ^N-1 。

That is, if the difference is greater than or equal to the preset threshold value 1-2 ^N Then LDR can be used _k Quantitated to 2 ^N-1 -1+DLDR _k The quantized element may be represented as {2 } ^N-1 -1+DLDR _k ,β _k -a }; if the difference is less than 1-2 ^N Then LDR can be used _k Direct quantization to-2 ^N-1 The quantized element may be represented as { -2 ^N-1 ,β _k }。

Also taking n=5 as an example, if the confidence value before quantization is [31,28, -4], the confidence maximum 31 may be quantized to 15 first according to the foregoing description; since 28-31= -3, -3 is larger than-31, 28 can be quantized to 12 (15-3); since-4-31= -35, -35 is smaller than-31, -4 can be quantized to-16. The quantized values were obtained as [15,12, -16].

According to the distribution characteristics of the confidence coefficient of the multi-system LDPC code and the physical meaning of the confidence coefficient, each confidence coefficient can be represented in a limited bit form by non-uniformly quantizing each confidence coefficient, more bits are used for distinguishing the part with larger confidence coefficient, fewer bits are used for distinguishing the part with smaller confidence coefficient, namely the part with larger confidence coefficient occupies more bit numbers, the smaller part occupies fewer bit numbers, and even under the condition that the quantized bit number is limited, the bit number is not occupied, so that the memory space of the opposite confidence coefficient can be optimized, and the complexity of an NB-LDPC decoding algorithm is reduced.

In the embodiment of the invention, the multiplication and division operation in the finite field can be converted into addition and subtraction operation by presetting simple element-power table and power-element table, so that the problem that the preset high-order finite field multiplication and division table needs to occupy a very large storage space is solved; on this basis, by unevenly quantizing the confidence degrees, each confidence degree can be expressed in the form of a finite number of bits, and the storage space for the confidence degrees can be optimized. Through the optimization processing of the two aspects, the occupation of the NB-LDPC decoding algorithm to the storage space is greatly reduced, the space complexity of the NB-LDPC decoding algorithm is reduced, and the decoding efficiency is improved.

It should be noted that, the sequence number of each step in the above embodiment does not mean the sequence of execution sequence, and the execution sequence of each process should be determined by its function and internal logic, and should not limit the implementation process of the embodiment of the present invention in any way.

Referring to fig. 3, a schematic diagram of an optimizing apparatus of a multi-system LDPC decoding algorithm according to an embodiment of the present invention may specifically include the following modules:

a receiving module 301, configured to receive an operation instruction for an element in a finite field, where the operation instruction includes a multiplication and division operator;

the conversion module 302 is configured to convert the multiplication and division operation corresponding to the multiplication and division operator into addition and subtraction operation according to a preset element-power table;

a calculating module 303, configured to calculate an operation result of the addition and subtraction operation;

a determining module 304, configured to query a preset power-element table, and determine a target element corresponding to the operation result;

and the quantization module 305 is configured to quantize the confidence of each code corresponding to different symbols in the multi-system LDPC decoding algorithm into a finite number of bits.

In the embodiment of the present invention, the operation instruction further includes a first element and a second element, and the conversion module 302 may specifically include the following sub-modules:

and the conversion sub-module is used for inquiring a preset element-power table to respectively obtain the power value of the first element and the power value of the second element and converting the multiplication and division operation into addition and subtraction operation.

In the embodiment of the present invention, the multiplication and division operator includes a multiplication operator or a division operator, and the calculation module 303 may specifically include the following sub-modules:

a first calculation sub-module for calculating, for the multiplication operator, a sum of the power value of the first element and the power value of the second element;

a second calculation sub-module for calculating, for the division operator, a difference between the power value of the first element and the power value of the second element.

In the embodiment of the present invention, the quantization module 305 may specifically include the following sub-modules:

the acquisition sub-module is used for respectively acquiring confidence coefficient sets of a plurality of symbols, wherein the confidence coefficient sets comprise a plurality of confidence coefficients corresponding to the plurality of symbols of the multi-system LDPC code one by one;

the identification sub-module is used for identifying the maximum value of the confidence coefficient in the confidence coefficient set;

a determining submodule, configured to determine numerical differences between each confidence level in the confidence level set and the maximum value of the confidence level set;

and the quantization sub-module is used for quantizing each confidence into a limited number according to the magnitude relation between the numerical value difference and a preset threshold value, and the preset threshold value is determined by the preset bit number of quantization processing.

In the embodiment of the present invention, the acquiring submodule may specifically include the following units:

the initial confidence coefficient acquisition unit is used for acquiring initial confidence coefficients of a plurality of symbols, wherein the initial confidence coefficients are floating point initial confidence coefficients or integer initial confidence coefficients;

and the confidence coefficient set generating unit is used for rounding the floating point type initial confidence coefficient to generate a confidence coefficient set of a plurality of elements.

In an embodiment of the present invention, the quantization module 305 may further include the following sub-modules:

a bit number determining submodule for determining the bit number N of the quantization processing;

a maximum quantization sub-module for quantizing the confidence maximum to a signed integer maximum 2 corresponding to the number of bits ^N-1 -1。

In the embodiment of the present invention, the quantization submodule may specifically include the following units:

a first quantization unit for, if the numerical value difference is 1-2 or more ^N The confidence is quantized to the numerical difference and 2 ^N-1 -sum of 1;

a second quantization unit for, if the value difference is less than 1-2 ^N The confidence is quantized to-2 ^N-1 。

For the device embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and reference should be made to the description of the method embodiments.

Referring to fig. 4, a schematic diagram of a decoder of one embodiment of the present invention is shown. As shown in fig. 4, the decoder 400 of the present embodiment includes: a processor 410, a memory 420, and a computer program 421 stored in the memory 420 and executable on the processor 410. The processor 410, when executing the computer program 421, implements the steps of the embodiments of the optimization method of the above-described multi-system LDPC decoding algorithm, such as steps S101 to S105 shown in fig. 1. Alternatively, the processor 410 may perform the functions of the modules/units of the apparatus embodiments described above, such as the functions of the modules 301 to 305 shown in fig. 3, when executing the computer program 421.

Illustratively, the computer program 421 may be partitioned into one or more modules/units that are stored in the memory 420 and executed by the processor 410 to accomplish the present invention. The one or more modules/units may be a series of computer program instruction segments capable of performing particular functions, which may be used to describe the execution of the computer program 421 in the decoder 400. For example, the computer program 421 may be divided into a receiving module, a converting module, a calculating module, a determining module, and a quantizing module, where each module specifically functions as follows:

The decoder 400 may be a computing device such as a desktop computer, a notebook computer, a palm computer, a cloud server, a navigation module, a time service module, etc. The decoder 400 may include, but is not limited to, a processor 410, a memory 420. It will be appreciated by those skilled in the art that fig. 4 is merely an example of a decoder 400 and is not intended to limit the decoder 400, and may include more or fewer components than shown, or may combine certain components, or different components, e.g., the decoder 400 may further include input and output devices, network access devices, buses, etc.

The processor 410 may be a central processing unit (Central Processing Unit, CPU), but may also be other general purpose processors, digital signal processors (Digital Signal Processor, DSPs), application specific integrated circuits (Application Specific Integrated Circuit, ASICs), off-the-shelf programmable gate arrays (Field-Programmable Gate Array, FPGAs) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.

The memory 420 may be an internal storage unit of the decoder 400, such as a hard disk or a memory of the decoder 400. The memory 420 may also be an external storage device of the decoder 400, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card) or the like, which are provided on the decoder 400. Further, the memory 420 may also include both internal storage units and external storage devices of the decoder 400. The memory 420 is used to store the computer program 421 as well as other programs and data required by the decoder 400. The memory 420 may also be used to temporarily store data that has been output or is to be output.

It will be apparent to those skilled in the art that the foregoing functional unit and module divisions are merely illustrative for convenience and brevity of description. In practical applications, the above-mentioned functions may be distributed by different functional units and modules according to the needs, that is, the internal structure of the apparatus/terminal device is divided into different functional units or modules, so as to complete all or part of the functions described above. The functional units and modules in the embodiment may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit, where the integrated units may be implemented in a form of hardware or a form of a software functional unit. In addition, the specific names of the functional units and modules are only for distinguishing from each other, and are not used for limiting the protection scope of the present invention. The specific working process of the units and modules in the above system may refer to the corresponding process in the foregoing method embodiment, which is not described herein again.

In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference may be made to related descriptions of other embodiments.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.

In the embodiments provided in the present invention, it should be understood that the disclosed apparatus/terminal device and method may be implemented in other manners. For example, the apparatus/terminal device embodiments described above are merely illustrative, e.g., the division of the modules or units is merely a logical function division, and there may be additional divisions in actual implementation, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. On the other hand, the coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection via interfaces, devices or units, which may be in electrical, mechanical or other forms.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The integrated modules/units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the present invention may implement all or part of the flow of the method of the above embodiment, or may be implemented by instructing the relevant hardware by a computer program, where the computer program may be stored in a computer readable storage medium, and the computer program may implement the steps of each of the method embodiments described above when executed by a processor. Wherein the computer program comprises computer program code which may be in source code form, object code form, executable file or some intermediate form etc. The computer readable storage medium may include: any entity or device capable of carrying the computer program code, a recording medium, a U disk, a removable hard disk, a magnetic disk, an optical disk, a computer Memory, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), an electrical carrier signal, a telecommunications signal, a software distribution medium, and so forth. It should be noted that the computer readable storage medium may include content that is subject to appropriate increases and decreases as required by jurisdictions and by jurisdictions in which such computer readable storage medium does not include electrical carrier signals and telecommunications signals.

The above embodiments are only for illustrating the technical solution of the present invention, and are not limited thereto. Although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention, and are intended to be included in the scope of the present invention.

Claims

1. A method for optimizing a multi-system LDPC decoding algorithm, comprising:

calculating an operation result of the addition and subtraction operation;

measuring confidence of each code corresponding to different symbols in the multi-system LDPC decoding algorithm into a finite number of bits;

the step of measuring the confidence of each code corresponding to different symbols in the multi-system LDPC decoding algorithm into a finite number of bits comprises the following steps:

respectively acquiring confidence coefficient sets of a plurality of symbols, wherein the confidence coefficient sets comprise a plurality of confidence coefficients corresponding to the plurality of symbols of the multi-system LDPC code one by one;

identifying a confidence maximum in the confidence set;

respectively determining numerical differences between each confidence degree in the confidence degree set and the maximum value of the confidence degrees;

and according to the magnitude relation between the numerical value difference and a preset threshold value, each confidence is quantized into a limited number, and the preset threshold value is determined by the preset bit number of quantization processing.

2. The method of claim 1, wherein the operation instruction further includes a first element and a second element, and the step of converting the multiplication and division operation corresponding to the multiplication and division operator into the addition and subtraction operation according to a preset element-power table includes:

and inquiring a preset element-power table to respectively obtain the power value of the first element and the power value of the second element, and converting the multiplication and division operation into addition and subtraction operation.

3. The method of claim 2, wherein the multiplication and division operator comprises a multiplication operator or a division operator, and wherein the step of calculating the operation result of the addition and subtraction operation comprises:

calculating, for the multiplication operator, a sum of the power value of the first element and the power value of the second element;

for the division operator, a difference between a power value of the first element and a power value of the second element is calculated.

4. The method of claim 1, wherein the step of separately obtaining confidence sets for a plurality of symbols comprises:

acquiring initial confidence degrees of a plurality of symbols, wherein the initial confidence degrees are floating point type initial confidence degrees or integer type initial confidence degrees;

and rounding the floating point type initial confidence coefficient to generate a confidence coefficient set of a plurality of symbols.

5. The method as recited in claim 4, further comprising:

determining the bit number N of quantization processing;

quantizing the confidence maximum to a signed integer maximum of 2 corresponding to the number of bits ^N-1 -1。

6. The method of claim 5, wherein said step of measuring said respective confidence as a finite number of bits based on a magnitude relationship between said numerical difference and a preset threshold comprises:

if the numerical value difference is more than or equal to 1-2 ^N The confidence is quantized to the numerical difference and 2 ^N-1 -sum of 1;

if the numerical difference is less than 1-2 ^N The confidence is quantized to-2 ^N-1 。

7. An optimizing apparatus for a multi-system LDPC decoding algorithm, comprising:

the quantization module is used for measuring the confidence of each code corresponding to different symbols in the multi-system LDPC decoding algorithm into a finite bit number;

the quantization module specifically comprises the following sub-modules:

8. Terminal device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that the processor implements the steps of the optimization method of the multi-system LDPC decoding algorithm according to any of claims 1 to 6 when the computer program is executed by the processor.

9. A computer readable storage medium storing a computer program, characterized in that the computer program when executed by a processor implements the steps of the optimization method of the multi-system LDPC decoding algorithm according to any one of claims 1 to 6.