CN111371455B - System for dynamic switching of PLL output frequency - Google Patents
System for dynamic switching of PLL output frequency Download PDFInfo
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- CN111371455B CN111371455B CN201911415101.4A CN201911415101A CN111371455B CN 111371455 B CN111371455 B CN 111371455B CN 201911415101 A CN201911415101 A CN 201911415101A CN 111371455 B CN111371455 B CN 111371455B
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- H—ELECTRICITY
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- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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Abstract
The invention discloses a system for dynamically switching the output frequency of a PLL, which comprises an editable PLL and a dynamic switching circuit. The PLL outputs an oscillation clock signal after locking an input clock signal input from the outside; the oscillating clock signal is divided by an output frequency divider to output a first clock signal. The dynamic switching circuit comprises a judging sub-circuit and a switching sub-circuit; the judging sub-circuit judges the validity of a first switching signal input from the outside according to the first clock signal; when the first switching signal is invalid, the switching sub-circuit outputs a preset configuration frequency division control signal; otherwise, the switching sub-circuit outputs a memory frequency division control signal generated by an externally input dynamic frequency division control signal. The output frequency divider outputs a first clock signal according to the configuration frequency division control signal or the memory frequency division control signal. When the user changes the output clock of the editable PLL, the user can adjust the output clock without resetting and relocking the editable PLL; and burrs generated in the process are effectively avoided.
Description
Technical Field
The invention relates to the field of signal delay, in particular to a system for dynamically switching the output frequency of a PLL.
Background
Fig. 1 is a block diagram of a prior art PLL. As shown in fig. 1, in the prior art, the phase-locked loop PLL is composed of a phase frequency detector PFD, a charge pump CP, a loop filter LF, a voltage controlled oscillator VCO, and a loop feedback divider fb_div.
The phase frequency detector compares the frequency and phase of the reference signal CLKref with the frequency and phase of the oscillating clock signal CLKvco processed by the loop feedback divider. When the comparison is stable, the PLL completes locking, and the relationship exists as follows:
Fvco＝Fref×Ndiv_fb (1)
where Fvco is the frequency of the oscillating clock signal CLKvco, fref is the frequency of the reference signal CLKref, and ndiv_fb is the division ratio coefficient of the loop feedback divider.
On the basis of the PLL described above, an output frequency divider out_div is added to obtain a phase-locked loop PLL (hereinafter, simply referred to as an editable PLL) with an editable frequency divider, as shown in fig. 2, for dividing the oscillating clock signal, where there is a relationship as follows:
where ndiv_out is the division ratio coefficient of the output frequency divider, and Fout is the frequency of the first clock signal CLKout.
As can be seen from equation (2), by setting the appropriate values of Fref, ndiv_fb and ndiv_out, the PLL can be locked to obtain the desired frequency of the first clock signal, i.e., the output clock frequency Fout.
When at least one of the values Fref, ndiv_fb and ndiv_out is changed, fout is changed. In general other applications, the editable PLL in this process needs to be reset and re-locked.
The PLL circuit includes a lock_detect module, as shown in fig. 3. The lock detection module receives the reference signal and the oscillation clock signal processed by the loop feedback frequency divider to judge. When the output signal PLL_LOCK signal of the LOCK detection module is switched to a high level, the PLL circuit is judged to be locked.
In some circuits employing the editable PLL shown in fig. 2, if it is desired to change only the frequency of the first clock signal output by the editable PLL, it is not desired to change the frequency of the oscillation clock signal output by the voltage controlled oscillator VCO. It is conventional practice to reset the editable PLL and to re-lock the first clock signal after reconfiguring the value of ndiv_out of the editable PLL. Since the PLL locking process typically requires tens or hundreds of microseconds (depending on the output clock frequency and locking accuracy requirements), this process is very time consuming.
Disclosure of Invention
The invention aims to solve the defects existing in the prior art.
To achieve the above objective, an embodiment of the present invention discloses a system for dynamically switching the output frequency of a PLL, which includes an editable PLL and a dynamic switching circuit. Wherein the editable PLL is composed of a phase-locked loop PLL and an output divider. Locking an externally input clock signal through a phase-locked loop (PLL), and outputting an oscillation clock signal after locking; the oscillating clock signal is divided by an output frequency divider to output a first clock signal. The dynamic switching circuit comprises a judging sub-circuit and a switching sub-circuit; the judging sub-circuit judges the validity of a first switching signal input from the outside according to the first clock signal; when the first switching signal is invalid, the switching sub-circuit outputs a preset configuration frequency division control signal; otherwise, the switching sub-circuit outputs a memory frequency division control signal generated by an externally input dynamic frequency division control signal. The output frequency divider outputs a first clock signal according to the configuration frequency division control signal or the memory frequency division control signal.
In one example, the first switching signal is determined to be valid when the pulse width of the first switching signal is greater than one clock cycle of the first clock signal; otherwise the first switching signal is inactive.
In one example, the validity of the first switching signal is inactive, active, or once active; after the first switching signal is judged to be valid for the first time, the validity is once valid; when the first switching signal is determined to be valid, the validity is valid and not once valid.
In a further example, when the first switching signal is valid, the memory frequency division control signal provided by the dynamic switching circuit is a dynamic frequency division control signal; when the first switching signal is effective, the memory frequency division control signal provided by the dynamic switching circuit is the dynamic frequency division control signal when the first switching signal is effective last time.
In one example, the judgment sub-circuit includes a first D flip-flop, a second D flip-flop, and an AND gate; the first D trigger outputs a first switching signal input from the outside from a Q end of the first D trigger according to a first clock signal and sends the first switching signal to the second D trigger; the second D trigger outputs a Q end output signal of the first D trigger from a Q end thereof according to the first clock signal; the AND gate receives output signals of the first D trigger and the second D trigger, generates a second switching signal, and the second switching signal is used for representing the validity of the first switching signal;
in one example, the switching sub-circuit includes a third D flip-flop, a fourth D flip-flop, and a selector; the third D trigger outputs the working voltage from the Q end of the third D trigger according to the second switching signal; the fourth D trigger outputs an externally input dynamic frequency division control signal from the Q end of the fourth D trigger according to the second switching signal to be used as a memory frequency division control signal; the selector receives the output signal of the third D trigger as a selection control signal, and selects a preset configuration frequency division control signal or a memory frequency division control signal output by the fourth D trigger as an output signal.
The embodiment of the invention has the advantages that: by setting a dynamic switching circuit for the output frequency divider of the editable PLL, dynamic switching of the frequency division signal of the output frequency divider is realized, so that a user does not need to reset and relock the editable PLL when changing the output clock of the editable PLL; and effectively avoids glitches generated during the output clock switching of the editable PLL.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a basic block diagram of a phase-locked loop PLL in the prior art;
FIG. 2 is a block diagram of the basic structure of an editable PLL in the prior art;
FIG. 3 is a block diagram of the basic structure of an editable PLL with lock detection module in the prior art;
FIG. 4 is a block diagram of a system for dynamic switching of PLL output frequency in accordance with an embodiment of the present invention;
FIG. 5 is a timing diagram of a system operating waveform according to an embodiment of the present invention;
fig. 6 is a schematic diagram of the basic structure of a FIFO according to the prior art.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The system for dynamically switching the output frequency comprises a frequency divider and a dynamic switching circuit.
Wherein,
the frequency divider receives an external clock signal and outputs a first clock signal according to the frequency division signal provided by the dynamic switching circuit. The user can adjust the output signal of the dynamic switching circuit according to the self requirement, and then the frequency divider is controlled to divide the frequency of the external clock signal to meet the requirement.
And the dynamic switching circuit judges the validity of the received first switching signal according to the received first clock signal. In one example, the validity of the first switching signal is determined by its pulse width, and when the pulse width of the first switching signal is greater than one clock cycle of the first clock signal, the first switching signal is determined to be valid; otherwise the first switching signal is inactive.
The dynamic switching circuit provides a divided signal to the frequency divider according to the validity of the first switching signal. Wherein the divided signal comprises: configuring a frequency division control signal and a memory frequency division control signal; specifically, the frequency division control signal is configured as a preset frequency division signal, and the memory frequency division control signal is a dynamic frequency division control signal customized according to the user requirement.
In one example, the validity of the first switching signal can be divided into: ineffective, effective and once effective. The validity of the first switching signal is invalid until the first switching signal is determined to be valid for the first time; after it is determined to be valid for the first time, its validity becomes once valid; the validity is valid for the time when it is determined to be valid, and is not once valid.
It is to be understood that the inactive, active and once active state of the first switching signal is embodied in the form of a certain period of time in the time sequence corresponding to a certain activity during operation of the system. I.e. the first switching signal is one of inactive, active and once active for a certain period of time.
For example, when the nth determination is made that the first switching signal is valid, the validity of the first switching signal is changed to be valid, and the first switching signal is not considered to be valid for a period of time in which the first switching signal is determined to be valid for the nth time; when the time for determining that the first switching signal is valid is ended, the validity of the first switching signal is changed to be once valid. N is a positive integer.
In a further example, the dynamic switching circuit provides the divided signal to the divider based on the validity of the first switching signal. When the first switching signal is invalid, the dynamic switching circuit provides a frequency division control signal as a frequency division signal of the frequency divider; when the first switching signal is valid or is once valid, the dynamic switching circuit provides a memory frequency division control signal as a frequency division signal of the frequency divider.
In yet a further example, the dynamic switching circuit provides the divided signal to the divider based on the validity of the first switching signal. When the first switching signal is effective, the memory frequency division control signal provided by the dynamic switching circuit is a dynamic frequency division control signal; when the first switching signal is effective, the memory frequency division control signal provided by the dynamic switching circuit is the dynamic frequency division control signal when the first switching signal is effective last time.
In one embodiment, a system for dynamically switching output frequencies is applied to an editable PLL circuit and performs signal interaction with an output frequency divider in the editable PLL circuit, as shown in fig. 4, and the system includes: a dynamic switching circuit, and an output divider VCO of the editable PLL circuit (other structures of the editable PLL circuit are not shown).
The dynamic switching circuit includes: a plurality of D flip-flops, and gates and a selector mux. Wherein,
the D flip-flop DFF1 generates an and gate first input signal q0 according to the first clock signal CLKout input at the CP terminal and the first switching signal Switch input at the D terminal.
The D flip-flop DFF2 generates an and gate second input signal q1 based on the first clock signal CLKout input from the CP terminal and the and gate first input signal q0 input from the D terminal.
The AND gate and receives the AND gate first input signal q0 and the AND gate second input signal q1, and generates a second switching signal update.
The D flip-flop DFF3 generates a selection signal mux_sel according to the second switching signal update input from the CP terminal and the operating voltage VDD input from the D terminal.
The D trigger DFF4 generates a memory frequency division control signal DIV_store according to the second switching signal update input by the CP end and the dynamic frequency division control signal DIV_dynamic input by the D end.
The selector mux selects the configuration frequency division control signal div_cfg or the memory frequency division control signal div_store as the first output signal D according to the selection signal mux_sel, and the first output signal D is used as the frequency division signal of the output frequency divider. The frequency division control signal DIV_cfg is configured as a preset frequency division signal.
The D flip-flop DFF1, the D flip-flop DFF2, and the and gate and are used for determining whether the first switching signal Switch is valid according to the first clock signal CLKout. When the AND gate first input signal q0 and the AND gate second input signal q1 are at a high level, namely the second switching signal update is at a high level, the first switching signal Switch is effective; when the AND gate first input signal q0 and/or the AND gate second input signal q1 are low level, i.e. the second switching signal update is low level, the first switching signal Switch is not valid.
The D-flip-flop DFF3 is configured to record validity of the first switching signal Switch by the second switching signal update, and when the first switching signal Switch is valid for the first time, the D-flip-flop DFF3 outputs the operating voltage VDD of the D-terminal as the Q-terminal according to the second switching signal update. After the first switching signal Switch is asserted for the first time, the Q terminal of the D flip-flop DFF3 always outputs the operating voltage VDD without resetting the D flip-flop DFF 3.
The D trigger DFF4 is used for outputting a memory frequency division control signal DIV_store according to the second switching signal update; when the first switching signal Switch is valid, the memory frequency division control signal DIV_stored provided by the dynamic switching circuit is a dynamic frequency division control signal DIV_dynamic; when the first switching signal Switch is effective, the memory frequency division control signal div_stored provided by the dynamic switching circuit is the dynamic frequency division control signal div_dynamic when the first switching signal Switch is effective last time.
The output divider VCO receives the oscillation clock signal CLKvco transmitted by the voltage-controlled oscillator in the editable PLL and outputs the first clock signal CLKout in accordance with the divided signal supplied from the dynamic switching circuit.
After the first clock signal CLKout is locked,
if the first switching signal Switch is low, the branch signals in the dynamic switching circuit are low, and the selector mux selects the configuration frequency division control signal div_cfg as the first output signal D to be supplied to the output frequency divider VCO.
If the first switching signal Switch is high level and lasts for two clock periods of the first clock signal CLKout. The first input signal q0 output by the D flip-flop DFF1 and the second input signal q1 output by the D flip-flop DFF2 will both be at high level, and the second switching signal update output by the and gate and is at high level. The D flip-flop DFF3 outputs the operating voltage VDD from the Q terminal, i.e., the selection signal mux_sel is the operating voltage VDD, i.e., the high level. The D flip-flop DFF4 outputs the dynamic frequency division control signal div_dynamic from the Q terminal, i.e., the memory frequency division control signal div_stored is the dynamic frequency division control signal div_dynamic. The selector mux selects the memory frequency division control signal div_stored to be supplied as the first output signal D to the output frequency divider VCO. When the configuration of the editable PLL comprising the system is finished and starts to work, each D trigger in the dynamic switching circuit is reset, and the Q end of each D trigger outputs a low level. The frequency division ratios of all the divided signals are set to 8 bits, including DIV_cfg [7:0], DIV_dynamic [7:0], DIV_store [7:0], D [7:0], and the waveforms of the nodes in the system are shown in FIG. 5.
At time T1, the first switching signal Switch is switched from low level to high level, but at this time, the and gate second input signal q1 is low level, and the second switching signal update is low level. Regardless of the waveform of the first clock signal CLKout, the selector mux selectively configures the frequency division control signal div_cfg as the first output signal D according to the low level select signal mux_sel, i.e., D [7:0] is div_cfg [7:0].
Further, in a period from the low level to the high level of the first switching signal Switch to the end of the time T1, when the first clock signal CLKout experiences a rising edge, the D flip-flop DFF1 outputs the first switching signal Switch input from the D terminal as the Q terminal, that is, the and gate first input signal Q0 is switched to the high level; when the first clock signal CLKout again experiences a rising edge, the D flip-flop DFF2 outputs the and gate first input signal Q0 input at the D terminal as the Q terminal, i.e., the and gate second input signal Q1 switches to a high level.
At the end of time T1, when the first input signal q0 and the second input signal q1 are at high level, the second switching signal update outputted from the and gate and switches to high level.
In the time T2, the D flip-flop DFF3 outputs the operating voltage VDD input at the D terminal as the Q terminal, i.e., the selection signal mux_sel is switched to the high level; when the second switching signal update is switched from low level to high level after entering the time T2, the D flip-flop DFF4 outputs the dynamic frequency division control signal div_dynamic input from the D terminal as the Q terminal, i.e. the memory frequency division control signal div_stored is switched to the dynamic frequency division control signal div_dynamic. When mux_sel is high, the selector mux selects the memory frequency division control signal DIV_store as the first output signal D, i.e., D [7:0] is DIV_store [7:0], i.e., DIV_dynamic [7:0].
The first clock signal CLKout is switched to a new frequency and remains according to the first output signal D until it is again subjected to the second switching signal update from low to high.
And in the time T2, the dynamic frequency division control signal DIV_dynamic is switched from the pattern to the pattern+1, and the time period is up to the end of the time T2. Due to the sampling signal of the first switching signal Switch, i.e. the influence of the first clock signal CLKout, the and gate first input signal q0 and/or the and gate second input signal q1 are at a low level, so that the second switching signal update is at a low level. The selector mux selects the memory frequency division control signal div_store as the first output signal D according to the high-level selection signal mux_sel. However, it should be noted that the dynamic frequency division control signal div_dynamic at this time cannot be outputted from the Q terminal by the D flip-flop DFF4, and the memory frequency division control signal div_store is the dynamic frequency division control signal div_dynamic when the first Switch signal Switch was active last time, that is, the dynamic frequency division control signal div_dynamic at the time T2 is always pattern.
At the end of time T2, when the first input signal q0 and the second input signal q1 are at high level, the second switching signal update outputted from the and gate and switches to high level.
When the second switching signal update is switched to a high level, namely at a time T3, the D trigger DFF3 outputs the working voltage VDD input by the D end as a Q end, namely the selection signal mux_sel is switched to the high level; when the second switching signal update switches to a high level, the D flip-flop DFF4 outputs the new dynamic frequency division control signal div_dynamic input at the D terminal as the Q terminal, i.e., the memory frequency division control signal div_stored switches to the new dynamic frequency division control signal div_dynamic. When mux_sel is high, the selector mux selects the new memory frequency division control signal div_store as the first output signal D.
Based on the characteristics of the D flip-flop, the D flip-flop DFF4 outputs the dynamic frequency division control signal div_dynamic input from the D terminal as the Q terminal only when the second switching signal update is switched from the low level to the high level, i.e., the memory frequency division control signal div_stored is switched to the new dynamic frequency division control signal div_dynamic.
Based on the characteristics of the D flip-flop, the D flip-flop DFF3 outputs the operating voltage VDD input at the D terminal as the Q terminal, i.e., after the selection signal mux_sel is switched to the high level, if the D flip-flop DFF3 is not reset, the Q terminal of the D flip-flop DFF3 will continuously output the high level.
To ensure that both the D flip-flop DFF1 and the D flip-flop DFF2 can sample to a high level, i.e., the Q terminals of both D flip-flops output a high level, the first switching signal Switch must be maintained for at least one clock cycle of the first clock signal CLKout.
To ensure that each new dynamic frequency division control signal div_dynamic can be sent as the first output signal D to the output frequency divider, the value of each bit of the dynamic frequency division control signal div_dynamic needs to be updated before the rising edge of the first switching signal switch arrives. The memory frequency division control signal uses the first clock signal CLKout as a sampling signal of the first switching signal Switch, and if the delays of the D flip-flop DFF2, the D flip-flop DFF4 and the selector mux are relatively low, the delays of the three together do not exceed one clock cycle of the oscillation clock signal CLKvco, so that the first clock signal CLKout does not cause glitches when the frequency is switched.
In one application example, a first-in first-out queue FIFO (First in First out), shown in fig. 6, whose read clock rdclk and write clock wrclk generally operate under different clock domains. Suppose that the write clock wrclk is synchronized with the input data datain, while the read clock rdclk is generated by a local PLL. During operation, the FIFO will have a full (full) or empty (empty) status due to possible frequency differences between the read clock rdclk and the write clock wrclk, which may cause errors. Further, the greater the frequency difference between the read clock rdclk and the write clock wrclk, the faster the state of full (full) or read empty (empty) will occur.
To solve the above problems, two methods are generally employed. The first method increases the depth of the FIFO; the second method reduces the frequency difference of the read clock rdclk and the write clock wrclk.
However, for the first aspect, increasing the depth of the FIFO necessarily increases design complexity, thereby increasing area. In the second aspect, however, the frequency difference between the read clock rdclk and the write clock wrclk is reduced by adjusting the output clock of the PLL. Assuming that the PLL output clock is the read clock, it is necessary to make the frequency of the output clock the same as the write clock of the FIFO. For a PLL that provides only integer division, the coverage of the output frequency that it can provide is likely to not meet the requirement of having the output clock be the same as the write clock frequency, and a fractional division structure needs to be added to the PLL to enable the PLL to meet the requirement of the write clock frequency. The addition of the fractional division structure also increases design complexity and area.
The system for automatically recovering the external clock based on the PLL is used for providing the read clock or the write clock for the FIFO, so that the problems can be well solved.
It is assumed that the first clock signal CLKout output by the PLL capable of dynamically switching the output clock frequency proposed in the embodiment of the present invention is taken as the read clock rdclk of the FIFO. Due to the limited output frequency range of the integer editable PLL, the frequency Frdclk of the read clock rdclk is difficult to be the same as the frequency Fwrclk of the externally supplied write clock wrclk.
By configuration, the read clock frequency Frdclk is made slightly lower than the write clock frequency Fwrclk. This configuration may result in a higher write speed of the FIFO than a read speed, and the data in the FIFO may slowly increase.
When the FIFO is about to be full, a near full signal almost_full will be issued. The system dynamically switches the divided signal of the output divider according to the near-full signal almost_full to change the frequency of the first clock signal CLKout, i.e. the read clock frequency Frdclk. The new read clock frequency Frdclk is made slightly higher than the write clock frequency Fwrclk, so that the write speed of FIFO is made smaller than the read speed, and the data in FIFO will be reduced slowly.
When the FIFO is to be read empty, a near empty signal almost_empty will be issued. The system dynamically switches the frequency division signal of the output frequency divider according to the near-empty signal almost_empty, thereby changing the frequency of the first clock signal CLKout, i.e. the read clock frequency Frdclk. The new read clock frequency Frdclk is made lower than the write clock frequency Fwrclk, thereby making the write speed of the FIFO greater than the read speed.
By repeating the above actions, the FIFO can not be in a full or empty state under the condition of dynamically switching the reading clock rdclk.
The invention provides a system for dynamically switching the output frequency of a PLL, which realizes the dynamic switching of a frequency division signal of an output frequency divider by setting a dynamic switching circuit for the output frequency divider of the editable PLL, so that a user does not need to reset and relock the editable PLL when changing the output clock of the editable PLL; and effectively avoids glitches generated during the output clock switching of the editable PLL.
The foregoing detailed description of the invention has been presented for purposes of illustration and description, and it should be understood that the invention is not limited to the particular embodiments disclosed, but is intended to cover all modifications, equivalents, alternatives, and improvements within the spirit and principles of the invention.
Claims (5)
1. The system for dynamically switching the output frequency of the PLL comprises an editable PLL which consists of a phase-locked loop PLL and an output frequency divider, wherein the editable PLL locks an externally input clock signal through the phase-locked loop PLL, and outputs an oscillation clock signal after the phase-locked loop PLL is locked, and the oscillation clock signal is divided by the output frequency divider to output a first clock signal;
the circuit is characterized by further comprising a dynamic switching circuit; the dynamic switching circuit comprises a judging sub-circuit and a switching sub-circuit; the judging sub-circuit is used for judging the validity of a first switching signal input from the outside according to the first clock signal; the switching sub-circuit is used for outputting a preset configuration frequency division control signal when the first switching signal is invalid; outputting a memory frequency division control signal generated by an externally input dynamic frequency division control signal when the validity of the first switching signal is valid or once valid; when the first switching signal is effective, the memory frequency division control signal is a dynamic frequency division control signal; when the first switching signal is effective, the memory frequency division control signal is a dynamic frequency division control signal when the first switching signal is effective in the last time;
the output frequency divider outputs a first clock signal according to the configuration frequency division control signal or the memory frequency division control signal.
2. The system of claim 1, wherein the first switching signal is determined to be active when a pulse width of the first switching signal is greater than one clock cycle of the first clock signal; otherwise, the first switching signal is invalid.
3. The system of claim 1, wherein the validity of the first switching signal is inactive, active, or once active; after the first switching signal is judged to be valid for the first time, the validity is once valid; the validity is valid and not once valid for a time when the first switching signal is determined to be valid.
4. The system of claim 1, wherein the decision sub-circuit comprises a first D flip-flop, a second D flip-flop, and an and gate; the first D trigger outputs a first switching signal input from the outside from a Q end of the first D trigger according to a first clock signal and sends the first switching signal to the second D trigger; the second D trigger outputs the Q end output signal of the first D trigger from the Q end thereof according to a first clock signal; the AND gate receives the output signals of the first D trigger and the second D trigger, and generates a second switching signal, wherein the second switching signal is used for representing the validity of the first switching signal.
5. The system of claim 1, wherein the switching sub-circuit comprises a third D flip-flop, a fourth D flip-flop, and a selector; the third D trigger outputs working voltage from the Q end of the third D trigger according to the second switching signal; the fourth D trigger outputs an externally input dynamic frequency division control signal from the Q end of the fourth D trigger according to the second switching signal to serve as a memory frequency division control signal; the selector receives the output signal of the third D trigger as a selection control signal, and selects a preset configuration frequency division control signal or a memory frequency division control signal output by the fourth D trigger as an output signal.
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| CN1617452A (en) * | 2003-11-10 | 2005-05-18 | 夏普株式会社 | PLL clock signal generation circuit |
| CN101860366A (en) * | 2004-03-09 | 2010-10-13 | 阿尔特拉公司 | The highly configurable PLL architecture that is used for FPGA (Field Programmable Gate Array) |
| CN103346790A (en) * | 2013-07-19 | 2013-10-09 | 苏州磐启微电子有限公司 | Frequency synthesizer capable of being locked quickly |
| CN105553447A (en) * | 2014-11-03 | 2016-05-04 | 上海华虹宏力半导体制造有限公司 | Clock switching circuit |
| CN109639271A (en) * | 2018-12-12 | 2019-04-16 | 上海华力集成电路制造有限公司 | Lock the phaselocked loop of indicating circuit and its composition |
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| US8125253B2 (en) * | 2009-11-02 | 2012-02-28 | Texas Instruments Incorporated | System and method for dynamically switching between low and high frequency reference clock to PLL and minimizing PLL output frequency changes |
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| CN1617452A (en) * | 2003-11-10 | 2005-05-18 | 夏普株式会社 | PLL clock signal generation circuit |
| CN101860366A (en) * | 2004-03-09 | 2010-10-13 | 阿尔特拉公司 | The highly configurable PLL architecture that is used for FPGA (Field Programmable Gate Array) |
| CN103346790A (en) * | 2013-07-19 | 2013-10-09 | 苏州磐启微电子有限公司 | Frequency synthesizer capable of being locked quickly |
| CN105553447A (en) * | 2014-11-03 | 2016-05-04 | 上海华虹宏力半导体制造有限公司 | Clock switching circuit |
| CN109639271A (en) * | 2018-12-12 | 2019-04-16 | 上海华力集成电路制造有限公司 | Lock the phaselocked loop of indicating circuit and its composition |
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