CN111352281A - Array substrate and display panel - Google Patents
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- CN111352281A CN111352281A CN202010265966.3A CN202010265966A CN111352281A CN 111352281 A CN111352281 A CN 111352281A CN 202010265966 A CN202010265966 A CN 202010265966A CN 111352281 A CN111352281 A CN 111352281A
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- 239000002184 metal Substances 0.000 claims description 19
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- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 238000007493 shaping process Methods 0.000 abstract description 3
- 230000005611 electricity Effects 0.000 description 10
- 238000013461 design Methods 0.000 description 4
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
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- 238000002161 passivation Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- NPXOKRUENSOPAO-UHFFFAOYSA-N Raney nickel Chemical class [Al].[Ni] NPXOKRUENSOPAO-UHFFFAOYSA-N 0.000 description 1
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- 229910001080 W alloy Inorganic materials 0.000 description 1
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- 238000004891 communication Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
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- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000011787 zinc oxide Substances 0.000 description 1
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136204—Arrangements to prevent high voltage or static electricity failures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/60—Protection against electrostatic charges or discharges, e.g. Faraday shields
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136254—Checking; Testing
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Nonlinear Science (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Mathematical Physics (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Optics & Photonics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Liquid Crystal (AREA)
- Elimination Of Static Electricity (AREA)
Abstract
The application provides an array substrate and a display panel, wherein the array substrate comprises a pixel circuit corresponding to a display area and a test circuit corresponding to a non-display area; one end of the test circuit is electrically connected with the pixel circuit, and the other end of the test circuit is connected with test pads which are arranged at intervals; an electrostatic protection structure is arranged on the other opposite side of the test pad connected with the test circuit, and the electrostatic protection structure and the test pad are arranged in a non-contact manner; wherein a side of the electrostatic protection structure adjacent to the test pad includes a plurality of discharge tips. This application is through before array substrate cutting shaping, set up the electrostatic protection structure of a set of lightning rod framework in its non-wiring region department, it includes a plurality of pointed ends that discharge, when carrying out probe detection, through the electric charge that the pointed end that discharges attracted the probe and produced to the static that makes the in-process of pricking production obtains releasing.
Description
Technical Field
The application relates to the technical field of display, in particular to an array substrate and a display panel.
Background
The Gate driver on Array, referred to as GOA for short, is a driving method for Gate line-by-line scanning, which is implemented by fabricating a Gate line scanning driving signal circuit on an Array substrate by using an Array process in the existing thin film transistor liquid crystal display.
Currently, due to design requirements, there are many test pads for performing various functions, such as celltest pad for performing celltest function, Arraytest pad for performing Arraytest, HVApad for performing HVAcuring, etc. The test pads can be exploded due to electrostatic discharge generated by static electricity charged by a needle point in an instrument in a needle inserting process, so that the test pads cannot well perform corresponding functions, and the stability of a panel is influenced.
Disclosure of Invention
The application provides an array substrate and a display panel, which are used for solving the problem that in the prior art, when a probe is detected, large-scale static electricity is formed to break down a test terminal.
In order to solve the above problems, the technical solution provided by the present application is as follows:
an array substrate comprises a pixel circuit corresponding to a display area and a test circuit corresponding to a non-display area;
one end of the test circuit is electrically connected with the pixel circuit, and the other end of the test circuit is connected with test pads which are arranged at intervals;
an electrostatic protection structure is arranged on the other opposite side of the test pad connected with the test circuit, and the electrostatic protection structure and the test pad are arranged in a non-contact manner;
wherein a side of the electrostatic protection structure adjacent to the test pad includes a plurality of discharge tips.
In the array substrate of the present application, the electrostatic protection structure further includes a common electrode line, and the plurality of discharge tips are connected to the common electrode line.
In the array substrate, the discharge tips and the common electrode lines are manufactured by the same photomask process.
In the array substrate of the present application, the electrostatic protection structure is an annular structure.
In the array substrate of the present application, the electrostatic protection structure surrounds the non-display area and surrounds the test pad.
In the array substrate of the present application, the array substrate includes a first metal layer, the electrostatic protection structure and the first metal layer are disposed on the same layer, and the electrostatic protection structure and the first metal layer are made of the same material.
In the array substrate of the application, the non-display area comprises a wiring area and a non-wiring area between the wiring areas, and the electrostatic protection structure is located in the non-wiring area.
In the array substrate of the present application, the electrostatic protection structure corresponds to each the test pad all is equipped with at least one discharge point.
In the array substrate of the present application, the shape of the discharge tip is triangular.
The application also provides a display panel, which comprises the array substrate.
Has the advantages that: this application is through before array substrate cutting shaping, set up the electrostatic protection structure of a set of lightning rod framework in its non-line region department, it includes a public electrode line, and with a plurality of that public electrode line is connected the point of discharging. When the probes are detected, static electricity carried on the probes is released to the common electrode wire through the discharge tips, so that the situation that the test gasket is substantially damaged in functionality due to large-scale static electricity generated during probe detection is avoided, the test gasket can effectively complete corresponding functions, and the reliability of the display panel is improved.
Drawings
The technical solutions and other advantages of the present application will become apparent from the following detailed description of specific embodiments of the present application when taken in conjunction with the accompanying drawings.
Fig. 1 is a top view of an array substrate according to an embodiment of the present disclosure;
FIG. 2 is an enlarged partial view of the dashed line region A of FIG. 1;
fig. 3 is a schematic structural diagram of an array substrate according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it is to be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the present application and for simplicity in description, and are not intended to indicate or imply that the referenced devices or elements must have a particular orientation, be constructed in a particular orientation, and be operated in a particular manner, and are not to be construed as limiting the present application. Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, features defined as "first", "second", may explicitly or implicitly include one or more of the described features. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; may be mechanically connected, may be electrically connected or may be in communication with each other; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.
In this application, unless expressly stated or limited otherwise, the first feature "on" or "under" the second feature may comprise direct contact of the first and second features, or may comprise contact of the first and second features not directly but through another feature in between. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The following disclosure provides many different embodiments or examples for implementing different features of the application. In order to simplify the disclosure of the present application, specific example components and arrangements are described below. Of course, they are merely examples and are not intended to limit the present application. Moreover, the present application may repeat reference numerals and/or letters in the various examples, such repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. In addition, examples of various specific processes and materials are provided herein, but one of ordinary skill in the art may recognize applications of other processes and/or use of other materials.
In the prior art, the display panel has many test pads to accomplish various functions due to design requirements, when the probe is detected, the test pads can be exploded due to the electrostatic discharge generated by the static of the needle point in the instrument in the needle inserting process, so that the test pads cannot well play a corresponding function, the stability of the display panel is influenced, and the yield of the display panel is poor.
Example one
Referring to fig. 1, a top view of an array substrate provided in an embodiment of the present application is shown.
In the present embodiment, the array substrate includes a pixel circuit 10 corresponding to the display area 100 and a test circuit 20 corresponding to the non-display area 200.
Before the array substrate is cut and formed, the test circuit 20 is disposed on the non-display area 200 below the display area 100, one end of the test circuit 20 is electrically connected to the pixel circuit 10, and the other end is connected to test pads 30 arranged at intervals.
The test pads 30 include, but are not limited to, dot screen test pads, array test pads, and HVA test pads that complete hvact.
It should be noted that, in this embodiment, before the array substrate is cut and formed, the array substrate includes a plurality of sets of the test pads 30 arranged at intervals, and this embodiment only describes one set of the design.
Referring to fig. 2, in the present embodiment, before the array substrate is cut and formed, an electrostatic protection structure 40 is disposed on the opposite side of the test pad 30 connected to the test circuit 20, and the electrostatic protection structure 40 and the test pad 30 are disposed in a non-contact manner.
In this embodiment, the non-display area 200 includes routing areas and non-routing areas located between the routing areas, and the electrostatic protection structure 40 is located in the non-routing areas.
In this embodiment, the electrostatic protection structure 40 is disposed around the non-display area 200.
Wherein, in the non-display area 200, the electrostatic structure 40 is disposed around the test pad 30, and the electrostatic structure 40 is a ring structure.
In the embodiment, the electrostatic protection structure 40 is a single metal layer structure, and this structure design can reduce the thickness of the array substrate.
Before the array substrate is cut and shaped, the electrostatic protection structure 40 includes a common electrode line 402; and a plurality of discharge tips 401 disposed at intervals are disposed at one side of the electrostatic protection structure 40 close to the test pad 30.
In this embodiment, before the array substrate is cut and formed, the discharge tips 401 and the common electrode lines 402 are manufactured by the same mask process, so that the manufacturing steps and the manufacturing cost are saved.
In the present embodiment, the shape of the discharge tip 401 includes, but is not limited to, a triangle, and the discharge tip 401 and the test pad 30 have a certain distance therebetween, i.e., a non-contact arrangement.
The discharge tip 401 is used for guiding static electricity remaining on the probe to be released to the common electrode line 401 when the array substrate is subjected to probe test, so that substantial damage to functions of the test pad due to large-scale static electricity generated when the test pad 30 is pricked is avoided, and the production yield of the display panel is improved.
In the present embodiment, the height and size of the discharge tip 401 are not particularly limited.
In the present embodiment, the esd protection structure 40 is provided with at least one discharge tip 401 corresponding to each of the test pads 30.
In the embodiment, before the array substrate is cut and formed, a group of electrostatic protection structures 40 having a lightning rod structure is disposed at a non-routing area thereof, and includes a common electrode line 402 and a plurality of discharge tips 401 connected to the common electrode line 402. When the probe is detected, static electricity carried on the probe is released to the common electrode line 401 through the discharge tip 401 corresponding to the test pad 30, so that substantial damage to the functionality of the test pad 30 due to large-scale static electricity generated by the test pad 30 during the probe detection is avoided, the test pad 30 can be effectively ensured to complete the corresponding function, and the reliability of the display panel is improved.
Referring to fig. 3, a schematic structural diagram of an array substrate according to an embodiment of the present disclosure is shown.
In this embodiment, the array substrate includes a substrate 501, and a first metal layer 502, a first insulating layer 503, an active layer 504, an active layer doping layer 505, a second metal layer 506, and a second insulating layer 507 sequentially stacked on the substrate 501.
In this embodiment, the substrate 501 may be one of a glass substrate, a quartz substrate, a resin substrate, and the like.
The substrate 110 may also be a flexible substrate, and the material of the flexible substrate may include polyimide.
Further, in this embodiment, the substrate 501 is a glass substrate.
In this embodiment, the first metal layer 502 is patterned to form a gate electrode and a gate line of a thin film transistor.
The first insulating layer 503 is disposed on the surface of the first metal layer 502 and is a gate insulating layer.
The first insulating layer 503 is mainly used to isolate the first metal layer 502 from the active layer 504.
The material of the first insulating layer 503 may be other insulating inorganic materials such as silicon nitride, silicon oxide, or silicon oxynitride.
In this embodiment, the second metal layer 506 includes a second metal trace.
In this embodiment, the array substrate includes a plurality of sets of the test pads 30 arranged at intervals.
Wherein, two adjacent groups of the test pads 30 are connected by the second metal trace.
In the present embodiment, the material of the active layer 504 includes a metal oxide, which includes indium gallium zinc oxide.
In this embodiment, the second insulating layer 507 may be a passivation layer or a cover plate.
Further, the second insulating layer 507 is a passivation layer.
Referring to fig. 2 and fig. 3, in the present embodiment, before the array substrate is cut and formed, the electrostatic protection structure 40 and the first metal layer 502 are disposed on the same layer, and the electrostatic protection structure 40 includes a common electrode line 402 and a plurality of discharge tips 401 connected to the common electrode line 402.
Wherein, the electrostatic protection structure 40 is made of the same material as the first metal layer 502.
In this embodiment, the metal material of the first metal layer 502 may be one of metals such as molybdenum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, or copper, and a combination of these metal materials may also be used.
Example two
This embodiment provides a display panel, which includes the array substrate according to the first embodiment, which has been described in detail in the first embodiment, and a description thereof is not repeated here.
The application provides an array substrate and a display panel, wherein the array substrate comprises a pixel circuit corresponding to a display area and a test circuit corresponding to a non-display area before cutting and forming; one end of the test circuit is electrically connected with the pixel circuit, and the other end of the test circuit is connected with test pads which are arranged at intervals; an electrostatic protection structure is arranged on the other opposite side of the test pad connected with the test circuit, and the electrostatic protection structure and the test pad are arranged in a non-contact manner; wherein a side of the electrostatic protection structure adjacent to the test pad includes a plurality of discharge tips.
This application is through before array substrate cutting shaping, set up a set of electrostatic protection structure that has the lightning rod framework in its non-line region department, it includes a public electrode line, and with a plurality of that public electrode line is connected the point of discharging. When the probes are detected, static electricity carried on the probes is released to the common electrode line through the discharge tips corresponding to the test pads, so that the problem that the functionality of the test pads is substantially damaged due to large-scale static electricity generated by the test pads during the detection of the probes is avoided, the test pads can effectively complete the corresponding functions of the test pads, and the reliability of the display panel is improved.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
The array substrate and the display panel provided by the embodiments of the present application are described in detail above, and the principles and embodiments of the present application are explained herein by applying specific examples, and the description of the embodiments is only used to help understand the technical solutions and core ideas of the present application; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.
Claims (10)
1. The array substrate is characterized by comprising a pixel circuit corresponding to a display area and a test circuit corresponding to a non-display area;
one end of the test circuit is electrically connected with the pixel circuit, and the other end of the test circuit is connected with test pads which are arranged at intervals;
an electrostatic protection structure is arranged on the other opposite side of the test pad connected with the test circuit, and the electrostatic protection structure and the test pad are arranged in a non-contact manner;
wherein a side of the electrostatic protection structure adjacent to the test pad includes a plurality of discharge tips.
2. The array substrate of claim 1, wherein the electrostatic protection structure further comprises a common electrode line, and a plurality of the discharge tips are connected to the common electrode line.
3. The array substrate of claim 2, wherein the discharge tips and the common electrode lines are formed by a same masking process.
4. The array substrate of claim 1, wherein the electrostatic protection structure is a ring structure.
5. The array substrate of claim 4, wherein the electrostatic protection structure surrounds the non-display area and surrounds the test pad.
6. The array substrate of claim 1, wherein the array substrate comprises a first metal layer, the electrostatic protection structure is disposed on the same layer as the first metal layer, and the electrostatic protection structure and the first metal layer are made of the same material.
7. The array substrate of claim 1, wherein the non-display area comprises routing areas and non-routing areas located between the routing areas, and the electrostatic protection structure is located in the non-routing areas.
8. The array substrate of claim 1, wherein the esd protection structure has at least one discharge tip corresponding to each of the test pads.
9. The array substrate of claim 1, wherein the discharge tips are triangular in shape.
10. A display panel comprising the array substrate according to any one of claims 1 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010265966.3A CN111352281A (en) | 2020-04-07 | 2020-04-07 | Array substrate and display panel |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010265966.3A CN111352281A (en) | 2020-04-07 | 2020-04-07 | Array substrate and display panel |
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| CN111352281A true CN111352281A (en) | 2020-06-30 |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111863885A (en) * | 2020-07-01 | 2020-10-30 | 上海天马有机发光显示技术有限公司 | Display panel to be cut, manufacturing method of display panel and display device |
| CN111983858A (en) * | 2020-08-07 | 2020-11-24 | 深圳市华星光电半导体显示技术有限公司 | Display panel |
| CN112201186A (en) * | 2020-10-10 | 2021-01-08 | 深圳市华星光电半导体显示技术有限公司 | Test component group |
| CN114823635A (en) * | 2022-06-29 | 2022-07-29 | 惠科股份有限公司 | Drive substrate and display panel |
| CN114859589A (en) * | 2022-06-07 | 2022-08-05 | Tcl华星光电技术有限公司 | Display panel and lighting method thereof |
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