CN111343801A - Impedance optimization method for circuit board via hole and circuit board - Google Patents
Impedance optimization method for circuit board via hole and circuit board Download PDFInfo
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- 230000008569 process Effects 0.000 claims abstract description 15
- 238000012545 processing Methods 0.000 claims description 4
- 238000003825 pressing Methods 0.000 claims description 3
- 238000003466 welding Methods 0.000 claims description 3
- 230000005540 biological transmission Effects 0.000 abstract description 16
- 230000009286 beneficial effect Effects 0.000 abstract description 2
- 239000011800 void material Substances 0.000 description 10
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
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- H05K3/0005—Apparatus or processes for manufacturing printed circuits for designing circuits by computer
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Abstract
The invention discloses an impedance optimization method of a circuit board via hole, which comprises the steps of designing a wire on a circuit board according to the design requirement of the circuit board; determining a target routing with a via hole design according to the routing path of the routing; and (3) performing size increase treatment on the anti-bonding pads at the through holes on the GND layer adjacent to the input signal layer and the output signal layer of the target wiring, so that the impedance at the through holes of the target wiring meets the wiring impedance requirement. Therefore, the impedance continuity at the via is optimized by changing the shape of the anti-pad at the routing via, so that the integrity requirement of a transmission signal is met under the condition of not increasing the process cost; moreover, what this application changed is that the anti-pad shape of via hole department on the input signal layer of walking the line and the respective adjacent GND layer of output signal layer can not influence the impedance of walking the line when optimizing via hole department impedance. The invention also discloses a circuit board which has the same beneficial effect as the impedance optimization method.
Description
Technical Field
The invention relates to the field of circuit board design, in particular to an impedance optimization method of a circuit board through hole and a circuit board.
Background
According to transmission line theory, the point of impedance discontinuity affects the integrity of the transmitted signal. In the circuit board wiring design, stubs exist at the wiring via holes, so that the impedance at the via holes is capacitive, that is, the impedance at the via holes is low, so that the impedance at the via holes is discontinuous, the integrity of transmission signals is restricted, and particularly for the wiring with high signal transmission rate, the continuity of the via hole impedance is more obviously affected. In the prior art, via stubs are usually removed by back drilling or deep micro-via processes to optimize the impedance at the via. However, the via stub cannot be completely removed by the back drilling process, and the stub within about 12 mils still remains, which affects the integrity of the transmission signal; deep micro-hole processes can completely remove via stubs, but the process cost is high.
Therefore, how to provide a solution to the above technical problem is a problem that needs to be solved by those skilled in the art.
Disclosure of Invention
The invention aims to provide an impedance optimization method of a circuit board via hole and a circuit board, which optimize the impedance continuity of the via hole by changing the shape of an inverse pad at the routing via hole, thereby meeting the integrity requirement of a transmission signal under the condition of not increasing the process cost; moreover, what this application changed is that the anti-pad shape of via hole department on the input signal layer of walking the line and the respective adjacent GND layer of output signal layer can not influence the impedance of walking the line when optimizing via hole department impedance.
In order to solve the technical problem, the invention provides an impedance optimization method of a circuit board via hole, which comprises the following steps:
designing the routing on the circuit board according to the design requirement of the circuit board;
determining a target routing with a via hole design according to the routing path of the routing;
and performing size increasing treatment on the anti-bonding pads at the through holes on the GND layer adjacent to the input signal layer and the output signal layer of the target wiring, so that the impedance at the through holes of the target wiring meets the wiring impedance requirement.
Preferably, the target trace is a differential signal line; the original anti-welding disc at the target routing through hole is oval;
correspondingly, the process of performing size increase processing on the anti-bonding pad at the via hole on the GND layer adjacent to each of the input signal layer and the output signal layer of the target trace includes:
and a structure formed by sequentially splicing an M-shaped structure, an inverted trapezoidal structure and a rectangular structure is added on the original anti-bonding pad structure at the through hole on the GND layer.
Preferably, the structure formed by sequentially splicing the M-shaped structure, the inverted trapezoidal structure and the rectangular structure is symmetrical about a central axis of the original anti-pad structure.
Preferably, the differential signal line includes a first signal line and a second signal line, and the profile of the M-shaped structure includes an inner V-shaped profile and an outer eight-shaped profile composed of a left-falling profile and a right-falling profile; wherein:
the left-falling outline is superposed with a circle which takes the center of a through hole of the first signal line on the GND layer as the center of a circle and has a radius larger than the minimum required radius value of a through hole reversed pad; the right-pressing profile is coincided with a circle which takes the center of the through hole of the second signal line on the GND layer as the center of a circle and has a radius larger than the minimum required radius value of the reverse pad of the through hole.
Preferably, the straight distance between the two ends of the left falling/right falling profile is close to 3 times of the track width.
Preferably, the target trace intersects its corresponding via at an angle of 45 degrees.
In order to solve the technical problem, the invention also provides a circuit board, and the circuit board adopts any one of the above impedance optimization methods for circuit board via holes to design the circuit board via holes.
Preferably, the circuit board is provided with a GND via hole penetrating through the circuit board.
The invention provides an impedance optimization method of a circuit board via hole, which is characterized in that a wire on a circuit board is designed according to the design requirement of the circuit board; determining a target routing with a via hole design according to the routing path of the routing; and (3) performing size increase treatment on the anti-bonding pads at the through holes on the GND layer adjacent to the input signal layer and the output signal layer of the target wiring, so that the impedance at the through holes of the target wiring meets the wiring impedance requirement. Therefore, the impedance continuity at the via is optimized by changing the shape of the anti-pad at the routing via, so that the integrity requirement of a transmission signal is met under the condition of not increasing the process cost; moreover, what this application changed is that the anti-pad shape of via hole department on the input signal layer of walking the line and the respective adjacent GND layer of output signal layer can not influence the impedance of walking the line when optimizing via hole department impedance.
The invention also provides a circuit board which has the same beneficial effects as the impedance optimization method.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed in the prior art and the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic structural diagram of an impedance optimization method for a via hole of a circuit board according to an embodiment of the present invention;
FIG. 2 is a graph of impedance at a via provided by an embodiment of the present invention;
FIG. 3 is a 3D model diagram of a via according to an embodiment of the present invention;
FIG. 4 is a cross-sectional view of a via 3D model according to an embodiment of the present invention;
FIG. 5 is a top view of a via model before via optimization according to an embodiment of the present invention;
FIG. 6 is a top view of a via model after via optimization according to an embodiment of the present invention;
FIG. 7 is an additional block diagram of an anti-pad shape provided by an embodiment of the present invention;
FIG. 8 is a cloud of a distribution of a stripline cross-section electric field provided by an embodiment of the invention;
FIG. 9 is a graph of stripline impedance as a function of reference plane width in accordance with an embodiment of the present invention;
FIG. 10 is a side view of a via 3D model according to an embodiment of the present invention;
FIG. 11 is a top view of a via model before via optimization according to an embodiment of the present invention;
FIG. 12 is a graph of impedance curves before optimization of a via for a d _ void varying from 30mil to 55mil according to an embodiment of the present invention;
FIG. 13 is a graph showing the return loss of differential signals when d _ void varies from 30mil to 55mil before optimization of a via according to an embodiment of the present invention;
FIG. 14 is a graph of impedance curves for a via optimized d _ void that varies from 30mil to 55mil, in accordance with an embodiment of the present invention;
fig. 15 is a graph showing the return loss of differential signals when d _ void varies from 30mil to 55mil after the via optimization according to the embodiment of the present invention.
Detailed Description
The core of the invention is to provide an impedance optimization method of a circuit board via hole and a circuit board, which optimize the impedance continuity of the via hole by changing the shape of an inverse pad at the routing via hole, thereby meeting the integrity requirement of a transmission signal under the condition of not increasing the process cost; moreover, what this application changed is that the anti-pad shape of via hole department on the input signal layer of walking the line and the respective adjacent GND layer of output signal layer can not influence the impedance of walking the line when optimizing via hole department impedance.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a schematic structural diagram of an impedance optimization method for a via hole of a circuit board according to an embodiment of the present invention.
The impedance optimization method of the circuit board via hole comprises the following steps:
step S1: and designing the routing on the circuit board according to the design requirement of the circuit board.
Specifically, a plurality of components are arranged on the circuit board according to application function requirements, and the components are connected through wiring laid on the circuit board. It should be noted that, the routing design of the components is as follows: 1) the routing starts from the component, when the routing is blocked by other via holes, the routing needs to be wound, if the routing cannot be wound, a cavity can be dug on the routing by taking the via hole as the center and taking the size of the bonding pad as the reference so as to separate the routing from the via hole; 2) the routing starts from a component, and when encountering other components, the routing needs to be bypassed or opened through hole layer changing routing; 3) the wiring starts from the components, and when other wirings are met, the wiring needs to be punched for layer changing.
Step S2: and determining the target routing with the via hole design according to the routing path of the routing.
Specifically, considering that in the circuit board routing design, stubs exist at the routing via holes, so that impedance at the via holes presents a capacitive property, that is, impedance at the via holes is low, so that impedance at the via holes is discontinuous, and integrity of transmission signals is restricted, the application needs to optimize impedance continuity at the via holes to meet the requirement of integrity of the transmission signals.
Based on this, according to the routing path of the routing on the circuit board, the routing (called target routing) with the via hole design is determined from the routing on the circuit board, so as to optimize the impedance continuity at the via hole subsequently.
Step S3: and (3) performing size increase treatment on the anti-bonding pads at the through holes on the GND layer adjacent to the input signal layer and the output signal layer of the target wiring, so that the impedance at the through holes of the target wiring meets the wiring impedance requirement.
Specifically, in order to optimize the impedance continuity at the via hole, the technical means adopted by the application is as follows: increasing the size of the anti-pad at the via of the target trace can increase the impedance at the via to approach the target impedance meeting the trace impedance requirement.
In addition, referring to fig. 2, fig. 2 is a graph illustrating impedance at a via according to an embodiment of the present invention. In fig. 2, the area a and the area C reflect the impedance of the lead laid in the anti-pad area, and since the part of the trace does not have the reference layer, the trace impedance will rise; the area B reflects the impedance of the via part, and the impedance of the via part is lower due to the stub of the via part. Based on this, considering that if the size of the anti-pad area where the trace is laid is increased, although the impedance at the via (area B) can be increased to make it close to the target impedance meeting the trace impedance requirement, the impedance at the lead area (area a, area C) can be increased at the same time to make it far from the target impedance meeting the trace impedance requirement, the application performs the size increase processing on the anti-pad at the via on the GND layer adjacent to each other of the input signal layer and the output signal layer of the target trace, so as to optimize the impedance at the via without affecting the impedance at the lead area.
The invention provides an impedance optimization method of a circuit board via hole, which is characterized in that a wire on a circuit board is designed according to the design requirement of the circuit board; determining a target routing with a via hole design according to the routing path of the routing; and (3) performing size increase treatment on the anti-bonding pads at the through holes on the GND layer adjacent to the input signal layer and the output signal layer of the target wiring, so that the impedance at the through holes of the target wiring meets the wiring impedance requirement. Therefore, the impedance continuity at the via is optimized by changing the shape of the anti-pad at the routing via, so that the integrity requirement of a transmission signal is met under the condition of not increasing the process cost; moreover, what this application changed is that the anti-pad shape of via hole department on the input signal layer of walking the line and the respective adjacent GND layer of output signal layer can not influence the impedance of walking the line when optimizing via hole department impedance.
On the basis of the above-described embodiment:
as an alternative embodiment, the target trace is a differential signal line; the original anti-welding disc at the target routing through hole is oval;
correspondingly, the process of carrying out size increasing processing on the anti-bonding pad at the through hole on the GND layer adjacent to the input signal layer and the output signal layer of the target wiring comprises the following steps:
and a structure formed by sequentially splicing an M-shaped structure, an inverted trapezoidal structure and a rectangular structure is added on the original anti-bonding pad structure at the through hole on the GND layer.
Specifically, when the target trace is a differential signal line, the original antipad shape of the differential signal line at the via hole before the via hole optimization is an ellipse, as shown in fig. 3 and 4, the two via holes in the middle are the via holes of the differential signal line, the antipad shape at the via hole of the differential signal line is an ellipse (the top view is shown in fig. 5), input and output refer to the flow direction of the transmission signal, and stub1 and stub2 refer to the lengths of the upper stub and the lower stub, respectively.
On the basis of the original oval anti-pad structure, the anti-pad structure formed by sequentially splicing the M-shaped structure, the inverted trapezoidal structure and the rectangular structure is added, and the D graph shown in the figures 6 and 7 is used, so that the size of the anti-pad is increased.
As an optional embodiment, the structure formed by sequentially splicing the M-shaped structure, the inverted trapezoidal structure and the rectangular structure is symmetrical about the central axis of the original anti-pad structure.
Specifically, as shown in fig. 6, the anti-pad structure added in the present application is symmetrical about the central axis of the original anti-pad structure, so as to better optimize the impedance continuity at the via hole.
As an alternative embodiment, the differential signal line includes a first signal line and a second signal line, and the profile of the M-shaped structure includes an inner V-shaped profile and an outer eight-shaped profile composed of a left-falling profile and a right-falling profile; wherein:
the left-falling outline is coincided with a circle which takes the center of a through hole of the first signal line on the GND layer as the center of a circle and has a radius larger than the minimum required radius value of the through hole reversed pad; the right-pressing profile coincides with a circle which takes the center of a through hole of the second signal line on the GND layer as the center of a circle and has a radius larger than the minimum required radius value of the reverse pad of the through hole.
Specifically, the differential signal line means that two signal lines transmit signals, the amplitudes of the transmission signals on the two signal lines are the same, and the phases of the transmission signals are opposite, and the differential signal is the voltage difference between the two signal lines, that is, the differential signal line includes a first signal line and a second signal line.
The profile of the M-shaped structure in the added anti-pad structure of the present application includes an inner V-shaped profile and an outer eight-shaped profile, which is further divided into a left-falling profile and a right-falling profile. More specifically, the skimming contour is coincided with a circle which takes the center of a through hole of the first signal line on the GND layer as the center of a circle and has a radius larger than the minimum required radius value of the through hole reversed pad; similarly, the right-pressed profile coincides with a circle which takes the center of a via hole of the second signal line on the GND layer as the center of a circle and has a radius larger than the minimum required radius value of the via hole reverse pad. For example, in a general process, it is required that the diameter of the anti-pad of the via hole of the differential signal line (i.e., the size of the signal hole avoiding the GND layer) is at least 30mil, and as shown in fig. 6, the right-hand contour coincides with a circle having a diameter d of 30mil centered on the center of the via hole of the second signal line on the GND layer.
As an alternative embodiment, the straight distance between the two ends of the left-falling/right-falling profile is set to be approximately 3 times the track width.
Specifically, as shown in fig. 7, the straight distance between the two ends of the left-falling/right-falling profile is W1, and the reference surface width W1 is selected, although ideally, the wider the reference surface is within a certain width range, the closer the transmission line impedance is to the target impedance, but the larger the reference surface is, the further the transmission line impedance is away from the target impedance, the further analysis is as follows:
the distribution of the electric field of the cross section of the strip line is analyzed by using a three-dimensional field analysis tool HFSS (High Frequency Structure Simulator), and a distribution cloud of the electric field of the cross section of the strip line as shown in fig. 8 is obtained. From the analysis results, it is inferred that the electric field (0 to 20dB) is mainly concentrated in the range of 3W width (W indicates the width of the strip line), and therefore, when the reference plane is close to 3W, the trace impedance can be considered to be close to the target impedance. Similarly, the impedance simulation using HFSS to verify the above reasoning, such as analyzing the strip line with the target impedance of 42.5ohm, and scanning the impedance curve with the reference surface width as shown in fig. 9, it can be seen that when the reference surface is close to 3W, the trace impedance value can be converged around 42.5ohm more smoothly.
Based on this, the straight distance W1 between both ends of the left-falling/right-falling profile is set to be close to 3 times the track width, and W1 is 3 times the target track width W.
As an alternative embodiment, the target trace intersects its corresponding via at an angle of 45 degrees.
Specifically, the target trace of the present application intersects with its corresponding via at an angle of 45 degrees, as shown in fig. 6, which enables faster coupling of transmission signals on the trace.
In addition, still be equipped with the GND via hole that runs through the circuit board on the circuit board of this application, as shown in FIG. 3, the circuit of being convenient for flows back nearby.
In conjunction with the above technical solutions, the circuit boards of fig. 10 and 11 are taken as examples to describe the basic embodiments of the present invention in detail:
as shown in fig. 11, the original anti-pad shape at the via of the differential signal line is an ellipse, and L1 and L2 determine the size of the ellipse anti-pad. Referring to fig. 10, the signal hole is back drilled with 12mil stubs above and below (the back drilling can ensure the stub length is not more than 12 mil). The diameter of the via hole is 12mil, the line width of the differential signal line is 4.4mil, the distance s is 7mil, the impedance is Z0 and 85ohm, and the center distance between the two middle signal holes is pitch and 40 mil.
Given that vias exhibit capacitive behavior when stub is present, the present application optimizes via impedance by increasing the antipad size at the via. Referring to fig. 12 and 13, fig. 12 is a graph of impedance when d _ void changes from 30mil to 55mil before optimizing a via according to an embodiment of the present invention, and fig. 13 is a graph of return loss of a differential signal when d _ void changes from 30mil to 55mil before optimizing a via according to an embodiment of the present invention. The "D" pattern shown in fig. 7 is added to each of the four layers L4, L6, L9 and L11, where W1 is 3 × W13.2 mil, and D _ void is scanned again from 30mil to 55mil, and the results are shown in fig. 14 and fig. 15.
Comparing the impedance curves, the optimal impedance range in fig. 12 is 80-93 ohm (D _ void is 42mil), and the optimal impedance range in fig. 14 is 80-90 ohm (D _ void is 55mil), the impedance optimization is obvious, and it is obvious that the impedance of the lead area is not obviously increased after the "D" area is increased. Comparing again the return loss curves, the return loss curve in fig. 15 is generally better than the return loss curve in fig. 13.
In general, the return loss curve of the high speed via is preferably less than-20 dB at 1.5 times fundamental frequency, for example, the fundamental frequency of 25G bps high speed signal is 12.5GHz, the fundamental frequency is 18.75GHz at 1.5 times, and the d _ void is 55mil in fig. 15 can be less than-20 dB at 18.75 GHz.
The application also provides a circuit board, and the circuit board adopts any one of the impedance optimization methods for the circuit board via hole to design the circuit board via hole.
As an alternative embodiment, the circuit board is provided with a GND via hole penetrating through the circuit board.
For the introduction of the circuit board provided in the present application, reference is made to the above-mentioned embodiments of the impedance optimization method, which are not repeated herein.
It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (8)
1. A method for optimizing the impedance of a via hole of a circuit board is characterized by comprising the following steps:
designing the routing on the circuit board according to the design requirement of the circuit board;
determining a target routing with a via hole design according to the routing path of the routing;
and performing size increasing treatment on the anti-bonding pads at the through holes on the GND layer adjacent to the input signal layer and the output signal layer of the target wiring, so that the impedance at the through holes of the target wiring meets the wiring impedance requirement.
2. The method of claim 1, wherein the target trace is a differential signal line; the original anti-welding disc at the target routing through hole is oval;
correspondingly, the process of performing size increase processing on the anti-bonding pad at the via hole on the GND layer adjacent to each of the input signal layer and the output signal layer of the target trace includes:
and a structure formed by sequentially splicing an M-shaped structure, an inverted trapezoidal structure and a rectangular structure is added on the original anti-bonding pad structure at the through hole on the GND layer.
3. The method for optimizing the impedance of a via hole in a circuit board according to claim 2, wherein the structure formed by sequentially splicing the M-shaped structure, the inverted trapezoidal structure and the rectangular structure is symmetrical about a central axis of the original anti-pad structure.
4. The method for impedance optimization of a circuit board via according to claim 3, wherein the differential signal line comprises a first signal line and a second signal line, and the profile of the M-shaped structure comprises an inner V-shaped profile and an outer eight-shaped profile consisting of a left-falling profile and a right-falling profile; wherein:
the left-falling outline is superposed with a circle which takes the center of a through hole of the first signal line on the GND layer as the center of a circle and has a radius larger than the minimum required radius value of a through hole reversed pad; the right-pressing profile is coincided with a circle which takes the center of the through hole of the second signal line on the GND layer as the center of a circle and has a radius larger than the minimum required radius value of the reverse pad of the through hole.
5. The method for optimizing the impedance of a via hole in a circuit board according to claim 4, wherein the straight distance between the two ends of the left-falling/right-falling profile is set to be approximately 3 times the track width.
6. The method of claim 1, wherein the target trace intersects its corresponding via at a 45 degree angle.
7. A circuit board characterized in that the circuit board is subjected to circuit board via design using the impedance optimization method for circuit board vias according to any one of claims 1 to 6.
8. The circuit board of claim 7, wherein the circuit board is provided with a GND via passing through the circuit board.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010244846.5A CN111343801B (en) | 2020-03-31 | 2020-03-31 | Impedance optimization method for circuit board via hole and circuit board |
| PCT/CN2021/071240 WO2021196828A1 (en) | 2020-03-31 | 2021-01-12 | Impedance optimization method for circuit board via holes, and circuit board |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010244846.5A CN111343801B (en) | 2020-03-31 | 2020-03-31 | Impedance optimization method for circuit board via hole and circuit board |
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| CN111343801A true CN111343801A (en) | 2020-06-26 |
| CN111343801B CN111343801B (en) | 2021-10-22 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112888155A (en) * | 2021-01-14 | 2021-06-01 | 合肥移瑞通信技术有限公司 | Circuit board, circuit board via hole optimization method, electronic device and storage medium |
| WO2021196828A1 (en) * | 2020-03-31 | 2021-10-07 | 苏州浪潮智能科技有限公司 | Impedance optimization method for circuit board via holes, and circuit board |
| CN113709962A (en) * | 2021-07-14 | 2021-11-26 | 浪潮商用机器有限公司 | Differential signal transmission multilayer PCB structure |
| CN114423184A (en) * | 2021-12-29 | 2022-04-29 | 浪潮(山东)计算机科技有限公司 | Method and device for manufacturing special-shaped anti-welding pad, electronic equipment and storage medium |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114143961B (en) * | 2021-11-29 | 2023-07-21 | 中汽创智科技有限公司 | Circuit board |
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| WO2021196828A1 (en) * | 2020-03-31 | 2021-10-07 | 苏州浪潮智能科技有限公司 | Impedance optimization method for circuit board via holes, and circuit board |
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| CN112888155B (en) * | 2021-01-14 | 2022-04-01 | 合肥移瑞通信技术有限公司 | Circuit board, circuit board via hole optimization method, electronic device and storage medium |
| CN113709962A (en) * | 2021-07-14 | 2021-11-26 | 浪潮商用机器有限公司 | Differential signal transmission multilayer PCB structure |
| CN113709962B (en) * | 2021-07-14 | 2023-05-02 | 浪潮商用机器有限公司 | Differential signal transmission multilayer PCB structure |
| CN114423184A (en) * | 2021-12-29 | 2022-04-29 | 浪潮(山东)计算机科技有限公司 | Method and device for manufacturing special-shaped anti-welding pad, electronic equipment and storage medium |
| CN114423184B (en) * | 2021-12-29 | 2024-05-10 | 浪潮(山东)计算机科技有限公司 | Special-shaped anti-bonding pad manufacturing method and device, electronic equipment and storage medium |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111343801B (en) | 2021-10-22 |
| WO2021196828A1 (en) | 2021-10-07 |
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