CN111327858A - Method, system and device for converting LVDS (Low Voltage differential Signaling) video signal into HDMI (high-definition multimedia interface) signal - Google Patents

Method, system and device for converting LVDS (Low Voltage differential Signaling) video signal into HDMI (high-definition multimedia interface) signal Download PDF

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CN111327858A
CN111327858A CN202010142390.1A CN202010142390A CN111327858A CN 111327858 A CN111327858 A CN 111327858A CN 202010142390 A CN202010142390 A CN 202010142390A CN 111327858 A CN111327858 A CN 111327858A
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signal
signals
lvds
hdmi
dvi
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CN111327858B (en
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王素珍
马家麟
仁贵珊
王鹏
王伟
涨灏
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Qingdao University
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/76—Television signal recording
    • H04N5/765—Interface circuits between an apparatus for recording and another apparatus

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Abstract

The invention belongs to the technical field of video interface signal conversion, and discloses a method, a system and a device for converting LVDS video signals into HDMI signals. The invention provides a device and a method for converting LVDS/MINILLVDS video form signals with different resolutions, different color depths and different differential channels into HDMI interface signals.

Description

Method, system and device for converting LVDS (Low Voltage differential Signaling) video signal into HDMI (high-definition multimedia interface) signal
Technical Field
The invention belongs to the technical field of video interface signal conversion, and relates to a method, a system and a device for converting an LVDS video signal into an HDMI signal.
Background
At present, with the development of social science and technology, people have higher and higher requirements on video quality and form, video resolution is continuously improved, and the types of video interfaces are more and more. A High Definition Multimedia Interface (HDMI) is a digital video/audio Interface technology, and is a special digital Interface suitable for video transmission, which can simultaneously transmit audio and video signals without performing digital/analog or analog/digital conversion before signal transmission, and is a currently common video and audio Interface signal; therefore, during the playing process of video or audio, files in other interface forms are often converted into HDMI interface signal forms.
CN101753885A provides a television signal output device, which can send signals such as AV, TV, VGA, S-video, etc. to a video/audio dedicated processing chip, and then to an LVDS transmission terminal to output LVDS signals. The LVDS signals are sent to a special chip to be converted into HDMI interface signals. The method adopts a special chip to convert an LVDS signal into an HDMI signal, and cannot realize the conversion of various types of LVDS video interface signals into signals of an HDMI interface.
CN108259802A discloses an interface conversion circuit for converting LVDS signals into HDMI signals. The method applies an X86CPU processor on a CICS device of a complex instruction system computer, converts LVDS into an analog VGA signal through a programming and digital-to-analog converter, and converts the VGA into an interface signal of HDMI by adopting a special chip. The method uses a CPU programming method to realize the conversion of signals, and the signals which pass through the digital image signal to analog VGA in the intermediate process are converted into signals of HDMI interface by a special chip. The method adopts computer equipment CICS equipment with complex instructions, so that the miniaturization of the equipment is not utilized; meanwhile, the intermediate conversion process is subjected to analog-to-digital conversion processing, so that certain loss is caused to image signals.
In summary, the problems of the prior art are as follows:
(1) the existing device for converting the video LVDS interface signal into the signal of the HDMI interface adopts a special chip, and the conversion of the LVDS/MINILLVDS video interface signal into the signal of the HDMI interface in various forms cannot be realized.
(2) Meanwhile, the conventional conversion technology adopts computer equipment CICS equipment with complex instructions, and does not utilize the miniaturization of the equipment; meanwhile, the intermediate conversion process is subjected to analog-to-digital conversion processing, so that loss is caused to image signals.
The difficulty of solving the technical problems is as follows: converting the multi-form LVDS/MINILLVDS video interface signals into signals of the HDMI interface relates to processing the video LVDS/MINILDS interface signals with different resolutions, different color depths and different differential channels. For example, high definition resolutions typically include 1080 × 1920, 1366 × 768, 1280 × 720, and the like; standard definition resolution is typically 800 × 600, 480 × 320,640 × 480, etc.; the chroma depth is 6bit, 8bit, 10bit, 12bit, 16bit and the like, and the wider the color depth is, the richer the color is; the differential channel of the LVDS generally comprises a single-path 6-bit LVDS output interface, a double-path 6-bit LVDS output interface, a single-path 8-bit LVDS output interface, a double-path 8-bit LVDS output interface and the like; to convert the differential signals of different forms of video LVDS/MINILVDS interfaces into HDMI interface signals of standard multimedia streams, the use of a dedicated conversion chip is obviously not possible, because the dedicated conversion chip is designed for a specific form of interface signals. And meanwhile, the computer equipment CICS equipment with complex instructions is adopted, and the miniaturization of the equipment is not utilized.
The significance of solving the technical problems is as follows: the invention adopts a large-scale programmable chip FPGA with high integration level to realize the conversion of LVDS/MINIDLVDS video interface signals in various forms into HDMI interface signals, most circuits of the device are realized on one programmable FPGA chip, the FPGA has the capability of multi-path parallel signal processing, the conversion processing can be carried out on the input video LVDS interface signals with different resolutions, different chroma depths and different differential channels, and through programming, the FPGA chip can self-adaptively realize the conversion of the LVDS/MINIDLVDS video interface signals in different forms into the HDMI interface signals, thereby increasing the compatibility of the use of the display; the device is particularly suitable for being applied to a display system production line and used for manufacturers to test the quality of different types of video circuit mainboards; because different types of video circuit mainboards correspond to different types of LVDS/MINILLVDS video interface signals, a corresponding display screen is required to test the quality of the mainboards; by using the device, a production workshop can test the performances of different LVDS/MINILLVDS video main boards by using the same screen, so that the process of repeatedly replacing the display screen is omitted, the cost is saved, and the economic benefit of an enterprise is improved.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a method, a system and a device for converting an LVDS video signal into an HDMI signal.
The invention is realized in this way, a method for converting LVDS video signals into HDMI interface signals, the method for converting LVDS video signals into HDMI interface signals comprises:
firstly, selecting a path of LVDS/MINILLVDS video differential signal to be converted under the action of a multi-form LVDS video interface signal input selection module;
secondly, the selected LVDS/MINILLVDS video signals are sent to a module for converting LVDSLVDS/MINILDS interface signals into DVI-D signals, and differential signals of the LVDSLVDS/MINILDS interfaces are converted into parallel DVI-D image signals;
and thirdly, sending the parallel DVI-D image signals to a module for converting the DVI-D signals into HDMI signal, converting the parallel DVI-D image signals into serial low-voltage differential TMDS signals, sending the serial low-voltage differential TMDS signals to the HDMI, and displaying the image signals in the form of the HDMI.
Further, the method for converting the LVDS/MINILLVDS signal into the DVI-D signal comprises the following steps: the output signal of the video data selection module is input into the LVDS/MINILLVDS signal to DVI-D signal conversion module, the signal is sampled in the signal sampling module, the sampling frequency is calculated according to the resolution of the input signal and the number of differential channels, and the signal sampling is completed; sending the differential signal to a TTL signal generation module, and judging the sampled differential signal into a TTL level signal; sending the image signals to a serial-parallel conversion module, and converting serial TTL level image signals into parallel image signals; sending the image to a buffer unit, and sorting and storing the image under the control of a frame synchronization signal; and sending the signal to a DVI-D signal generation module to generate parallel RGB signals and image control signals to become signals of a DVI-D interface.
Further, the method for converting the LVDS/MINILLVDS signal into the DVI-D signal further comprises the following steps:
(1) the LVDS signal sampling is to sample the differential signal of each channel of the transmission line, convert the differential signal into a logic level signal which can be received by the FPGA chip, the logic level signal is corresponding to the image data and the control data of the video, condition the signal and send the signal to the extraction circuit of the subsequent line and field synchronous signal;
(2) extracting a video control signal, performing sequence detection on a plurality of logic level signals in the FPGA, and finding out line and field synchronizing signals for video control; under the control of the line and field synchronizing signals, the serial clock is in phase synchronization with the line and field synchronizing signals and is used for extracting pixel data of an image;
(3) generating an SDRAM address generator, and storing the signals subjected to the parallel processing of the FPGA into an SDRAM memory; under the action of synchronous clock signal, generating address generator for buffering multiple SDRAM ports and storing multiple signals in bit form; simultaneously, generating an address signal of the position of the RGB pixel point, and sending the address signal to a mapping module of an LVDS protocol;
(4) controlling and generating a mapping RGB address signal, reading out parallel LVDS data in the SDRAM, simultaneously analyzing an LVDS data form, and analyzing the LVDS data to an RGB data space according to the mapping relation between the LVDS data form and the RGB data form; and generating signals for mapping RGB addresses under the control of a system clock, and performing serial-parallel conversion on bit signals corresponding to RGB of each pixel point to generate parallel RGB signals.
Further, the DVI-D signal is converted into an HDMI interface signal, R, G, B with 8 bits are extracted one by one, divided into 3 paths of signals, and corresponding control signals are added; encoding 8-bit video data of 3 channels into a 10-bit DC balanced code; encoding 4-bit audio and auxiliary data on 3 TMDS links into continuous 10-bit direct current balance data and sending out the data; obtaining 3 paths of TMDS differential signals, and displaying image information on a display with an HDMI interface; and converting the RGB pixel points of the parallel DVI-D signal image and the control signal into TDMS signals.
Further, the method for converting the LVDS video signals into the HDMI interface signals extracts image information RGB and control HS/VS signals of images from the LVDS signals;
(1) acquiring data, namely generating a 74.25 × 7-519.75 MHZ sampling clock signal by a receiving end under the control of an LVDS differential clock frequency of 74.25MHZ, sampling the differential data, converting the differential data into a TTL signal, and sending the sampled single-ended signal to a serial-to-parallel processing module for processing;
(2) serial TTL data is converted into parallel processing, and SDR in SDR mode is setclkAt 74.25 × 7 ═ 519.75MHZ, the serial data was sampled with a 519.75MHZ clock and the parallel data was sent with a 74.25MHZ pixel clock, at each SDRclkRespectively sampling four paths of differential data on the rising edge of a clock, sampling a data signal of a pixel clock after 7 clocks, and extracting the data signal into parallel 28-bit TTL signals;
(3) extracting line and field synchronizing signals, wherein the parallelized 28-bit TTL signals comprise five signals of a shadow elimination signal DE, a line synchronizing signal HS, a field synchronizing signal VS, a pixel clock signal DCLK and a data RGB signal; wherein DE, HS, VS belong to the synchronizing signal, DCLK belongs to the clock signal, RGB belongs to the image data signal; the horizontal synchronizing signal HS selects an effective horizontal signal interval on the LVDS liquid crystal panel, the field synchronizing signal VS selects an effective field signal interval on the liquid crystal panel, and the HS and the VS are subjected to XOR logic operation to obtain a shadow eliminating signal DE in the video signal;
(4) the HDMI interface signal is output, and the FPGA is directly utilized to generate a signal for controlling and configuring the HDMI conversion chip;
(5) the HDMI circuit is initialized, and the HDMI circuit is already initialized successfully by the display having the HDMI interface being lit.
It is another object of the present invention to provide a program storage medium for receiving user input, the stored computer program causing an electronic device to perform the steps comprising:
firstly, selecting a path of multi-form LVDS/MINILLVDS video signals to be converted under the action of a multi-form LVDS video interface signal input selection module;
secondly, the selected LVDS/MINILLVDS video signal is sent to an LVDS/MINILDS signal to HDMI interface signal conversion module, and serial differential signals of the LVDS/MINILDS in a specific form are converted into parallel DVI-D image signals;
and thirdly, sending the parallel DVI-D image signals to a module for converting the DVI-D signals into HDMI signal, converting the parallel DVI-D image signals into serial low-voltage differential TMDS signals, sending the serial low-voltage differential TMDS signals to the HDMI, and displaying the image signals in the form of the HDMI.
Another objective of the present invention is to provide a system for converting LVDS video signal to HDMI interface signal, which implements the method for converting LVDS video signal to HDMI interface signal, the system comprising:
the multi-form LVDS/MINIDLVDS video signal input selection module is used for selecting a path of multi-form LVDS/MINIDLVDS video signal to be converted under the action of the multi-form LVDS interface signal input selection module; the selected LVDS/MINIDLVDS video signal is sent to the LVDS/MINIDLVDS signal to HDMI interface signal module;
the module for converting the LVDS/MINILLVDS video signals into DVI-D signals is used for converting serial differential signals of the specific LVDS/MINILDS into parallel DVI-D image signals;
the module for converting DVI-D signals into HDMI signals is used for transmitting the parallel DVI-D image signals to the module for converting DVI-D signals into HDMI signals, converting the parallel DVI-D image signals into serial low-voltage differential TMDS signals, transmitting the serial low-voltage differential TMDS signals to an HDMI, and displaying the image signals in the form of the HDMI;
the HDMI is used for transmitting the TMDS signal to the input signal end of the liquid crystal screen and displaying the image signal;
further, the LVDS/MINILLVDS to DVI-D signal module comprises: the device comprises a signal sampling module, a TTL signal generating module, a serial-parallel conversion module, an image control signal extraction and image data extraction, frame synchronization, a buffer unit and a DVI-D signal generating module;
the output signal of the video data selection module is input into the LVDS/MINILLVDS to DVI-D signal module, the signal is sampled, the sampling frequency is calculated according to the resolution of the input signal and the number of differential channels, and the signal sampling is completed; sending the signal to a TTL signal generating module;
the TTL signal generation module is used for judging the sampled differential signals into TTL level signals; sending to a serial-parallel conversion module;
the serial-parallel conversion module is used for converting the serial TTL level image signals into parallel image signals; sending to a buffer unit;
the buffer unit is used for sorting and storing the images under the control of the frame synchronization signal; sent to a DVI-D signal generating module,
and the DVI-D signal generation module is used for generating parallel RGB signals and control signals of images to become signals of a DVI-D interface.
Another objective of the present invention is to provide a device for converting LVDS video signals into HDMI interface signals, which carries the system for converting LVDS video signals into HDMI interface signals, wherein the device for converting LVDS video signals into HDMI interface signals comprises; the device comprises a multi-form LVDS/MINIDLVDS video signal input part, an LVDS/MINIDLVDS signal to DVI-D conversion module, an HDMI conversion chip and interface signal, a DVI-D interface signal module and a digital-to-analog conversion and VGA interface module;
the data signals of the image RGB output from the FPGA are connected with the data input D [35:4] of the SIL 9134; control signal clocks CLK, DE, HS and VS of the image are respectively connected with corresponding pins SIL 9134; the configuration signals CSCL, CSCD, RESET of SIL9134 are connected to FPGA configuration pins.
The invention also aims to provide a switching board device provided with the device for converting the LVDS video signal into the HDMI interface signal, which is used for testing the quality of the television mainboard with different types of LVDS/MINILLVDS signals.
In summary, the advantages and positive effects of the invention are: in the conversion process, the large-scale programmable FPGA device is adopted to realize the sampling and conversion of the LVDS/MINIDLVDS signals with different bit widths, different resolutions and different channels in various forms, and the signals are processed into the signals of a DVI-D interface. As the FPGA works by realizing corresponding functions through an internal hardware circuit, the FPGA has high flexibility and high conversion speed. The DVI-D signal is converted into HDMI signal via special chip, and the image signal is displayed on HDMI interface. Different liquid crystal screens correspond different resolutions, different chroma depths, different difference channels, so the form of the corresponding host video source is different, and different screens are required to be built according to different forms in production test to display signals, so that the production test period is prolonged, and the improvement of the production efficiency of enterprises is not utilized. The invention aims to provide a device for converting LVDS/MINI-LVDS differential signals in different video forms into HDM interface signals, which is beneficial to production and test of manufacturers and improves the economic benefit of the manufacturers. In the conversion process, a large-scale programmable FPGA device is adopted to realize sampling and conversion of LVDS/MINILLVDS signals with different bit widths, different resolutions and different channels in various forms, and digital signals are processed into signals of a DVI-D interface. The FPGA works by realizing corresponding functions through an internal hardware circuit, so that the flexibility is high and the conversion speed is high; meanwhile, the FPGA has the in-system programmable characteristic, so that the invention can carry out in-system programming adjustment according to the actually input signal, and further increases the compatibility of the system.
The invention comprises a multi-form LVDS/MINIDLVDS video interface signal input selection module, a multi-form LVDSLVDS/MINIDLVDS video interface signal to DVI-D signal conversion module, a DVI-D signal to HDMI interface signal conversion module and an HDMI interface module. The invention provides a device and a method for converting LVDS/MINILLVDS video interface signals with different resolutions, different color depths and different differential channels into HDMI interface signals, wherein the LVDS/MINILLVDS interface signals transmitted by a standard definition and high-definition video mainboard are converted into signals of an HDMI interface, and the HDMI signals are output to a screen for display; therefore, the method, the device and the system for converting the LVDS video signals into the HDMI interface signals are convenient for the majority of users of the display to carry out video conversion, and the compatibility of the display in use is improved; the device is particularly suitable for being applied to a display system production line and used for manufacturers to test the quality of different types of video circuit mainboards; because different types of video circuit mainboards correspond to different types of LVDS/MINILLVDS video interface signals, a corresponding display screen is required to test the quality of the mainboards; the device can be used for testing the performance of different video main boards by using the same screen in a production workshop, so that the process of repeatedly replacing the display screen is omitted, the cost is saved, and the economic benefit of an enterprise is improved.
Drawings
Fig. 1 is a flowchart of a method for converting LVDS video signals into HDMI signals according to an embodiment of the present invention.
FIG. 2 is a system diagram for converting LVDS video signals to HDMI signals according to an embodiment of the present invention;
in the figure: 1. a multi-form LVDS/MINILLVDS video signal input selection module; 2. a module for converting the LVDS/MINILLVDS video signals into DVI-D signals in various forms; 3. a module for converting DVI-D signal into HDMI signal; 4. HDMI interface module.
Fig. 3 is a block diagram of a system for converting LVDS/MINILVDS video signals into HDMI interface signals in various forms according to an embodiment of the present invention.
Fig. 4 is a schematic diagram of a hardware circuit of a system for converting LVDS/MINILVDS video signals into HDMI interface signals in various forms according to an embodiment of the present invention.
Fig. 5 is a schematic structural diagram of an implementation of converting various LVDS/MINILVDS video signals into HDMI interface signals according to an embodiment of the present invention.
Fig. 6 is a clock test diagram of various LVDS/mini LVDS video interface signals according to an embodiment of the invention.
Fig. 7 is a schematic diagram of signal data acquisition of the LVDS/MINILVDS video interface according to the embodiment of the present invention.
Fig. 8 is a schematic diagram of a parallelization process of LVDS/MINILVDS video interface signal data according to an embodiment of the present invention.
Fig. 9 is a diagram of a line sync signal HS for providing a DVI-D signal according to an embodiment of the present invention.
Fig. 10 is a diagram of a field sync signal VS for providing a DVI-D signal according to an embodiment of the present invention.
Fig. 11 is a diagram illustrating an effective strobe signal DE of a DVI-D signal according to an embodiment of the present invention.
Fig. 12 is a schematic diagram of a DVI-D signal conversion HDMI interface signal circuit according to an embodiment of the present invention.
Fig. 13 is a diagram of a system test result provided by the embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the following embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
In view of the problems in the prior art, the present invention provides a method, a system and a device for converting LVDS video signals to HDMI signals, which are described in detail below with reference to the accompanying drawings.
As shown in fig. 1, a method for converting an LVDS video signal into an HDMI signal according to an embodiment of the present invention includes the following steps:
s101: under the action of a plurality of video LVDS interface signal input selection modules, selecting a path of LVDS/MINILLVDS video signals of various forms to be converted;
s102: the selected LVDS/MINILLVDS video signal is sent to an LVDS/MINILDS interface signal to DVI-D signal conversion module, and serial differential signals of specific form LVDS/MINILDS are converted into parallel DVI-D image signals;
s103: the parallel DVI-D image signals are sent to a module for converting the DVI-D signals into HDMI interface signals, and the parallel DVI-D image signals are converted into serial low-voltage differential TMDS signals;
s104: sending the image signal to the HDMI interface to display the image signal in the form of HDMI interface.
As shown in fig. 2, a system for converting LVDS video signals into HDMI signals according to an embodiment of the present invention includes:
the device comprises a plurality of video LVDS/MINILLVDS interface signal input selection modules, a plurality of video LVDS/MINILDS interface signal to DVI-D signal conversion module, a DVI-D signal to HDMI interface signal conversion module and an HDMI interface module;
the multi-video LVDS/MINIDLVDS interface signal input selection module 1 is used for selecting a path of multi-video LVDS/MINIDLVDS interface signals to be converted under the action of the multi-video LVDS interface signal input selection module; the selected LVDS/MINIDLVDS video signal is sent to an LVDS/MINIDLVDS-HDMI interface signal module;
a module 2 for converting signals of the various video LVDS/MINILLVDS interfaces into DVI-D signals, which is used for converting serial differential signals of the LVDS/MINILDS interfaces in a specific form into parallel DVI-D image signals;
and the DVI-D signal to HDMI signal conversion module 3 is used for transmitting the parallel DVI-D image signals to the DVI-D signal to HDMI signal conversion module, converting the parallel DVI-D image signals into serial low-voltage differential TMDS signals, transmitting the serial low-voltage differential TMDS signals to the HDMI, and displaying the image signals in the form of the HDMI.
And the HDMI 4 is used for transmitting the TMDS signals to the input signal end of the liquid crystal display and displaying the image signals.
The technical solution of the present invention is further described below with reference to the accompanying drawings.
The structure block diagram of the invention is shown in fig. 3, and comprises a plurality of video LVDS/MINILVDS interface signal input selection modules, a plurality of video LVDS/MINILVDS interface signal to DVI-D signal conversion module, a DVI-D signal to HDMI interface signal conversion module, and an HDMI interface module. The video input selection module is used for selecting a path of various video LVDS/MINILLVDS interface signals to be converted under the action of the various video LVDS interface signal input selection module. The selected LVDS/MINILLVDS video signal is sent to a LVDS/MINILDS to DVI-D signal conversion module, and serial differential signals of the LVDS/MINILDS in a specific form are converted into parallel DVI-D image signals; the parallel DVI-D image signal is sent to a module for converting the DVI-D signal into an HDMI signal, the parallel DVI-D image signal is converted into a serial low-voltage differential TMDS signal and is sent to an HDMI, and the image signal in the form of the HDMI is displayed. The HDMI is used for transmitting the TMDS signal to the input signal end of the liquid crystal display and displaying the image signal.
The hardware circuit mechanism of the present invention is shown in fig. 4. Comprises a multi-form LVDS/MINILLVDS video signal input part; LVDS/MINILLVDS to DVI-D module (FPGA), HDMI conversion chip and interface signal. In the hardware system, the core device is an FPGA, and the operating frequency of the FPGA is required to meet the sampling requirement of the input differential video signal and the requirement of converting the differential signal into the TTL level. On the type selection of the chip, an Xilinx A7 series chip XC7A200T chip is adopted, the number of LogicCells in the chip is 215360, the size of Block RAM is 13140Kb, the running speed is in three grades of-1, -2 and-3, and the FMax interval is 464 MHz-628 MHz. The throughput of the data processing of the FPGA is larger than 1.48GB/s of data volume transmitted per second required by 2K @60fps video, so that the requirement on processing speed can be met. The HDMI conversion chip selects an SIL9134HDMI coding chip of a Silion Image company, supports 1080p @60HZ output at the highest level, and meets the current common standard definition and high definition display requirements. The control and configuration device of the HDMI conversion chip selects an ARM series STM32F407ZGT6 chip to complete the configuration of DVI-D digital signals input by the HDMI and the configuration of TMDS signals output by the HDMI.
According to the implementation scheme of the LVDS/MINIDLVDS to DVI-D signal module, the LVDS/MINIDLVDS to DVI-D signal module has the function of converting serial differential signals of various video LVDS/MINIDLVDS interfaces into parallel DVI-D image signals. The LVDS/MINIDLVDS to DVI-D signal module implementation is shown in the FPGA flag portion of FIG. 3.
The LVDS/MINILLVDS to DVI-D signal module comprises a signal sampling module, a TTL signal generating module, a serial-parallel conversion module, an image control signal extraction and image data extraction, frame synchronization, a buffer unit and a DVI-D signal generating module. The output signal of the video data selection module is input into the LVDS/MINILLVDS to DVI-D signal module, the signal is sampled firstly, the sampling frequency is calculated according to the resolution of the input signal and the number of differential channels, and the signal sampling is completed; sending the differential signal to a TTL signal generation module, and judging the sampled differential signal into a TTL level signal; sending the image signals to a serial-parallel conversion module, and converting serial TTL level image signals into parallel image signals; sending the image to a buffer unit, and sorting and storing the image under the control of a frame synchronization signal; and sending the signal to a DVI-D signal generation module to generate parallel RGB signals and image control signals to form DVI-D signals.
In the DVI-D signal to HDMI interface signal conversion module provided by the embodiment of the invention, the RGB pixel points of the parallel DVI-D signal Image and the control signal are converted into TDMS signals, and a special HDMI conversion chip SIL9134HDMI coding chip of Silion Image company is adopted, so that the display requirements of standard definition and high definition commonly used at present are met. And the conversion control and configuration of the HDMI conversion chip are realized by using an STM32F407ZGT6 chip of an ARM series.
The technical solution of the present invention is further described with reference to the following specific examples.
Example 1
The principle of extracting image information RGB and image control HS/VS signals from LVDS/MINILVDS signals to DVI-D signals according to the embodiment of the present invention is shown in fig. 5.
(1) LVDS data sampling circuit. The differential signals of each channel of the transmission line are sampled and converted into logic level signals which can be received by an FPGA chip, and the signals correspond to image data and control data of videos. The signal is conditioned and sent to the extraction circuit of the subsequent horizontal and vertical synchronizing signals.
(2) And a video control signal extraction circuit. And carrying out sequence detection on the multi-channel logic level signals in the FPGA to find out the line and field synchronizing signals controlled by the video. Under the control of the line and field synchronizing signals, the serial clock is synchronized with the phase of the line and field synchronizing signals to extract the pixel data of the image.
(3) An SDRAM address generator is generated. And storing the signals subjected to the parallel processing of the FPGA into an SDRAM memory. Under the action of synchronous clock signal, an address generator for buffering multiple SDRAM ports is generated to store multiple signals in form of bits. And simultaneously, generating an address signal of the position of the RGB pixel point, and sending the address signal to a mapping module of an LVDS protocol.
(4) Controlling and generating the mapped RGB address signals. Reading out the parallel LVDS/MINILLVDS data in the SDRAM, simultaneously analyzing the LVDS/MINILLVDS data form, and analyzing the LVDS/MINILDS data to the RGB data space according to the mapping relation between the LVDS/MINILDS data form and the RGB data form. And generating signals for mapping RGB addresses under the control of a system clock, and performing serial-parallel conversion on bit signals corresponding to RGB of each pixel point to generate parallel RGB signals.
The DVI-D signal to HDMI signal conversion module of the embodiment of the invention, TMDS (time MINIMIZedDifferencential Signal) minimizes transmission differential signals, realizes zero direct current offset of the signals in a channel through coding, has a peak value of 100-350mV, and is superior to LVDS signals in power consumption and anti-interference capability. The TMDS format includes video pixel data, control data, and data packets. The data packet contains audio data and auxiliary information data, and each TMDS channel contains 8-bit video data, 4-bit island data and 2-bit control data, and is transmitted by a time division multiplexing technique. By analyzing the form of TMDS signals, R, G, B with 8 bits are extracted one by one, divided into 3 paths of signals, and added with corresponding control signals; encoding 8-bit video data of 3 channels into a 10-bit DC balanced code; encoding 4-bit audio and auxiliary data on 3 TMDS links into continuous 10-bit direct current balance data and sending out the data; and finally obtaining 3 paths of TMDS differential signals, and displaying image information on a display with an HDMI interface. And converting the RGB pixel points of the parallel DVI-D signal image and the control signal into TDMS signals. A special HDMI conversion chip SIL9134HDMI coding chip of a Silion Image company is adopted, and the standard definition and high definition display requirements which are commonly used at present are met. And the conversion control and configuration of the HDMI conversion chip are realized by using an STM32F407ZGT6 chip of an ARM series.
Example 2
The embodiment of the invention extracts the image information RGB and the control information HS/VS signals, becomes a DVI-D signal analysis multi-form LVDS/MINILLVDS signal, has an explicit control clock signal in the differential data, and transmits one pixel information in one clock signal. The receiving end can extract image information and control information through the explicit clock signal. Differential signaling in LVDS is a common form of transmission signals in 50, 44, 42, 38, etc. inch screens, where the resolution is 1080p \1080i, 1366p \1366i, 720p, 1280p, etc. signals.
The process of extracting image data from the LVDS differential signals and extracting image information RGB and control HS/VS signals of the image from the LVDS signals is shown in the figure and comprises modules of data acquisition, serial-parallel conversion, synchronous extraction, data framing and the like. The signal sources of LVDS are 1080 × 1920 and 1366 × 768 resolutions, with specific parameters as shown in table 1.
TABLE 1 Signal Source parameters
Name of TFT-LCD Screen size (mm) Resolution ratio Clock MHz Kind of protocol Rate of transmission
Beijing east BOE 1366(H)x 768(V) 1366*768i 78 VISA、JEITA 250Mhz
Taiwan Chimei-1 580.8(H)x 328.8V) 1366*768p 80 VISA、JEITA 250Mhz
Korean LG-1 1286.0(H)x 745.0(V) 1920*1080 74.5 VISA、JEITA 300Mhz
Korean LG-2 983.0(H)x 576.0(V) 1920*1080 74.5 VISA、JEITA 300Mhz
One path of differential data signal observed by an agilent oscilloscope is shown in fig. 6. It can be seen from the figure that the pixel transmission frequency is 74.4MHZ and the maximum peak to peak value of the differential signal is 500 mv.
(1) Data acquisition
Fig. 7 is a schematic diagram of data acquisition. Under the control of LVDS differential clock frequency 74.25MHZ, a receiving end generates a sampling clock signal of 74.25 × 7 ═ 519.75MHz, samples differential data, converts the differential data into a TTL (Transistor-Transistor Logic) signal, and sends the sampled single-ended signal to a serial-to-parallel processing module for processing.
(2) Serial TTL data to parallel processing
The serial-parallel module is realized by adopting a primitive program inside the FPGA. The primitive of the FPGA can select two modes, one is DDR (double Data rate) mode, and one is SDR (single Data rate) mode, the DDR mode is that the rising edge and the falling edge of the clock respectively sample Data, and the SDR mode is that the rising edge of the clock samples.
In the practice of this invention. The present invention sets the SDR mode because the pixel clock is 74.25MHZ, and if the SDR mode is set, the present invention sets the SDR in the SDR modeclkAt 74.25 × 7 ═ 519.75MHZ, the serial data was sampled at 519.75MHZ, and then the parallel data was sent at 74.25MHZ pixel clock. The sampling and deserializing process is shown in FIG. 8, at each pointPersonal digital random access device (SDR)clkAnd respectively sampling four paths of differential data at the rising edge of the clock, sampling a data signal of one pixel clock after 7 clocks, and extracting the data signal into parallel 28-bit TTL signals.
(3) Extraction of horizontal and vertical synchronizing signals
As shown in fig. 8, the parallelized 28-bit TTL signals include five types of signals, such as a blanking signal DE, a horizontal synchronization signal HS, a field synchronization signal VS, a pixel clock signal DCLK, and a data RGB signal. Where DE, HS, VS belong to the synchronization signal, DCLK to the clock signal, and RGB to the image data signal.
The line synchronizing signal (HS) is used for selecting an effective line signal interval on the LVDS liquid crystal panel, the field synchronizing signal (VS) is used for selecting an effective field signal interval on the liquid crystal panel, and the HS and the VS are subjected to XOR logic operation to obtain a shadow eliminating signal DE in the video signal. As shown in fig. 9-11 are the extracted HS, VS, DE signals, respectively.
(4) HDMI interface signal output
In embodiment 2 of the present invention, signals for controlling and configuring the HDMI conversion chip are generated directly by using the FPGA. The implementation of a hardware chip HDMI output interface is adopted, an SIL9134HDMI coding chip of a Silion Image company is selected, and the highest 1080p @60HZ output is supported. Fig. 12 shows the connection relationship between the parallel image data signal output from the FPGA and the SIL9134HDMI encoding chip. The data signals of the image RGB output from the FPGA are connected with the data input D [35:4] of the SIL 9134; control signal clocks CLK, DE, HS and VS of the image are respectively connected with corresponding pins SIL 9134; the configuration signals CSCL, CSCD, RESET of SIL9134 are connected to FPGA configuration pins. The SIL9134 is initialized and controlled by programming of the FPGA.
The technical effects of the present invention will be described in detail with reference to the tests below.
Fig. 13 is an overall effect display diagram after the system test is successful. The oscilloscope in the figure shows one path of differential clock and one path of differential data. The image data on the notebook computer is sent to a certain television mainboard, and the differential data signal output by the television mainboard is sent to the FPGA circuit board. The differential data is extracted and processed by the FPGA large-scale programmable chip and is sent to an SIL9134HDMI coding chip, an image signal of an HDMI interface is output, and an image is sent to a display screen with an HMDI interface for display. As can be seen from the figure, the video signal outputted from the FPGA normally shows the signal of the HDMI interface.
The invention provides a device and a method for converting LVDS/MINILLVDS video signals with different resolutions, different color depths and different differential channels into HDMI interface signals, which can convert standard definition and high definition video differential signals into signals of an HDMI interface and output the HDMI signals to a screen for display, thereby providing a convenient method for testing a video circuit board by users and display manufacturers and improving the economic benefit of enterprises.
It should be noted that the embodiments of the present invention can be realized by hardware, software, or a combination of software and hardware. The kernel device of the hardware is an FPGA device, and an internal logic circuit of the FPGA is designed through a hardware programming language, so that a circuit for converting LVDS/MINILLVDS signals in various forms into HDMI interface signals is realized. The software portions may be stored in a memory and executed by a suitable instruction execution system, such as a microprocessor or specially designed hardware. Those skilled in the art will appreciate that the apparatus and methods described above may be implemented using computer executable instructions and/or embodied in processor control code, such code being provided on a carrier medium such as a disk, CD-or DVD-ROM, programmable memory such as read only memory (firmware), or a data carrier such as an optical or electronic signal carrier, for example. The apparatus and its modules of the present invention may be implemented by hardware circuits such as very large scale integrated circuits or gate arrays, semiconductors such as logic chips, transistors, or programmable hardware devices such as field programmable gate arrays, programmable logic devices, etc., or by software executed by various types of processors, or by a combination of hardware circuits and software, e.g., firmware.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.

Claims (10)

1. A method for converting LVDS video signals into HDMI signals is characterized by comprising the following steps:
firstly, selecting a path of LVDS/MINILLVDS video differential signal to be converted under the action of a multi-form LVDS video interface signal input selection module;
secondly, the selected LVDS/MINILLVDS video signals are sent to a module for converting LVDSLVDS/MINILDS interface signals into DVI-D signals, and differential signals of the LVDS/MINILDS interface signals are converted into parallel DVI-D image signals;
and thirdly, sending the parallel DVI-D image signals to a module for converting the DVI-D signals into HDMI signal, converting the parallel DVI-D image signals into serial low-voltage differential TMDS signals, sending the serial low-voltage differential TMDS signals to the HDMI, and displaying the image signals in the form of the HDMI.
2. The method of converting LVDS/MINIDLVDS signals to HDMI signals according to claim 1, wherein the method of converting LVDS/MINIDLVDS signals to DVI-D signals comprises: the output signal of the video data selection module is input into the LVDS/MINILLVDS signal to DVI-D signal conversion module, the signal is sampled in the signal sampling module, the sampling frequency is calculated according to the resolution of the input signal and the number of differential channels, and the signal sampling is completed; sending the differential signal to a TTL signal generation module, and judging the sampled differential signal into a TTL level signal; sending the image signals to a serial-parallel conversion module, and converting serial TTL level image signals into parallel image signals; sending the image to a buffer unit, and sorting and storing the image under the control of a frame synchronization signal; and sending the signal to a DVI-D signal generation module to generate parallel RGB signals and image control signals to become signals of a DVI-D interface.
3. The method for converting LVDS/MINIDLVDS signals into HDMI signals according to claim 2, wherein the method for converting LVDS/MINIDLVDS signals into DVI-D signals further comprises:
(1) the LVDS signal sampling is to sample the differential signal of each channel of the transmission line, convert the differential signal into a logic level signal which can be received by the FPGA chip, the logic level signal is corresponding to the image data and the control data of the video, condition the signal and send the signal to the extraction circuit of the subsequent line and field synchronous signal;
(2) extracting a video control signal, performing sequence detection on a plurality of logic level signals in the FPGA, and finding out line and field synchronizing signals for video control; under the control of the line and field synchronizing signals, the serial clock is in phase synchronization with the line and field synchronizing signals and is used for extracting pixel data of an image;
(3) generating an SDRAM address generator, and storing the signals subjected to the parallel processing of the FPGA into an SDRAM memory; under the action of synchronous clock signal, generating address generator for buffering multiple SDRAM ports and storing multiple signals in bit form; simultaneously, generating an address signal of the position of the RGB pixel point, and sending the address signal to a mapping module of an LVDS protocol;
(4) controlling and generating a mapping RGB address signal, reading out parallel LVDS data in the SDRAM, simultaneously analyzing an LVDS data form, and analyzing the LVDS data to an RGB data space according to the mapping relation between the LVDS data form and the RGB data form; and generating signals for mapping RGB addresses under the control of a system clock, and performing serial-parallel conversion on bit signals corresponding to RGB of each pixel point to generate parallel RGB signals.
4. The method according to claim 1, wherein the DVI-D signal to HDMI signal conversion method comprises extracting R, G, B with 8 bits each one by one, dividing into 3 channels of signals, and adding corresponding control signals; encoding 8-bit video data of 3 channels into a 10-bit DC balanced code; encoding 4-bit audio and auxiliary data on 3 TMDS links into continuous 10-bit direct current balance data and sending out the data; obtaining 3 paths of TMDS differential signals, and displaying image information on a display with an HDMI interface; and converting the RGB pixel points of the parallel DVI-D signal image and the control signal into TDMS signals.
5. The method according to claim 1, wherein the LVDS-to-HDMI interface signal method extracts image information RGB and control HS/VS signals of the image from the LVDS signals;
(1) acquiring data, namely generating a 74.25 × 7-519.75 MHZ sampling clock signal by a receiving end under the control of an LVDS differential clock frequency of 74.25MHZ, sampling the differential data, converting the differential data into a TTL signal, and sending the sampled single-ended signal to a serial-to-parallel processing module for processing;
(2) serial TTL data is converted into parallel processing, and SDR in SDR mode is setclkAt 74.25 × 7 ═ 519.75MHZ, the serial data was sampled with a 519.75MHZ clock and the parallel data was sent with a 74.25MHZ pixel clock, at each SDRclkRespectively sampling four paths of differential data on the rising edge of a clock, sampling a data signal of a pixel clock after 7 clocks, and extracting the data signal into parallel 28-bit TTL signals;
(3) extracting line and field synchronizing signals, wherein the parallelized 28-bit TTL signals comprise five signals of a shadow elimination signal DE, a line synchronizing signal HS, a field synchronizing signal VS, a pixel clock signal DCLK and a data RGB signal; wherein DE, HS, VS belong to the synchronizing signal, DCLK belongs to the clock signal, RGB belongs to the image data signal; the horizontal synchronizing signal HS selects an effective horizontal signal interval on the LVDS liquid crystal panel, the field synchronizing signal VS selects an effective field signal interval on the liquid crystal panel, and the HS and the VS are subjected to XOR logic operation to obtain a shadow eliminating signal DE in the video signal;
(4) the HDMI interface signal is output, and the FPGA is directly utilized to generate a signal for controlling and configuring the HDMI conversion chip;
(5) the HDMI circuit is initialized, and the HDMI circuit is already initialized successfully by the display having the HDMI interface being lit.
6. A program storage medium for receiving user input, the stored computer program causing an electronic device to perform the steps comprising:
firstly, selecting a path of multi-form LVDS/MINILLVDS video signals to be converted under the action of a multi-form LVDS video interface signal input selection module;
secondly, the selected LVDS/MINILLVDS video signal is sent to an LVDS/MINILDS signal to HDMI interface signal conversion module, and serial differential signals of the LVDS/MINILDS in a specific form are converted into parallel DVI-D image signals;
and thirdly, sending the parallel DVI-D image signals to a module for converting the DVI-D signals into HDMI signal, converting the parallel DVI-D image signals into serial low-voltage differential TMDS signals, sending the serial low-voltage differential TMDS signals to the HDMI, and displaying the image signals in the form of the HDMI.
7. An LVDS video signal to HDMI interface signal system for implementing the method of converting LVDS video signal to HDMI interface signal according to any one of claims 1 to 6, wherein the LVDS video signal to HDMI interface signal system comprises:
the multi-form LVDS/MINIDLVDS video signal input selection module is used for selecting a path of multi-form LVDS/MINIDLVDS video signal to be converted under the action of the multi-form LVDS interface signal input selection module; the selected LVDS/MINIDLVDS video signal is sent to the LVDS/MINIDLVDS signal to HDMI interface signal module;
the module for converting the LVDS/MINILLVDS video signals into DVI-D signals is used for converting serial differential signals of the specific LVDS/MINILDS into parallel DVI-D image signals;
the module for converting DVI-D signals into HDMI signals is used for transmitting the parallel DVI-D image signals to the module for converting DVI-D signals into HDMI signals, converting the parallel DVI-D image signals into serial low-voltage differential TMDS signals, transmitting the serial low-voltage differential TMDS signals to an HDMI, and displaying the image signals in the form of the HDMI;
and the HDMI is used for transmitting the TMDS signal to the input signal end of the liquid crystal display and displaying the image signal.
8. The LVDS video to HDMI interface signaling system of claim 7, further characterized in that said LVDS/MINILVDS to DVI-D signaling module comprises: the device comprises a signal sampling module, a TTL signal generating module, a serial-parallel conversion module, an image control signal extraction and image data extraction, frame synchronization, a buffer unit and a DVI-D signal generating module;
the output signal of the video data selection module is input into the LVDS/MINILLVDS to DVI-D signal module, the signal is sampled, the sampling frequency is calculated according to the resolution of the input signal and the number of differential channels, and the signal sampling is completed; sending the signal to a TTL signal generating module;
the TTL signal generation module is used for judging the sampled differential signals into TTL level signals; sending to a serial-parallel conversion module;
the serial-parallel conversion module is used for converting the serial TTL level image signals into parallel image signals; sending to a buffer unit;
the buffer unit is used for sorting and storing the images under the control of the frame synchronization signal; sent to a DVI-D signal generating module,
and the DVI-D signal generation module is used for generating parallel RGB signals and control signals of images to become signals of a DVI-D interface.
9. An LVDS video signal to HDMI interface signal conversion device carrying the LVDS video signal to HDMI interface signal conversion system of claim 7, wherein said LVDS video signal to HDMI interface signal conversion device comprises; the device comprises a multi-form LVDS/MINIDLVDS video signal input part, an LVDS/MINIDLVDS signal-to-DVI-D conversion module, an HDMI conversion chip and an interface signal module;
the data signals of the image RGB output from the FPGA are connected with the data input D [35:4] of the SIL 9134; control signal clocks CLK, DE, HS and VS of the image are respectively connected with corresponding pins SIL 9134; the configuration signals CSCL, CSCD, RESET of SIL9134 are connected to FPGA configuration pins.
10. An adapter board device installed with the device for converting LVDS video signals into HDMI signals according to claim 9, wherein the device is used for testing the quality of the television mainboard with different types of LVDS/MINIDLVDS signals.
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