CN111312815B - GaN-based power transistor structure and preparation method thereof - Google Patents
GaN-based power transistor structure and preparation method thereof Download PDFInfo
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Abstract
The invention discloses a GaN-based power transistor structure and a preparation method thereof, wherein the GaN-based power transistor structure comprises: the transistor comprises a source electrode structure, a laminated structure, a drain electrode structure and a grid electrode structure, wherein the source electrode structure is arranged at a first end of the laminated structure, and the drain electrode structure is arranged at a second end of the laminated structure relative to the source electrode structure; the grid structure is arranged on the laminated structure and is arranged between the first end and the second end; wherein, laminated structure includes: the lower barrier layer, the channel layer, the upper barrier layer and the passivation layer are sequentially laminated from bottom to top. The GaN-based power transistor structure stabilizes the reverse conduction voltage drop of the device at about 0V, so that the device has follow current capability under the condition that the forward conduction characteristic is not influenced, and the application of the GaN-based power transistor in a high-frequency power electronic system is promoted.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a GaN-based power transistor structure and a preparation method thereof.
Background
A High Electron Mobility Transistor (HEMT) is a field effect Transistor having a heterojunction structure. The GaN-based HEMT has excellent performances such as high switching speed, low parasitic, high output power and the like, and has great application potential in a high-frequency power electronic system. However, due to the lack of a body diode, the GaN-based HEMT does not have a freewheeling capability, has a large reverse conduction voltage drop when the device is in an off state, and the voltage drop is regulated by the gate-source voltage, so that the synchronous rectification of the power converter is influenced, extra power loss is generated, and the system efficiency is reduced.
Disclosure of Invention
Technical problem to be solved
The invention discloses a GaN-based power transistor structure and a preparation method thereof, aiming at solving the technical problems that in the prior art, a GaN-based HEMT does not have follow current capability and has larger reverse conduction voltage drop when a device is in an off state, so that the efficiency of a device system is influenced.
(II) technical scheme
One aspect of the present invention discloses a GaN-based power transistor structure, comprising: the source electrode structure is arranged at a first end of the laminated structure, and the drain electrode structure is arranged at a second end of the laminated structure relative to the source electrode structure; the grid structure is arranged on the laminated structure and is positioned between the first end and the second end; wherein, laminated structure includes: the lower barrier layer, the channel layer, the upper barrier layer and the passivation layer are sequentially laminated from bottom to top.
According to an embodiment of the present invention, the GaN-based power transistor structure further comprises: the substrate structure is arranged below the laminated structure; the base structure includes: the buffer layer is arranged below the lower barrier layer; the substrate layer is arranged below the buffer layer.
According to an embodiment of the present invention, the GaN-based power transistor structure further comprises: the 2DEG layer is formed in the channel layer and is formed below an interface of the channel layer and the upper barrier layer; and the 2DHG layer is formed in the channel layer and is formed above the interface of the lower barrier layer and the channel layer.
According to an embodiment of the invention, the source structure comprises: the source electrode hole is formed in the first end of the laminated structure, sequentially penetrates through the passivation layer, the upper barrier layer and the channel layer from top to bottom, and partially penetrates through the lower barrier layer; the lower source electrode is arranged at the lower end of the source electrode hole and corresponds to the upper part of the lower barrier layer and the lower part of the channel layer; and the upper source electrode is arranged at the upper end of the source electrode hole and corresponds to the upper part of the channel layer, the upper barrier layer and the passivation layer.
According to an embodiment of the present invention, an ohmic contact is formed between the upper source electrode and the 2DEG layer; and forming a Schottky contact between the lower source electrode and the 2DHG layer.
According to an embodiment of the present invention, a drain structure includes: the drain hole is formed in the second end of the laminated structure, sequentially penetrates through the passivation layer, the upper barrier layer and the channel layer from top to bottom, and partially penetrates through the lower barrier layer; the lower drain electrode is arranged at the lower end of the drain electrode hole and corresponds to the upper part of the lower barrier layer and the lower part of the channel layer; and the upper drain electrode is arranged at the upper end of the drain electrode hole and corresponds to the upper part of the channel layer, the upper barrier layer and the passivation layer.
According to the embodiment of the invention, an ohmic contact or a Schottky contact is formed between the upper drain electrode and the 2DEG layer; and ohmic contact is formed between the lower drain electrode and the 2DHG layer.
According to an embodiment of the present invention, a gate structure includes: the grid electrode hole is formed in the passivation layer of the laminated structure and is close to the source electrode structure, and the grid electrode hole penetrates through the passivation layer and partially penetrates through the upper barrier layer; and the grid electrode is arranged in the grid electrode hole and corresponds to the upper parts of the passivation layer and the upper barrier layer.
According to an embodiment of the present invention, the material of the source structure, the drain structure or the gate structure includes: one or more of Ti, al, ni, W, pt, pd, au or Ag.
According to an embodiment of the present invention, the material of the buffer layer comprises GaN; the materials of the lower barrier layer or the upper barrier layer include: one or more of AlN, alGaN, alInN, inGaN, or AlInGaN; the material of the channel layer includes: inGaN, wherein the Ga component is between 0 and 100%; the material of the passivation layer comprises: one or more combinations of silicon nitride, silicon dioxide, aluminum nitride, or GaN.
According to an embodiment of the invention, the thickness of the upper or lower barrier layer comprises: 1nm to 50nm, and the thickness of the channel layer is 10 to 500nm.
In another aspect of the present invention, a method for preparing the above GaN-based power transistor structure is disclosed, which comprises: forming a laminated structure; forming a source electrode structure and a drain electrode structure on the laminated structure; and forming a gate structure between the source structure and the drain structure on the stacked structure.
According to an embodiment of the present invention, forming a source structure and a drain structure on a stacked structure includes: forming a source electrode structure at the first end of the laminated structure, and forming a drain electrode structure at the second end of the laminated structure; or forming a drain structure at the second end of the laminated structure and forming a source structure at the first end of the laminated structure.
(III) advantageous effects
The invention discloses a GaN-based power transistor structure and a preparation method thereof, wherein the GaN-based power transistor structure comprises: the transistor comprises a source electrode structure, a laminated structure, a drain electrode structure and a grid electrode structure, wherein the source electrode structure is arranged at a first end of the laminated structure, and the drain electrode structure is arranged at a second end of the laminated structure relative to the source electrode structure; the grid structure is arranged on the laminated structure and is arranged between the first end and the second end; wherein, laminated structure includes: the lower barrier layer, the channel layer, the upper barrier layer and the passivation layer are sequentially laminated from bottom to top. The double heterojunction structure is formed by the upper Barrier layer, the lower Barrier layer and the channel layer between the upper Barrier layer and the lower Barrier layer, the double-channel GaN-based HEMT device structure of the 2DEG layer and the 2DHG layer is formed, the 2DEG layer is used as a forward conduction channel of a Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) structure in the device, the 2DHG layer is used as a reverse conduction channel from a source electrode to a drain electrode of a Schottky Diode (SBD) structure in the device, the reverse conduction voltage drop of the device is stabilized to about 0V, the device has follow current capability under the condition that the forward conduction characteristic of the device is not influenced, and the application of the GaN-based power Transistor in a high-frequency power electronic system is promoted.
Drawings
FIG. 1 is a schematic diagram of the composition of a GaN-based power transistor structure according to an embodiment of the invention;
FIG. 2 is a schematic circuit diagram of an equivalent circuit diagram of a GaN-based power transistor structure according to an embodiment of the invention;
FIG. 3 is a schematic diagram of the corresponding band principle of a GaN-based power transistor structure according to an embodiment of the invention;
fig. 4 is a schematic flow chart of a method for fabricating a GaN-based power transistor structure according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the following embodiments and the accompanying drawings.
The invention discloses a GaN-based power transistor structure and a preparation method thereof, aiming at solving the technical problems that in the prior art, a GaN-based HEMT does not have follow current capability and has larger reverse conduction voltage drop when a device is in an off state, so that the efficiency of a device system is influenced.
One aspect of the present invention discloses a GaN-based power transistor structure, as shown in fig. 1, comprising: source structure 310, stack structure 100, drain structure 320 and gate structure 330,
the source structure 310 is disposed at the first end of the stacked structure 100, and is used for providing a source for the GaN-based power transistor structure, and a position for extracting the source may be provided, so that the upper end thereof may partially protrude out of the stacked structure 100.
The drain structure 320 is disposed at a second end of the stacked structure 100 opposite to the source structure 310; the drain electrode is provided for the GaN-based power transistor structure, and a position for leading out the drain electrode is provided, so that the upper end thereof may partially protrude out of the stacked-layer structure 100.
The gate structure 330 is disposed on the stacked structure 100 and between the first terminal and the second terminal; the position for providing the grid electrode for the GaN-based power transistor structure can be provided, and the position for leading out the grid electrode can be provided, so that the upper end of the grid electrode can partially protrude out of the laminated structure 100.
In the embodiment of the present invention, as shown in fig. 1, with respect to the first terminal and the second terminal of the GaN-based power transistor structure, it is described in terms of the GaN-based power transistor structure as an independent structure, so that those skilled in the art can accurately understand the structure thereof. In practical situations, a plurality of GaN-based power transistor structures can be formed on one wafer substrate at the same time to form an array of the GaN-based power transistor structures, and an isolation layer can be arranged between adjacent GaN-based power transistor structures to avoid the contact of respective source electrodes or drain electrodes of the adjacent GaN-based power transistor structures to cause structural short circuit or other influences. For the GaN-based power transistor structure with an independent structure, the source structure 310 may be located at a first end of the GaN-based power transistor structure, and the drain structure 320 may be located at a second end of the GaN-based power transistor structure, or the positions may be reversed.
Wherein, the laminated structure 100 includes: a lower barrier layer 110, a channel layer 120, an upper barrier layer 130, and a passivation layer 140 stacked in this order from bottom to top. The stacked structure 100 is used as a functional layer of a GaN-based power transistor structure to realize a GaN-based HEMT device of the present invention. The channel layer 120, the upper barrier layer 130 and the passivation layer 140 are used to cooperate with the source structure 310 at the first end and the drain structure 320 at the second end to form a forward conducting MOSFET structure, and the lower barrier layer 110 is used to cooperate with the source structure 310 at the first end and the drain structure 320 at the second end to form a reverse conducting SBD structure, so that the MOSFET structure and the SBD structure are integrated in the GaN-based power transistor structure. The passivation layer 140 serves to space the outside and the stacked structure 100, maintain insulating properties between electrodes, prevent short circuits between the electrodes, and provide protection to the stacked structure 100.
According to an embodiment of the present invention, as shown in fig. 1, the GaN-based power transistor structure further includes: a base structure 200 disposed under the stacked structure 100; the base structure 200 includes: the buffer layer 220 and the substrate layer 210 are used to provide a substrate function for the stacked structure 100 to facilitate the formation of the GaN-based power transistor structure on the base structure 200. The buffer layer 220 is disposed below the lower barrier layer 110, and the buffer layer 220 may be made of a GaN material, which may have a good lattice match with the substrate layer 210, or with the lower barrier layer 110, so as to establish a more stable bonding effect between the lower barrier layer 110 and the substrate layer 210, and enhance the structural stability of the device. Substrate layer 210 is disposed below buffer layer 220 and is primarily used to provide a substrate function.
According to an embodiment of the present invention, as shown in fig. 1, the GaN-based power transistor structure further includes: the 2DEG layer and the 2DHG layer, i.e., the GaN-based power transistor structure of the present invention, form a 2DEG layer (two-dimensional electron gas layer) and a 2DHG layer (two-dimensional hole gas layer) through a double heterojunction structure implemented by the lower barrier layer 110 and the channel layer 120 and the upper barrier layer 130 and the channel layer 120.
The 2DEG layer is formed in the channel layer 120, and the 2DEG layer is formed below an interface between the channel layer 120 and the upper barrier layer 130, so that the 2DEG layer can be used as a forward conduction channel and form the MOSFET structure with the source electrode structure 310, the drain electrode structure 320, and the gate electrode structure 330.
The 2DHG layer is formed in the channel layer 120, and the 2DHG layer is formed above the interface between the lower barrier layer 110 and the channel layer 120, so that the 2DEG layer can be used as a reverse conduction channel to form the SBD structure with the source electrode structure 310 and the drain electrode structure 320.
Therefore, the GaN-based power transistor structure of the invention realizes high integration of a MOSFET structure and an SBD structure, and simultaneously forms a double-channel structure of the GaN-based power transistor structure through the 2DEG layer formed in the channel layer 120 and the 2DHG layer formed in the channel layer 120, so that when the GaN-based power transistor structure is in an off state, the reverse conduction voltage drop of the device is stabilized to about 0V, the device has stable follow current capability without affecting the forward conduction characteristic, and simultaneously, the original forward conduction performances of the device, such as threshold voltage, forward conduction resistance, saturation current and the like, and the dynamic performances, such as switching speed and the like, are maintained, in addition, no extra wafer area is occupied for high integration of the MOSFET structure and the SBD structure, the size of an integrated circuit is effectively reduced, and the application of the GaN-based power transistor in a high-frequency power electronic system is promoted.
According to an embodiment of the present invention, as shown in fig. 1, the source structure 310 includes: a source hole, a lower source 311 and an upper source 312, wherein the source hole is opened at the first end of the stacked structure 100, and the source hole sequentially penetrates through the passivation layer 140, the upper barrier layer 130 and the channel layer 120 from top to bottom and partially penetrates through the lower barrier layer 110; the source hole is mainly used for providing a receiving space for the lower source 311 and the upper source 312.
A lower source 311 is disposed at a lower end of the source hole, the lower source 311 being disposed corresponding to an upper portion of the lower barrier layer 110 and a lower portion of the channel layer 120; an end surface of a lower end of the lower source electrode 311 contacts a bottom surface of the source hole, and at least one side surface of the lower source electrode 311 contacts an end surface of an upper portion of the lower barrier layer 110 corresponding to the first end and an end surface of a lower portion of the channel layer 120 corresponding to the first end to cooperate with the lower drain electrode 321 of the drain structure 320, thereby forming a 2DHG layer in the channel layer 120 above an interface of the lower barrier layer 110 and the channel layer 120.
An upper source 312 is disposed at an upper end of the source hole, the upper source 312 being disposed corresponding to an upper portion of the channel layer 120, the upper barrier layer 130, and the passivation layer 140; an end surface of a lower end of the upper source electrode 312 contacts an end surface of an upper end of the lower source electrode 311, at least one side surface of the upper source electrode 312 contacts an end surface of an upper portion of the channel layer 120 corresponding to the first end, an end surface of the upper barrier layer 130 corresponding to the first end, and an end surface of the passivation layer 140 corresponding to the first end to cooperate with the upper drain electrode 322 of the drain structure 320, and a 2DEG layer is formed in the channel layer 120 below an interface of the channel layer 120 and the upper barrier layer 130.
According to an embodiment of the present invention, as shown in fig. 1, the drain structure 320 includes: a drain hole, a lower drain 321 and an upper drain 322, wherein the drain hole is opened at the second end of the stacked structure 100, and the drain hole sequentially penetrates through the passivation layer 140, the upper barrier layer 130 and the channel layer 120 from top to bottom, and partially penetrates through the lower barrier layer 110; the drain hole is mainly used for providing a receiving space for the lower drain 321 and the upper drain 322.
The lower drain 321 is disposed at the lower end of the drain hole, and the lower drain 321 is disposed corresponding to the upper portion of the lower barrier layer 110 and the lower portion of the channel layer 120; an end surface of a lower end of the lower drain 321 contacts a bottom surface of the drain hole, and at least one side surface of the lower drain 321 contacts an end surface of an upper portion of the lower barrier layer 110 corresponding to the first end and an end surface of a lower portion of the channel layer 120 corresponding to the first end to cooperate with the lower source 311 of the source structure 310, so that a 2DHG layer is formed in the channel layer 120 above an interface of the lower barrier layer 110 and the channel layer 120.
An upper drain electrode 322 is disposed at an upper end of the drain hole, the upper drain electrode 322 being disposed corresponding to an upper portion of the channel layer 120, the upper barrier layer 130, and the passivation layer 140; an end surface of a lower end of the upper drain electrode 322 contacts an end surface of an upper end of the lower drain electrode 321, at least one side surface of the upper drain electrode 322 contacts an end surface of an upper portion of the channel layer 120 corresponding to the first end, an end surface of the upper barrier layer 130 corresponding to the first end, and an end surface of the passivation layer 140 corresponding to the first end, so as to match the upper source electrode 312 of the source electrode structure 310, and form a 2DEG layer in the channel layer 120 below an interface of the channel layer 120 and the upper barrier layer 130.
Based on the above-mentioned GaN-based power transistor structure, as shown in fig. 1, the channel layer 120, the upper barrier layer 130 are configured to form a MOSFET structure in a forward direction with the upper source 312 at the first end, the upper drain 322 at the second end, and the gate structure 330, and the lower barrier layer 110 is configured to form an SBD structure in a reverse direction with the lower source 311 at the first end, the lower drain 321 at the second end, and the channel layer 120, so as to integrate the MOSFET structure and the SBD structure in the GaN-based power transistor structure. As shown in fig. 2, the GaN-based power transistor structure of the present invention may be a HEMT device structure, in which the drain D of the HEMT structure is connected to the cathode (lower drain 321) of the SBD structure, and the source S of the HEMT structure is connected to the anode (lower source 311) of the SBD structure. When the grid-source voltage of the HEMT structure is greater than the threshold voltage, if the drain-source voltage is greater than 0V, the HEMT structure is in a conducting state, and the SBD structure is in reverse bias and is cut off; if the drain-source voltage is less than 0V and the drain-source voltage is slightly higher than the threshold voltage of the SBD structure, the HEMT structure can not be conducted reversely, and the SBD structure is in a conducting state, so that the equivalent circuit has follow current capability.
According to the embodiment of the present invention, as shown in fig. 1, a schottky contact is formed between the lower source electrode 311 and the 2DHG layer, and an ohmic contact is formed between the lower drain electrode 321 and the 2DHG layer, so that the GaN-based power transistor structure of the present invention may form an SBD structure having the 2DHG layer through the lower source electrode 311, the lower drain electrode 321, the channel layer 120, and the lower barrier layer 110, and the 2DHG layer may be used as a reverse conduction channel of the GaN-based power transistor structure of the present invention, and provides a freewheeling capability for an equivalent circuit when the device is in an off state. As shown in fig. 3, the lower barrier layer 110 disposed on the buffer layer 220 serves to raise the energy band of the device structure in cooperation with the channel layer 120, and a hole gas is generated in the channel layer 120 at the interface between the lower barrier layer 110 and the channel layer 120, forming a 2DHG layer.
According to an embodiment of the present invention, as shown in fig. 1, an ohmic contact is formed between the upper source electrode 312 and the 2DEG layer, and an ohmic contact or a schottky contact is formed between the upper drain electrode 322 and the 2DEG layer; the GaN-based power transistor structure of the present invention may form a MOSFET structure having a 2DEG layer through the upper source 312, the upper drain 322, the channel layer 120, and the upper barrier layer 130, and the 2DEG layer may be used as a forward conduction channel of the GaN-based power transistor structure of the present invention. As shown in fig. 3, the upper barrier layer 130 disposed on the channel layer 120 serves to pull down an energy band of the device structure in cooperation with the channel layer 120, and electron gas is generated in the channel layer 120 under an interface between the upper barrier layer 130 and the channel layer 120, forming a 2DEG layer. Therefore, with the double heterostructure of lower barrier layer 110/channel layer 120/upper barrier layer 130 of the present invention, polarization properties are used to enable the band to create a 2DEG layer and a 2DHG layer at the upper and lower heterointerfaces, respectively.
According to an embodiment of the present invention, as shown in fig. 1, the gate structure 330 includes: gate hole and gate, gate structure 330 is used to provide gate G of the GaN-based power transistor structure of the present invention, as shown in fig. 2. The gate hole is opened on the passivation layer 140 of the stacked structure 110, the gate hole is disposed close to the source structure 310, and the gate hole penetrates through the passivation layer 140 and partially penetrates through the upper barrier layer 130 to provide a space for accommodating the gate; and a gate electrode is disposed at the gate hole, and the gate hole is disposed corresponding to the passivation layer 140 and the upper portion of the upper barrier layer 130. The end surface and the side surface of the lower end of the gate electrode are in contact with the upper barrier layer 130, a part of the peripheral side surface of the gate electrode is in contact with the passivation layer 140, and the upper end of the gate electrode may protrude out of the passivation layer 140 by a certain distance. So as to lead out the gate G of the device. Similarly, the upper ends of the upper source electrode 312 and the upper drain electrode 322 may also protrude a certain distance above the passivation layer 140 so that the device can lead out the source electrode S and the drain electrode D, as shown in fig. 1. In addition, the gate hole is disposed close to the source structure 310, so that the gate-source voltage Vgs applied through the gate can achieve the turn-on of the MOSFET structure, so that the threshold voltage of the device is more stable.
In addition, the gate electrode may perform a depletion function on the corresponding 2DEG (two-dimensional electron gas) on the channel layer 120, so that the 2DEG layer at the corresponding position disappears to form a normally-off device structure. The MOSFET structure achieves forward conduction when a certain gate-source voltage Vgs is applied. Therefore, the GaN-based power transistor structure can be simultaneously suitable for an enhancement mode/depletion mode GaN-based MIS/MES-HEMT device and is integrated with the reverse parallel Schottky diode.
According to an embodiment of the present invention, the material of the source structure 310, the drain structure 320, or the gate structure 330 includes: one or more of Ti, al, ni, W, pt, pd, au or Ag. Since the source structure 310 includes: a lower source 311 and an upper source 312, and a drain structure 320 comprising: a lower drain 321 and an upper drain 322, and a gate structure 330 including: therefore, the material choices of the lower source 311, the upper source 312, the lower drain 321, the upper drain 322 and the gate include: one or more of Ti, al, ni, W, pt, pd, au or Ag. In addition, in order to form an ohmic contact between the upper source electrode 312 and the 2DEG layer, an ohmic contact or a schottky contact is formed between the upper drain electrode 322 and the 2DEG layer to form a MOSFET structure having the 2DEG layer; and forming schottky contact between the lower source electrode 311 and the 2DHG layer, forming ohmic contact between the lower drain electrode 321 and the 2DHG layer to form an SBD structure with a 2DHG layer, wherein the material selection of the lower source electrode 311, the upper source electrode 312, the lower drain electrode 321, the upper drain electrode 322 and the gate electrode can be different, for example, the material of the lower source electrode 311 can be Ti, the material of the upper source electrode 312 can be Al, the material of the lower drain electrode 321 can be Ni, and the material of the upper drain electrode 322 can be Pt, specifically for the integration purpose of forming an SBD structure with a 2DHG layer and a MOSFET structure with a 2DEG layer.
According to an embodiment of the present invention, as shown in fig. 1, the material of the buffer layer 220 includes GaN; the materials of lower barrier layer 110 or upper barrier layer 130 include: one or more of AlN, alGaN, alInN, inGaN, or AlInGaN; the material of the channel layer 120 includes: inGaN, wherein in the InGaN material of the channel layer 120, the Ga component is between 0 and 100%; the material of the passivation layer 140 includes: one or more combinations of silicon nitride, silicon dioxide, aluminum nitride, or GaN. The GaN-based material has a good direct band gap and excellent electron saturation mobility, so that the GaN-based power transistor structure has high-frequency, high-temperature and high-power performances, and on the other hand, the GaN-based material achieves a good forbidden bandwidth and is strong in chemical stability, so that the device structure can have good working stability, the breakdown voltage of the GaN-based material is higher, the device can work under higher voltage, the polarization performance is not good, the conduction band of the heterojunction structure of the GaN-based material is discontinuous, and the current capacity is stronger. It should be understood by those skilled in the art that the references to GaN, alN, alGaN, alInN, inGaN, alInGaN, etc. in the present invention are only a symbolic representation of the corresponding material and are not limitations on the corresponding component ratios of the material.
According to an embodiment of the invention, as shown in fig. 1, the thickness of upper barrier layer 130 or lower barrier layer 110 includes: 1nm to 50nm, and particularly, the thickness of the upper barrier layer 130 can be 1nm to 10nm, so that the device can be used as an enhancement device to realize a better depletion function of the 2DEG layer. While at other thicknesses the device may be a depletion mode device. Therefore, the GaN-based power transistor structure can be a depletion mode HEMT structure or an enhancement mode HEMT structure, and simultaneously realizes integration with the anti-parallel SBD structure. The thickness of the channel layer is 10-500nm.
Another aspect of the present invention discloses a method for preparing the above-mentioned GaN-based power transistor structure, as shown in fig. 4, including:
s410, forming a laminated structure;
s420, forming a source electrode structure and a drain electrode structure on the laminated structure;
and S430, forming a gate structure between the source structure and the drain structure on the laminated structure.
The GaN-based power transistor structure is analyzed in detail, and the passivation layer in the stacked structure can be formed by using a metal organic compound chemical vapor deposition method, a low pressure chemical vapor deposition method, a plasma enhanced chemical vapor deposition method, or an atomic layer deposition method. The invention discloses a preparation method of a GaN-based power transistor structure, which has a processing technology compatible with that of a traditional GaN-based HEMT device structure and is simultaneously suitable for integration of an enhanced/depletion type GaN-based MIS/MES-HEMT device and a reverse parallel Schottky diode.
According to an embodiment of the present invention, forming a source structure and a drain structure on a stacked structure includes: forming a source electrode structure at the first end of the laminated structure, and forming a drain electrode structure at the second end of the laminated structure; or forming a drain structure at the second end of the laminated structure and forming a source structure at the first end of the laminated structure. Specifically, the source hole of the source structure and the drain hole of the drain structure may be formed simultaneously, but for the formation sequence of the upper source and the lower source of the source structure and the upper drain and the lower drain of the drain structure, for the source structure, the lower source may be formed first, and then the upper source may be formed.
The above-mentioned embodiments are intended to illustrate the objects, technical solutions and advantages of the present invention in further detail, and it should be understood that the above-mentioned embodiments are only exemplary embodiments of the present invention, and are not intended to limit the present invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (9)
1. A GaN-based power transistor structure, comprising:
the laminated structure comprises a lower barrier layer, a channel layer, an upper barrier layer and a passivation layer which are sequentially laminated from bottom to top;
a source structure disposed at a first end of the stack structure,
the drain electrode structure is arranged at the second end of the laminated structure relative to the source electrode structure;
a gate structure disposed on the stack structure and between the first end and the second end;
the 2DEG layer is formed in the channel layer and below an interface of the channel layer and the upper barrier layer, and the 2DEG layer is used as a forward conduction channel and forms an MOSFET structure with a source electrode structure, a drain electrode structure and a grid electrode structure; and
the 2DHG layer is formed in the channel layer and above the interface of the lower barrier layer and the channel layer, and the 2DHG layer is used as a reverse conduction channel to form an SBD structure with the source electrode structure and the drain electrode structure;
the high integration of the MOSFET structure and the SBD structure is realized, and meanwhile, the double-channel structure of the GaN-based power transistor structure is formed by the 2DEG layer formed in the channel layer and the 2DHG layer formed in the channel layer, so that the reverse conduction voltage drop of the device tends to be stable at 0V when the GaN-based power transistor structure is in an off state.
2. The GaN-based power transistor structure of claim 1, further comprising: a base structure disposed below the stack structure, the base structure comprising:
a buffer layer disposed below the lower barrier layer; and
and the substrate layer is arranged below the buffer layer.
3. The GaN-based power transistor structure of claim 1, wherein the source structure comprises:
the source electrode hole is formed at the first end of the laminated structure, sequentially penetrates through the passivation layer, the upper barrier layer and the channel layer from top to bottom, and partially penetrates through the lower barrier layer;
the lower source electrode is arranged at the lower end of the source electrode hole and corresponds to the upper part of the lower barrier layer and the lower part of the channel layer; and
the upper source electrode is arranged at the upper end of the source electrode hole and corresponds to the upper part of the channel layer, the upper barrier layer and the passivation layer;
an ohmic contact is formed between the upper source electrode and the 2DEG layer; and
and a Schottky contact is formed between the lower source electrode and the 2DHG layer.
4. The GaN-based power transistor structure of claim 1, wherein the drain structure comprises:
the drain hole is formed in the second end of the laminated structure, sequentially penetrates through the passivation layer, the upper barrier layer and the channel layer from top to bottom, and partially penetrates through the lower barrier layer;
the lower drain electrode is arranged at the lower end of the drain electrode hole and corresponds to the upper part of the lower barrier layer and the lower part of the channel layer; and
the upper drain electrode is arranged at the upper end of the drain electrode hole and corresponds to the upper part of the channel layer, the upper barrier layer and the passivation layer;
an ohmic contact or a Schottky contact is formed between the upper drain electrode and the 2DEG layer; and
and ohmic contact is formed between the lower drain electrode and the 2DHG layer.
5. The GaN-based power transistor structure of claim 1, wherein the gate structure comprises:
the grid electrode hole is arranged on the passivation layer of the laminated structure and close to the source electrode structure, penetrates through the passivation layer and partially penetrates through the upper barrier layer; and
and the grid electrode is arranged in the grid electrode hole and corresponds to the upper parts of the passivation layer and the upper barrier layer.
6. The GaN-based power transistor structure of claim 1,
the source structure, the drain structure or the gate structure comprises: one or more of Ti, al, ni, W, pt, pd, au or Ag.
7. The GaN-based power transistor structure of claim 2,
the material of the buffer layer comprises GaN;
the material of the lower barrier layer or the upper barrier layer comprises: one or more of AlN, alGaN, alInN, inGaN, or AlInGaN;
the material of the channel layer includes: inGaN, wherein the Ga component is between 0 and 100%;
the material of the passivation layer comprises: one or more combinations of silicon nitride, silicon dioxide, aluminum nitride, or GaN;
the thicknesses of the upper or lower barrier layers include: 1nm to 50nm, and
the thickness of the channel layer is 10-500nm.
8. A method of fabricating a GaN-based power transistor structure as claimed in any of claims 1-7, comprising:
forming a laminated structure;
forming a source electrode structure and a drain electrode structure on the laminated structure; and
forming a gate structure between the source structure and the drain structure on the stacked structure.
9. The method of claim 8, wherein forming a source structure and a drain structure on the stacked structure comprises:
forming a source electrode structure at a first end of the laminated structure, and forming a drain electrode structure at a second end of the laminated structure; or
And forming a drain structure at the second end of the laminated structure, and forming a source structure at the first end of the laminated structure.
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