CN113611742B - GaN power device integrated with Schottky tube - Google Patents
GaN power device integrated with Schottky tube Download PDFInfo
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- CN113611742B CN113611742B CN202110907784.6A CN202110907784A CN113611742B CN 113611742 B CN113611742 B CN 113611742B CN 202110907784 A CN202110907784 A CN 202110907784A CN 113611742 B CN113611742 B CN 113611742B
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- 230000004888 barrier function Effects 0.000 claims abstract description 30
- 239000011148 porous material Substances 0.000 claims abstract description 14
- 239000004065 semiconductor Substances 0.000 claims abstract description 6
- 239000004020 conductor Substances 0.000 claims description 40
- 239000003989 dielectric material Substances 0.000 claims description 18
- 238000002161 passivation Methods 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 2
- 230000005684 electric field Effects 0.000 abstract description 4
- 230000000903 blocking effect Effects 0.000 abstract description 2
- 230000005533 two-dimensional electron gas Effects 0.000 abstract description 2
- 238000011084 recovery Methods 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7788—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
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- Electrodes Of Semiconductors (AREA)
Abstract
The invention belongs to the technical field of power semiconductors, and relates to a GaN power device integrated with a Schottky tube. When the integrated Schottky tube is in a forward conduction state, the integrated Schottky tube is in an off state; during reverse follow current, the integrated Schottky tube is conducted, has low conduction voltage drop and quick reverse recovery characteristics, and reduces the area of the device; the two-dimensional electron gas under the grid is exhausted by the P-type GaN grid, and the enhanced vertical device is realized by combining the P-type highly doped GaN blocking layer with pores; the P-type high-doped GaN barrier layer modulates electric field distribution, so that high withstand voltage is realized; the tri-gate structure can provide stronger gate control capability and improve the switching speed of the device.
Description
Technical Field
The invention belongs to the technical field of power semiconductors, and particularly relates to a GaN power device integrated with a Schottky tube.
Background
Because GaN materials have superior characteristics of wide band gap, high electron saturation velocity, high electron mobility, high critical breakdown field, etc., gaN devices can operate efficiently at high temperature, high voltage, and high frequency. Compared to lateral GaN HEMT (High-electron-mobility transistor) devices, the electric field peak of the vertical GaN device is far from the device surface, the breakdown voltage is mainly dependent on the thickness of the drift layer, and the sensitivity to traps and surface states is lower, so that the vertical GaN device is more suitable for High power applications.
In many power switching applications it is desirable for the device to have low loss reverse conduction capability to provide a freewheel path for an inductive load. The large power loss can be caused by large conduction voltage drop of the vertical GaN device body diode, and low-loss reverse conduction is generally realized by adopting a power transistor and a freewheeling diode in reverse parallel connection. But this approach not only increases cost and chip area, but also introduces additional parasitic inductance and capacitance.
Disclosure of Invention
In view of the above problems, the present invention provides a GaN power device integrated with a schottky diode.
The technical scheme of the invention is as follows:
a GaN power device integrating a Schottky tube comprises a first conductive material 1, an N-type highly doped GaN layer 2, a GaN buffer layer 3, a barrier layer 4 and a passivation layer 5 which are sequentially stacked from bottom to top along the vertical direction of the device; the P-type highly doped GaN barrier layer 7 with pores is inserted into the GaN buffer layer 3, and the intermittent P-type highly doped GaN barrier layer 7 is symmetrically distributed along the transverse direction of the device; the center of the device comprises a grid structure and a Schottky anode groove structure along the transverse direction of the device, the grid structure and the Schottky anode groove structure are arranged in parallel along the longitudinal direction of the device, the second conductive materials 6 are symmetrically distributed on two sides of the device, and a space is reserved between the second conductive materials 6 and the two structures;
the longitudinal direction is a third dimension direction perpendicular to the transverse direction and the vertical direction;
the drain electrode is led out from the lower surface of the first conductive material 1;
the second conductive material 6 penetrates through the passivation layer 5 from top to bottom and is in contact with the barrier layer 4, the contact type is ohmic contact, and a source electrode is led out of the upper surface of the second conductive material 6;
the method is characterized in that:
the Schottky anode groove structure consists of a dielectric material 8 and a third conductive material 9, penetrates through the passivation layer 5 and the barrier layer 4 in sequence from top to bottom, is in contact with the GaN buffer layer 3, is positioned right above the pore of the P-type highly doped GaN barrier layer 7, and has a groove width larger than the pore width of the P-type highly doped GaN barrier layer 7; the dielectric material 8 is positioned at the bottom and the side wall of the groove; the third conductive material 9 is inlaid in the dielectric material 8 at the bottom of the groove, the bottom of the third conductive material is contacted with the GaN buffer layer 3, the contact type is Schottky contact, and the anode of the Schottky diode is led out from the upper surface of the third conductive material 9 and is in short circuit with the source electrode;
the gate structure comprises a P-type GaN layer 10, a dielectric material 12 and a fourth conductive material 11, wherein the P-type GaN layer 10 penetrates through the passivation layer 5 and contacts the barrier layer 4, and the dielectric material 12 covers the top of the P-type GaN layer 10 and the front and rear side walls of the semiconductor along the longitudinal direction; the fourth conductive material 11 is covered on the dielectric material 12;
the upper surface of the fourth conductive material 11 is led out of the gate.
The invention has the beneficial effects that the reverse freewheeling is realized by integrating the Schottky diode in the longitudinal direction, compared with the external reverse parallel freewheeling diode, the area is saved and the parasitic parameter is reduced; the P-type highly doped GaN barrier layer assists in exhausting the drift region, so that electric field distribution is optimized, and the withstand voltage of the device is further improved; the P-type highly doped GaN barrier layer with the pores enables two-dimensional electron gas (2 DEG) to only pass through the pores to form vertical current, and the enhanced vertical device is realized by combining the P-type GaN grid with the 2DEG under the depletion gate; the tri-gate structure can provide stronger gate control capability and improve the switching speed of the device.
Drawings
Fig. 1 is a schematic structural view of embodiment 1;
FIG. 2 is a cross-sectional view taken along AA' of example 1;
FIG. 3 is a cross-sectional view taken along BB' of example 1;
FIG. 4 is a cross-sectional view of example 1 taken along CC';
Detailed Description
The technical scheme of the invention is described in detail below with reference to the accompanying drawings and examples:
example 1
As shown in fig. 1, the semiconductor device comprises a first conductive material 1, an N-type highly doped GaN layer 2, a GaN buffer layer 3, a barrier layer 4 and a passivation layer 5 which are sequentially stacked from bottom to top along the vertical direction of the device; the P-type highly doped GaN barrier layer 7 with pores is inserted into the GaN buffer layer 3, and the intermittent P-type highly doped GaN barrier layer 7 is symmetrically distributed along the transverse direction of the device; the center of the device comprises a grid structure and a Schottky anode groove structure along the transverse direction of the device, the grid structure and the Schottky anode groove structure are arranged in parallel along the longitudinal direction of the device, the second conductive materials 6 are symmetrically distributed on two sides of the device, and a space is reserved between the second conductive materials 6 and the two structures;
the longitudinal direction is a third dimension direction perpendicular to the transverse direction and the vertical direction;
the drain electrode is led out from the lower surface of the first conductive material 1;
the second conductive material 6 penetrates through the passivation layer 5 from top to bottom and is in contact with the barrier layer 4, the contact type is ohmic contact, and a source electrode is led out of the upper surface of the second conductive material 6;
the method is characterized in that:
the Schottky anode groove structure consists of a dielectric material 8 and a third conductive material 9, penetrates through the passivation layer 5 and the barrier layer 4 in sequence from top to bottom, is in contact with the GaN buffer layer 3, is positioned right above the pore of the P-type highly doped GaN barrier layer 7, and has a groove width larger than the pore width of the P-type highly doped GaN barrier layer 7; the dielectric material 8 is positioned at the bottom and the side wall of the groove; the third conductive material 9 is inlaid in the dielectric material 8 at the bottom of the groove, the bottom of the third conductive material is contacted with the GaN buffer layer 3, the contact type is Schottky contact, and the anode of the Schottky diode is led out from the upper surface of the third conductive material 9 and is in short circuit with the source electrode;
the gate structure comprises a P-type GaN layer 10, a dielectric material 12 and a fourth conductive material 11, wherein the P-type GaN layer 10 penetrates through the passivation layer 5 and contacts the barrier layer 4, and the dielectric material 12 covers the top of the P-type GaN layer 10 and the front and rear side walls of the semiconductor along the longitudinal direction; the fourth conductive material 11 is covered on the dielectric material 12;
the upper surface of the fourth conductive material 11 is led out of the gate.
The working principle of this example is: when the grid is blocked in the forward direction, a low potential is applied to the grid, the P-type GaN depletes a 2DEG channel below the grid, and a current path above a pore of the P-type highly doped GaN blocking layer is blocked, so that the device is turned off, and enhancement type is realized; the P-type highly doped GaN barrier layer assists in exhausting the drift region, so that electric field distribution is optimized, and withstand voltage is improved; and when the grid is conducted in the forward direction, the potential is increased to recover the 2DEG under the grid, and electrons start from the source electrode to pass through the channel 2DEG at the heterojunction, then enter the GaN buffer layer and the N-type highly doped GaN layer through the pores between the P-type highly doped GaN barrier layers, and finally reach the drain electrode. The anode of the Schottky diode is in short circuit with the source electrode of the transistor device, the source electrode is added with low potential when in forward conduction, the drain electrode is added with high potential, and the diode is in an off state; during reverse freewheeling, the source electrode is increased in potential, the drain electrode is increased in potential, current flows in from the anode of the Schottky diode, passes through the GaN buffer layer and the N-type high-doped GaN layer and flows out from the drain electrode.
Claims (2)
1. A GaN power device integrating a Schottky tube comprises a first conductive material (1), an N-type highly doped GaN layer (2), a GaN buffer layer (3), a barrier layer (4) and a passivation layer (5) which are sequentially stacked from bottom to top along the vertical direction of the device; a P-type highly doped GaN barrier layer (7) with pores is inserted into the GaN buffer layer (3), namely the P-type highly doped GaN barrier layer (7) is discontinuously and symmetrically distributed along the transverse direction of the device; the device comprises a grid structure and a Schottky anode groove structure in the middle along the transverse direction of the device, wherein the grid structure and the Schottky anode groove structure are arranged in parallel along the longitudinal direction of the device, second conductive materials (6) are symmetrically distributed on two sides of the device, and a space is reserved between the second conductive materials (6) and the grid structure and between the second conductive materials and the Schottky anode groove structure;
defining the longitudinal direction as a third dimension direction perpendicular to the transverse direction and the vertical direction;
the drain electrode is led out from the lower surface of the first conductive material (1);
the second conductive material (6) penetrates through the passivation layer (5) from top to bottom and is in contact with the barrier layer (4), the contact type is ohmic contact, and a source electrode is led out of the upper surface of the second conductive material (6);
the method is characterized in that:
the Schottky anode groove structure consists of a dielectric material (8) and a third conductive material (9), sequentially penetrates through the passivation layer (5) and the barrier layer (4) from top to bottom, is in contact with the GaN buffer layer (3), is positioned right above the pore of the P-type highly-doped GaN barrier layer (7), and has a groove width larger than the pore width of the P-type highly-doped GaN barrier layer (7); the dielectric material (8) is positioned at the bottom and the side wall of the groove; the third conductive material (9) is inlaid in the dielectric material (8) at the bottom of the groove, the bottom of the third conductive material is contacted with the GaN buffer layer (3), the contact type is Schottky contact, and the anode of the Schottky diode is led out from the upper surface of the third conductive material (9) and is in short circuit with the source electrode;
the grid structure comprises a P-type GaN layer (10), a dielectric material (12) and a fourth conductive material (11), wherein the P-type GaN layer (10) penetrates through the passivation layer (5) and is in contact with the barrier layer (4), and the dielectric material (12) covers the top of the P-type GaN layer (10) and front and rear side walls of the semiconductor along the longitudinal direction; the fourth conductive material (11) is covered on the dielectric material (12);
and a grid electrode is led out from the upper surface of the fourth conductive material (11).
2. An enhanced GaN vertical electron transistor integrated with a schottky tube according to claim 1, characterized in that the barrier layer (4) is made of one or a combination of several materials AlN, alGaN, inGaN, inAlN.
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| CN202110907784.6A CN113611742B (en) | 2021-08-09 | 2021-08-09 | GaN power device integrated with Schottky tube |
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| CN202110907784.6A CN113611742B (en) | 2021-08-09 | 2021-08-09 | GaN power device integrated with Schottky tube |
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| CN113611742B true CN113611742B (en) | 2023-04-25 |
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| CN114447101B (en) * | 2022-01-24 | 2023-04-25 | 电子科技大学 | Vertical GaN MOSFET integrated with freewheeling channel diode |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105118830A (en) * | 2015-08-03 | 2015-12-02 | 电子科技大学 | Enhanced HEMT of integrated SBD |
| CN107482059A (en) * | 2017-08-02 | 2017-12-15 | 电子科技大学 | A kind of GaN hetero-junctions longitudinal direction is inverse to lead FET |
| CN111312815A (en) * | 2020-02-28 | 2020-06-19 | 中国科学院微电子研究所 | GaN-based power transistor structure and preparation method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110047910B (en) * | 2019-03-27 | 2020-07-31 | 东南大学 | Heterojunction semiconductor device with high voltage endurance capability |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105118830A (en) * | 2015-08-03 | 2015-12-02 | 电子科技大学 | Enhanced HEMT of integrated SBD |
| CN107482059A (en) * | 2017-08-02 | 2017-12-15 | 电子科技大学 | A kind of GaN hetero-junctions longitudinal direction is inverse to lead FET |
| CN111312815A (en) * | 2020-02-28 | 2020-06-19 | 中国科学院微电子研究所 | GaN-based power transistor structure and preparation method thereof |
Non-Patent Citations (3)
| Title |
|---|
| Li Zhang，et. al..p -GaN Gate Power Transistor With Distributed Built-in Schottky Barrier Diode for Low-loss Reverse Conduction. IEEE Electron Device Letters .2020,全文. * |
| Ruopu Zhu， et. al..A split gate vertical GaN power transistor with intrinsic reverse conduction capability and low gate charge. IEEE Transactions on Electron Devices .2018,全文. * |
| Tao Sun，et. al..Vertical GaN Power Transistor with Embedded Fin-shaped Diode for High Performance Power Conversion.2020 IEEE 15th International Conference on Solid-State & Integrated Circuit Technology (ICSICT).2020,全文. * |
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