CN111312809B - Power device and manufacturing method thereof - Google Patents

Power device and manufacturing method thereof Download PDF

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CN111312809B
CN111312809B CN202010409858.9A CN202010409858A CN111312809B CN 111312809 B CN111312809 B CN 111312809B CN 202010409858 A CN202010409858 A CN 202010409858A CN 111312809 B CN111312809 B CN 111312809B
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layer
field plate
dielectric layer
interlayer dielectric
doped region
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CN111312809A (en
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王东
丛茂杰
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing Electronics Shaoxing Corp SMEC
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SMIC Manufacturing Shaoxing Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
    • H01L29/66333—Vertical insulated gate bipolar transistors
    • H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66666—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
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Abstract

The invention provides a power device and a manufacturing method thereof, wherein the power device comprises a substrate, an insulating medium layer formed on the substrate and a floating field plate embedded in the insulating medium layer, the substrate is provided with at least one groove, a gate structure is formed in the groove, a body region is formed in the substrate at the periphery of the groove, a doped region with the conductivity type opposite to that of the body region is formed in the surface layer of the body region, and the floating field plate at least covers part of a boundary interface between the groove and the doped region and is insulated and isolated from the doped region and the gate structure.

Description

Power device and manufacturing method thereof
Technical Field
The invention relates to the technical field of integrated circuit manufacturing, in particular to a power device and a manufacturing method thereof.
Background
A Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) is an important component of a medium-low voltage synchronous rectification power supply because of the advantages of a simple driving circuit, low driving power, high switching speed, high working frequency and the like. At present, most of medium and low voltage MOSFETs use a trench MOSFET structure, and compared with a planar MOSFET, the trench MOSFET structure has smaller on-resistance (Rdson) in unit area under the same withstand voltage (BV). The trench MOSFET structure is shown in fig. 1, and includes a substrate 100, an epitaxial layer 101 formed on the substrate 100, a gate oxide layer 102 formed on the inner wall of a trench of the epitaxial layer 101, a gate 103 filled in the trench of the epitaxial layer 101, a body region 104 formed between adjacent trenches of the epitaxial layer 101, a source region 105 formed in the epitaxial layer 101 above the body region 104, an insulating dielectric layer 106 formed on the surface of the epitaxial layer 101, an adhesive layer 107 formed on the inner wall of a contact hole in the insulating dielectric layer 106, a tungsten plug 108 filled in the contact hole, and an external metal layer 109 formed on the surface of the insulating dielectric layer 106, wherein the external metal layer 109 is electrically connected with the source region 105 through the tungsten plug 108.
The electric field strength of the trench MOSFET is very high at three locations, namely the bottom of the trench (i.e., the bottom of the gate 103), the junction of the body region 104 and the epitaxial layer 101, and the surface of the source region 105, according to the device characteristics and process characteristics. The electric field distribution is optimized through the process, the electric field intensity can be reduced, and the withstand voltage (BV) of the device is further improved. The electric field distribution at the bottom of the trench is usually optimized by making the trench bottom more rounded, the electric field distribution at the junction of the body region 104 and the epitaxial layer 101 is usually optimized by making a shallow junction, and the electric field distribution at the surface of the source region 105 is usually optimized by reducing the tip electric field accumulation effect through the process of rounding the sharp corners at the top of the trench.
However, the above scheme for optimizing the electric field distribution still cannot meet the requirement of further improving the withstand voltage of the device.
In addition, the above-described problem also occurs in a power device such as an IGBT (Insulated Gate Bipolar Transistor) having a trench Gate.
Disclosure of Invention
The invention aims to provide a power device and a manufacturing method thereof, which are used for optimizing the electric field distribution on the surface of a doped region on the periphery of the top of a grid groove so as to improve the withstand voltage of the device.
To solve the above technical problem, the present invention provides a power device, including:
the semiconductor device comprises a substrate and a plurality of semiconductor chips, wherein the substrate is provided with at least one groove, a gate structure is formed in the groove, a body region is formed in the substrate on the periphery of the top of the groove, a doped region is formed in the surface layer of the body region, and the conductivity type of the doped region is opposite to that of the body region;
an insulating dielectric layer formed on the substrate;
and the floating field plate is embedded in the insulating medium layer, at least covers part of boundary interfaces between the groove and the doped region, and is isolated from the gate structure and the doped region through the insulating medium layer.
Optionally, the floating field plate covers the whole surface of the trench; and/or the floating field plate covers the whole doped region.
Optionally, the material of the floating field plate comprises at least one of a doped semiconductor, a metal silicide and a metal.
Optionally, the bottom of the trench and/or the top of the trench is rounded.
Optionally, the gate structure has an upper gate and a lower gate, the lower gate is filled in the lower part of the trench, the upper gate is filled in the upper part of the trench, and the upper gate and the lower gate are isolated and insulated by a gate isolation layer.
Optionally, the power device further includes:
the conductive plug penetrates through the insulating medium layer and the doped region, and the bottom of the conductive plug extends into the body region with partial thickness below the doped region so as to be electrically connected with the doped region and the body region;
and the external metal layer is formed on the insulating medium layer and is electrically connected with the conductive plug.
The invention also provides a manufacturing method of the power device, which comprises the following steps:
providing a substrate, wherein the substrate is provided with at least one groove, a gate structure is formed in the groove, a body region is formed in the substrate on the periphery of the top of the groove, a doped region is formed in the surface layer of the body region, and the conductivity type of the doped region is opposite to that of the body region;
covering a first interlayer dielectric layer on the substrate, wherein the doped region and the groove are both buried in the first interlayer dielectric layer;
forming a floating field plate exposing a part of the surface of the first interlayer dielectric layer, wherein the floating field plate at least covers a part of a boundary interface between the groove and the doped region;
and covering a second interlayer dielectric layer on the first interlayer dielectric layer and the floating field plate.
Optionally, the first interlayer dielectric layer is made of silicon dioxide or silicon nitride, and the second interlayer dielectric layer is made of at least one of silicon oxynitride, borosilicate glass, phosphosilicate glass, fluorosilicone glass, borophosphosilicate glass, and borophosphosilicate-fluorosilicone glass.
Optionally, the step of forming the floating field plate comprises: depositing a field plate layer on the first interlayer dielectric layer, and photoetching and etching the field plate layer to form the floating field plate;
or, the step of forming the floating field plate includes: etching the first interlayer dielectric layer with partial thickness to form a shallow opening, filling a field plate layer in the shallow opening, and flattening the top surface of the field plate layer to the top surface of the first interlayer dielectric layer to form the floating field plate;
or, the step of forming the floating field plate includes: and forming a patterned photoresist layer on the first interlayer dielectric layer, depositing a field plate layer on the photoresist layer, and stripping the photoresist layer and the redundant field plate layer above the photoresist layer to form the floating field plate.
Optionally, after the first interlayer dielectric layer and the floating field plate are covered with the second interlayer dielectric layer, the method further includes:
etching the second interlayer dielectric layer, the first interlayer dielectric layer, the doped region and the body region with partial thickness to form a contact hole;
and filling a conductive plug in the contact hole and forming an external metal layer on the second interlayer dielectric layer, wherein the conductive plug is electrically connected with the doped region and the body region, and the external metal layer is electrically connected with the conductive plug.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
the floating field plate is additionally arranged in the insulating medium layer above the doped region on the periphery of the top of the groove (namely the grid groove), at least covers part of a boundary interface between the groove and the doped region, and is at least insulated and isolated from the doped region and the grid structure, so that the accumulation effect of a tip electric field on the top of the groove can be reduced through the floating field plate, the electric field distribution of the doped region is optimized, and the purpose of improving the withstand voltage of a device is achieved.
Drawings
Fig. 1 is a schematic cross-sectional view of a prior art trench MOSFET device;
fig. 2 to 4 are schematic cross-sectional views of power devices according to embodiments of the present invention;
FIG. 5 is a flow chart of a method of fabricating a power device in accordance with an embodiment of the present invention;
fig. 6 to 10 are schematic cross-sectional views of devices in a method for manufacturing a power device according to an embodiment of the invention;
fig. 11 to 14 are schematic cross-sectional views of devices in a method for manufacturing a power device according to another embodiment of the present invention;
fig. 15 to 18 are schematic device cross-sectional structures in a method for manufacturing a power device according to still another embodiment of the present invention.
Detailed Description
The technical solution proposed by the present invention will be further described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Referring to fig. 2, an embodiment of the invention provides a power device, which includes a substrate, an insulating dielectric layer 206, a conductive plug 208, an external metal layer 209, and a floating field plate 210.
The substrate comprises a base 200 and an epitaxial layer 201, wherein a gate structure, a body region 204 and a doped region 205 are formed in the epitaxial layer 201. The substrate may be any suitable semiconductor material known to those skilled in the art, such as silicon, germanium, silicon germanium, or the like, the epitaxial layer 201 is a semiconductor layer formed on the substrate 200, and has a thickness greater than that of the substrate 200, and the conductivity types of the epitaxial layer 201 and the substrate 200 are the same, such as both N-type semiconductor layers. At least one trench (i.e., a gate trench, not labeled in the figures) is formed in the epitaxial layer 201, and the depth of the trench is less than the thickness of the epitaxial layer 201. The gate structure is filled in the trench, the gate structure includes a gate dielectric layer 202 covering the inner wall of the trench and a gate 203 filled in the trench, the gate dielectric layer 202 is made of silicon dioxide, the gate 203 is made of polysilicon, and the top of the gate 203 may be flush with the top of the epitaxial layer or slightly lower than the top of the epitaxial layer 201. Body region 204 is formed in epitaxial layer 201 at the periphery of the trench with the bottom of body region 204 shallower than the bottom of the trench and body region 204 has a conductivity type opposite to that of the epitaxial layer, e.g., when the conductivity type of the epitaxial layer is N-type, the conductivity type of body region 204 is P-type. Doped region 205 is formed in a surface layer of body region 204, and a conductivity type of doped region 205 is opposite to a conductivity type of body region 204, for example, when the conductivity type of body region 204 is P-type, the conductivity type of doped region 205 is N-type. The depth of body region 204 is sufficiently deep to provide a space for forming doped region 205, so as to ensure the performance of doped region 205, and is sufficiently shallow to form a shallow junction at the junction of body region 204 and epitaxial layer 201, so as to optimize the electric field distribution at the junction of body region 204 and epitaxial layer 201, and improve the withstand voltage of the power device. In addition, the boundary between the doped region 205 and the body region 204 is lower than the top of the gate 203, so that the doped region 205 and the gate 203 are overlapped, and the effectiveness of a channel of a power device is ensured. When the power device is a MOSFET, the doped region 205 is a source region of the MOSFET, and when the power device is an IGBT, the doped region 205 is an emitter region of the IGBT.
In this embodiment, a plurality of trenches are formed in the epitaxial layer 201, the gate structures in the trenches are the same, and the body region 204 and the doped region 205 therein are formed between some adjacent trenches. In addition, the bottom and the top corner of each groove are rounded, and the bottom of each groove is more round relative to the top of the groove, so that the electric field accumulation effect of the top end of the bottom of the channel and the electric field accumulation effect of the top end of the groove are avoided, the electric field distribution of the bottom of the groove and the electric field distribution of the top of the groove are further optimized, and the voltage resistance of the device is further improved.
An insulating dielectric layer 206 is formed on the epitaxial layer 201 and buries both the doped region 205 and the gate structure. The material of the insulating dielectric layer 206 includes at least one of silicon dioxide, silicon nitride, and a low-K dielectric having a dielectric constant K lower than that of silicon dioxide. The insulating dielectric layer 206 may be a single-layer structure or a stacked structure, for example, a silicon dioxide layer formed by a plasma enhanced vapor deposition process is disposed below the floating field plate 210, and a borophosphosilicate glass layer is disposed around the sidewall of the floating field plate 210 and covers the floating field plate 210. In addition, the top surface of the insulating dielectric layer 206 is flat, which can provide a flat process surface for the formation of the external metal layer 209. A contact hole (not labeled in fig. 2) is formed in insulating dielectric layer 206 and sequentially penetrates insulating dielectric layer 206 and doped region 205 and extends into a portion of the thickness of body region 204 below doped region 205 to expose a portion of the surface of body region 204.
The conductive plug 208 is filled in the contact hole of the insulating dielectric layer 206 and electrically connected to the doped region 205 and the body region 204, thereby shorting the parasitic transistor formed by the doped region 205, the body region 204 and the bottom epitaxial layer 201, and avoiding device latch-up (or reducing the probability of occurrence of possible latch-up). The material of the conductive plug 208 includes at least one of tungsten, copper, cobalt, nickel, and the like. In this embodiment, a conductive adhesive layer 207 is further sandwiched between the conductive plug 208 and the inner wall of the contact hole to enhance the adhesion between the conductive plug 208 and the insulating dielectric layer 206, and ensure the electrical connection reliability between the conductive plug 208 and the body region 204 and the doped region 205. The material of the adhesion layer 207 may include titanium and/or tantalum.
The floating field plate 210 is buried in the insulating dielectric layer 206 and covers at least a portion of the interface between the trench and the doped region 205, and the material of the floating field plate 210 is a conductive material, the conductive material includes at least one of a doped semiconductor, a metal silicide and a metal and other non-metal-containing conductive materials, the doped semiconductor includes, for example, N-doped or P-doped polysilicon, N-doped or P-doped single crystal silicon, N-doped or P-doped germanium, polysilicon doped with nitrogen or oxygen, the metal silicide includes cobalt silicide, titanium silicide, nickel silicide, tungsten silicide, copper silicide, etc., and the metal includes at least one of tungsten, copper, cobalt, aluminum, gold, platinum, nickel, etc. The floating field plate 210 is also insulated and isolated from the conductive plug 208, the gate 203, and the doped region 205 by the insulating dielectric layer 206, respectively. Preferably, the material of the floating field plate 210 does not contain metal, so as to prevent metal from diffusing in the insulating dielectric layer 206, thereby ensuring the insulating property of the insulating dielectric layer 206, and preventing short circuit and leakage between the floating field plate 210 and the conductive plug 208, the gate 203 and the doped region 205, respectively.
In addition, the trench is usually a stripe trench having a length extending in one direction, as an example, the shape of the floating field plates 210 in a plan view may be a stripe extending in the length direction of the trench, the floating field plates 210 on both sides of the conductive plug 208 are independent and parallel to each other, and may be composed of a plurality of discontinuous field plates uniformly or non-uniformly arranged in the length direction of the trench, and the shape, size, and pitch of each field plate may be completely the same or not completely the same, or may be a continuous field plate continuously extending to the boundary of the device region in the length direction of the trench. As another example, two adjacent trenches may share the same floating field plate 210, i.e., floating field plate 210 extends along the length of the trench and floating field plate 210 has a width sufficient to cover the region between two adjacent trenches, and is hollowed out at conductive plug 208, which is equivalent to conductive plug 208 penetrating floating field plate 210, and floating field plate 210 covers the entire doped region 205.
It should be noted that the floating height of floating field plate 210 relative to doped region 205 (i.e., the vertical distance between the bottom surface of floating field plate 210 and the top surface of doped region 205) and the degree of overlap between floating field plate 210 and the trench and doped region 205 all affect the optimization of the electric field distribution at doped region 205. Therefore, when the floating field plate 210 is disposed, it can be reasonably adjusted according to specific device withstand voltage requirements, and it can even fully cover the top of the trench where the surrounding gate structure is located, and also fully cover the top of the doped region 205, which is not particularly limited in the present invention. As an example, when the thickness of the insulating dielectric layer 206 is 5000 Å -10000 Å, the floating height of the floating field plate 210 may be 1/6-2/3 of the thickness of the insulating dielectric layer 206, and when the width of the trench in which the gate structure is located is 0.1 μm-3 μm, the floating field plate 210 may cover the top of the trench entirely or partially.
An external metal layer 209 is formed on the insulating dielectric layer 206 and electrically connected to the conductive plug 208. The external metal layer 209 functions to electrically connect the doped region 205 with other external electrical structures through the conductive plug 208. The material of the external metal layer 209 may be the same as or different from the material of the conductive plug 208.
It should be noted that, in the above embodiment, the substrate has the base 200 and the epitaxial layer 201, and the depth of each trench is the same as the above, but the technical solution of the present invention is not limited thereto, and in other embodiments of the present invention, the substrate may be a silicon-on-insulator or a bulk silicon structure, and the depth of at least one trench in all the trenches is different from the depth of the other trenches.
In addition, it should be noted that, although the gate structures in the trenches are the same and only have one gate in the above embodiments, the technical solution of the present invention is not limited thereto.
Referring to fig. 3, in some other embodiments of the present invention, the gate structure in the trench includes an upper gate 203b and a lower gate 203a separated from each other, the lower gate 203a is filled in a lower portion of the trench, the upper gate 203b is filled in an upper portion of the trench, and the upper gate 203b and the lower gate 203a are isolated from each other by a gate isolation layer 202 c. Upper gate 203b is also insulated from body region 204 by a gate dielectric layer 202b overlying the sidewalls of the upper portion of the trench, and lower gate 203a is also insulated from body region 204 and epitaxial layer 201 by a gate dielectric layer 202a overlying the inner walls of the lower portion of the trench. The material of the lower gate 203a may be the same as or different from the material of the upper gate 203 a. The gate dielectric layer 202b and the gate dielectric layer 202a may be made of the same material or different materials. For example, the upper gate 203b is a metal gate, the gate dielectric layer 202b is a high-K dielectric having a dielectric constant K higher than that of silicon dioxide, the lower gate 203a is a polysilicon gate, and the gate dielectric layer 202a is silicon dioxide. The gate isolation layer 202c may be formed together with the gate dielectric layer 202b or may be formed separately, and when the gate isolation layer 202c may be formed separately from the gate dielectric layer 202b, the gate isolation layer 202c may be thicker than the gate dielectric layer 202 b. In addition, the lower gate 203a can be electrically connected to the doped region 205, grounded or independently suspended, thereby serving as another field plate to optimize the electric field at the bottom of the trench, and further improving the voltage resistance of the device.
Referring to fig. 4, in still other embodiments of the present invention, at least two trenches are formed in the epitaxial layer 201, and the gate structure in at least one of the trenches is different from the gate structure in the other trenches. Specifically, epitaxial layer 201 has two adjacent trenches with doped region 205 and body region 204 formed in epitaxial layer 201 between the two adjacent trenches. The gate structure in one of the trenches has only one gate 203c, the gate 203c is insulated and isolated from the doped region 205, the body region 204 and the epitaxial layer 201 by a gate dielectric layer 202d covering the inner wall of the trench, the gate structure in the other trench comprises an upper gate 203b and a lower gate 203a which are separated from each other up and down, the lower gate 203a is filled in the lower part of the trench, the upper gate 203b is filled in the upper part of the trench, and the upper gate 203b and the lower gate 203a are insulated and isolated by a gate isolation layer 202 c. Upper gate 203b is also insulated from body region 204 by a gate dielectric layer 202b overlying the sidewalls of the upper portion of the trench, and lower gate 203a is also insulated from body region 204 and epitaxial layer 201 by a gate dielectric layer 202a overlying the inner walls of the lower portion of the trench.
The following describes in detail a method for manufacturing a power device according to the present invention, taking the structure of the power device shown in fig. 2 as an example, with reference to fig. 5 and fig. 6 to 10, and fig. 11 to 14, and fig. 15 to 18.
Referring to fig. 5, an embodiment of the invention provides a method for manufacturing a power device, including the following steps:
s1, providing a substrate, wherein the substrate is provided with at least one groove, a gate structure is formed in the groove, a body region is formed in the substrate at the periphery of the top of the groove, a doped region is formed in the surface layer of the body region, and the conductivity type of the doped region is opposite to that of the body region;
s2, covering a first interlayer dielectric layer on the substrate, wherein the doped region and the groove are both buried in the first interlayer dielectric layer;
s3, forming a floating field plate exposing a part of the surface of the first interlayer dielectric layer, wherein the floating field plate at least covers a part of a boundary interface between the groove and the doped region;
s4, covering a second interlayer dielectric layer on the first interlayer dielectric layer and the floating field plate, and etching the second interlayer dielectric layer, the first interlayer dielectric layer, the doped region and the body region with partial thickness to form a contact hole;
and S5, filling a conductive plug in the contact hole and forming an external metal layer on the second interlayer dielectric layer, wherein the conductive plug is electrically connected with the doped region and the body region, and the external metal layer is electrically connected with the conductive plug.
Referring to fig. 6, in step S1, first, a substrate 200 is provided, and an epitaxial layer 201 is formed on the substrate 200; then, etching a part of the epitaxial layer 201 through a photolithography and etching process to form at least one trench (not labeled in fig. 6) in the epitaxial layer 201, and further rounding the bottom and top of the trench; then forming an oxide layer on the inner wall of the groove by a thermal oxidation process; then, depositing polycrystalline silicon by a chemical vapor deposition process until all the grooves are filled; the excess oxide layer and polysilicon on the top surface of the epitaxial layer 201 are then removed by a chemical mechanical polishing process to form a gate dielectric layer 202 covering the inner walls of the trench and a gate 203 filled in the trench, thereby forming a gate structure in the trench. And then, taking the gate structure as a mask, performing body region ion implantation and doped region ion implantation on the epitaxial layer 201 at the periphery of the trench, and annealing to form a body region 204 and a doped region 205, wherein the conductivity types of the body region 204 and the doped region 205 are opposite, the bottom of the body region 204 is shallower than the bottom of the trench, and the doped region 205 is formed in the surface layer of the body region 204. The work of providing the substrate in step S1 is thus completed.
It should be noted that, in other embodiments of the present invention, in step S1, after the gate 203 is formed, the gate 203 may be etched back to some extent according to needs, so as to round the top of the trench, so as to optimize the electric field distribution at the top of the trench. In addition, when the upper gate and the lower gate shown in fig. 3 and 4 need to be formed in the trench, reference may be made to a conventional manufacturing process of a power device having an upper gate and a lower gate, which is not described herein again.
With continued reference to fig. 6, in step S2, a silicon dioxide film may be covered on the epitaxial layer 201 by a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, and a chemical mechanical polishing process may be used to perform a top planarization on the deposited silicon dioxide film to form a first interlayer dielectric layer 206a with a flat top surface for providing a flat process surface for a subsequent process, wherein a thickness of the first interlayer dielectric layer 206a after the top planarization above the doped region 205 is determined by a floating height of a floating field plate to be formed. The silicon dioxide film is formed by adopting a Plasma Enhanced Chemical Vapor Deposition (PECVD) process, so that on one hand, silicon in the epitaxial layer 201 and the doping region 205 can be prevented from being consumed, and the step coverage performance of the formed silicon dioxide is excellent, and on the other hand, the temperature of the process is usually lower than 450 ℃, and the performance of the existing structure in the substrate cannot be adversely affected. In other embodiments of the present invention, the first interlayer dielectric layer 206a may be made of other materials, such as silicon nitride.
Referring to fig. 7 and 8, in step S3, a polysilicon film with a certain thickness is formed on the first interlayer dielectric layer 206a by a low-temperature polysilicon deposition process at a process temperature usually lower than 450 ℃ (even lower than 300 ℃), and the polysilicon film is doped with N-type dopants such as phosphorus or arsenic, or P-type dopants such as boron or indium, so as to form a field plate layer 210 a; then, a patterned photoresist layer 211 is formed on the field plate layer 210a through a series of photolithography processes of photoresist coating, exposure, development, etc.; next, the field plate layer 210a is etched by using the patterned photoresist layer 211 as a mask to form the floating field plate 210, and at this time, the bottom surface of the floating field plate 210 is flush with the top surface of the first interlayer dielectric layer 206a, and at least covers a part of the interface between the trench and the doped region 205, and leaves the region of the doped region 205 where the conductive plug is to be formed later, thereby reducing the difficulty of etching the contact hole to be formed later, and the shape of the floating field plate 210 may be a strip shape extending along the length direction of the trench. The patterned photoresist layer 211 is then removed. The field plate layer 210a is formed by a low-temperature polysilicon deposition process, so that the existing structure in the substrate can be prevented from being adversely affected by polysilicon deposition.
It should be noted that in other embodiments of the present invention, in step S3, other conductive materials may be selected to form field plate layer 210, such as metal, metal silicide, doped silicon germanium, doped germanium or doped monocrystalline silicon, etc.
Referring to fig. 8 and 9, in step S4, first, a second interlayer dielectric layer 206b may be formed by using a low pressure vapor deposition process, where the material of the second interlayer dielectric layer 206b is different from the material of the first interlayer dielectric layer 206b, and the material of the second interlayer dielectric layer 206b includes at least one of phosphosilicate glass, borosilicate glass, borophosphosilicate glass, fluorosilicone glass, and silicon oxynitride, for example. The second interlayer dielectric layer 206b can bury the floating field plate 210 therein, and has a thickness depending on the height of the conductive plug to be formed, and the second interlayer dielectric layer 206b and the first interlayer dielectric layer 206a are stacked to form a desired insulating dielectric layer. Next, the second interlayer dielectric layer 206b above the doped region 205, the first interlayer dielectric layer 206a, the doped region 205 and the body region 204 below the doped region 205 are etched through photolithography and etching processes to form the contact hole 212.
Referring to fig. 10, in step S5, a thin adhesion layer 207 is first formed on the inner wall of the contact hole 212 by a suitable process such as sputtering, and then a metal material is filled into the contact hole by a process such as tungsten sputtering, and the excess adhesion layer 207 and the metal material on the top surface of the second interlayer dielectric layer 206b are removed by a process such as chemical mechanical polishing to form the conductive plug 208 filled in the contact hole 212. Then, an external metal layer 209 is formed on the second interlayer dielectric layer 206b by a series of processes such as metal deposition, photolithography, and etching. It should be noted that, when the sidewall of the contact hole 212 exposes the sidewall of the floating field plate 210, in order to avoid electrical leakage caused by electrical contact between the formed conductive plug 208 and the floating field plate 210, before the formation of the adhesion layer 207, the sidewall of the contact hole 212 is covered with an insulating medium, which exposes the doped region 205 at the bottom of the contact hole 212 and the corresponding surface of the body region 204, so as to ensure the electrical connection between the conductive plug 208 and the doped region 205 and the body region 204, respectively.
After step S5, ion implantation may be further performed from the back side of the substrate 200 to form another doped region (e.g., a drain region of a MOSFET, not shown), and a metal layer electrically contacting the another doped region is further formed on the back side of the substrate 200 by a back side metallization process.
It should be noted that, in the above embodiment, the conductive plug 208 and the external metal layer 209 are sequentially formed by two metal deposition processes, but the technical solution of the present invention is not limited thereto, and in other embodiments of the present invention, the conductive plug 208 and the external metal layer 209 are formed by one metal deposition process.
It should be further noted that, in the above embodiment, the floating field plate 210 is formed by depositing the field plate layer 210a on the first interlayer dielectric layer 206a, and performing photolithography and etching on the field plate layer 210a, but the technical solution of the present invention is not limited to only the above process for forming the floating field plate 210.
Specifically, as an example, please refer to fig. 5 and fig. 11 to fig. 14, in the manufacturing method of the power device according to another embodiment of the present invention, steps S1 to S5 are sequentially performed. The steps S1 to S2 are the same as those in the previous embodiment, and the specific process can be referred to the above description, which is not repeated herein. In addition, the planarized first interlayer dielectric layer 206a in step S2 is thick enough, so that in step S3, as shown in fig. 11, the first interlayer dielectric layer may be directly subjected to photolithography and etching to form a shallow opening 213 in the first interlayer dielectric layer 206a, where the surface of the gate 203 and the surface of the doped region 205 are not exposed by the shallow opening 213; then, referring to fig. 12 and 13, a field plate layer 210b is formed by a corresponding vapor deposition process, the field plate layer 210b has a thickness sufficient to fill the shallow opening 213, and the top surface of the field plate layer is further planarized by a chemical mechanical polishing process to the top surface of the first interlayer dielectric layer 206a to form a floating field plate 210, where the top surface of the floating field plate 210 is flush with the top surface of the first interlayer dielectric layer 206 a. Referring to fig. 13 and 14, step S4 and step S5 are executed, and steps S4 to step S5 are the same as those in the previous embodiment, and the specific process may refer to the above description, which is not repeated herein.
The method for manufacturing the power device shown in fig. 11 to 14 can achieve the same technical effects as those of the previous embodiment.
As another example, please refer to fig. 5 and fig. 15 to fig. 18, in a manufacturing method of a power device according to another embodiment of the present invention, steps S1 to S5 are sequentially performed. The steps S1 to S2 are the same as those in the previous embodiment, and the specific process can be referred to the above description, which is not repeated herein. In step S3, referring to fig. 15, a patterned photoresist layer 214 may be formed on the first interlayer dielectric layer 206a by a series of photolithography processes including photoresist coating, exposure, and development; then, referring to fig. 16, a field plate layer 210c is deposited on the patterned photoresist layer 214; next, referring to fig. 17, the patterned photoresist layer 214 and the excess field plate layer 210c thereon are stripped together, and the remaining field plate layer forms the floating field plate 210. Afterwards, referring to fig. 18, step S4 and step S5 are executed, and steps S4 to step S5 are the same as those in the previous embodiment, and the specific process may refer to the above description, which is not repeated herein.
In the method of manufacturing the power device shown in fig. 15 to 18, the floating field plate 210 is manufactured by a lift-off process, which can further simplify the process.
In addition, it should be noted that the technical solution of the present invention is applicable to any power device having a trench-type gate, such as a MOSFET, an IGBT, and the like, and can optimize the surface electric field distribution of the doped region (e.g., the source region of the MOSFET or the emitter region of the IGBT) on the periphery of the top of the gate trench, so as to achieve the purpose of improving the withstand voltage of the power device.
The above description is only for the purpose of describing the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the present invention.

Claims (10)

1. A power device having a trench gate, comprising:
the semiconductor device comprises a substrate and a plurality of semiconductor chips, wherein the substrate is provided with at least one groove, a gate structure is formed in the groove, a body region is formed in the substrate on the periphery of the top of the groove, a doped region is formed in the surface layer of the body region, and the conductivity type of the doped region is opposite to that of the body region;
an insulating dielectric layer formed on the substrate;
and the floating field plate is embedded in the insulating medium layer, at least covers part of a boundary interface between the groove and the doped region, and is isolated from the gate structure and the doped region through the insulating medium layer, and the floating height of the floating field plate accounts for 1/6-2/3 of the thickness of the insulating medium layer.
2. The power device of claim 1, wherein the floating field plate covers the trench entirely; and/or the floating field plate covers the whole doped region.
3. The power device of claim 1, in which the material of the floating field plate comprises at least one of a doped semiconductor, a metal silicide, and a metal.
4. The power device of claim 1, wherein a bottom of the trench and/or a top of the trench is rounded.
5. The power device of claim 1, wherein the gate structure has an upper gate and a lower gate, the lower gate is filled in a lower portion of the trench, the upper gate is filled in an upper portion of the trench, and the upper gate and the lower gate are insulated and isolated from each other by a gate isolation layer.
6. The power device of claim 1, further comprising:
the conductive plug penetrates through the insulating medium layer and the doped region, and the bottom of the conductive plug extends into the body region with partial thickness below the doped region so as to be electrically connected with the doped region and the body region;
and the external metal layer is formed on the insulating medium layer and is electrically connected with the conductive plug.
7. A method for manufacturing a power device with a trench gate according to any one of claims 1 to 6, comprising:
providing a substrate, wherein the substrate is provided with at least one groove, a gate structure is formed in the groove, a body region is formed in the substrate on the periphery of the top of the groove, a doped region is formed in the surface layer of the body region, and the conductivity type of the doped region is opposite to that of the body region;
covering a first interlayer dielectric layer on the substrate, wherein the doped region and the groove are both buried in the first interlayer dielectric layer;
forming a floating field plate exposing a part of the surface of the first interlayer dielectric layer, wherein the floating field plate at least covers a part of a boundary interface between the groove and the doped region;
covering a second interlayer dielectric layer on the first interlayer dielectric layer and the floating field plate, wherein the second interlayer dielectric layer and the first interlayer dielectric layer are stacked to form an insulating dielectric layer, and the floating height of the floating field plate accounts for 1/6-2/3 of the thickness of the insulating dielectric layer.
8. The manufacturing method according to claim 7, wherein the first interlayer dielectric layer is made of silicon dioxide or silicon nitride, and the second interlayer dielectric layer is made of at least one of silicon oxynitride, borosilicate glass, phosphosilicate glass, fluorosilicone glass, borophosphosilicate glass, and borophosphofluorosilicone glass.
9. The method of manufacturing of claim 7, wherein the step of forming the floating field plate comprises: depositing a field plate layer on the first interlayer dielectric layer, and photoetching and etching the field plate layer to form the floating field plate;
or, the step of forming the floating field plate includes: etching the first interlayer dielectric layer with partial thickness to form a shallow opening, filling a field plate layer in the shallow opening, and flattening the top surface of the field plate layer to the top surface of the first interlayer dielectric layer to form the floating field plate;
or, the step of forming the floating field plate includes: and forming a patterned photoresist layer on the first interlayer dielectric layer, depositing a field plate layer on the photoresist layer, and stripping the photoresist layer and the redundant field plate layer above the photoresist layer to form the floating field plate.
10. The method of manufacturing of claim 7, further comprising, after covering the second interlayer dielectric layer over the first interlayer dielectric layer and the floating field plate:
etching the second interlayer dielectric layer, the first interlayer dielectric layer, the doped region and the body region with partial thickness to form a contact hole;
and filling a conductive plug in the contact hole and forming an external metal layer on the second interlayer dielectric layer, wherein the conductive plug is electrically connected with the doped region and the body region, and the external metal layer is electrically connected with the conductive plug.
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