CN111291526A

CN111291526A - Novel method for simulating stability of fast power supply loop

Info

Publication number: CN111291526A
Application number: CN202010185747.4A
Authority: CN
Inventors: 韩朝辉; 陈盈安; 卢笙
Original assignee: Xinqiyuan Shanghai Semiconductor Technology Co ltd
Current assignee: Xinqiyuan Shanghai Semiconductor Technology Co ltd
Priority date: 2020-03-17
Filing date: 2020-03-17
Publication date: 2020-06-16

Abstract

The invention discloses a novel method for rapid power supply loop stability simulation, which uses a distributed model for modeling and extracts S parameters when the power supply loop stability is simulated. Because the extraction of the parasitic parameters of the power supply network takes a large amount of time in the simulation method in the prior art, the method provided by the invention is more concise and effective, the simulation time of a plurality of weeks is shortened to be completed within one day, and the correctness of the simulation result can be ensured.

Description

Novel method for simulating stability of fast power supply loop

Technical Field

The invention belongs to the field of circuit simulation, and particularly relates to power supply loop stability simulation.

Background

With the development of social economy and the progress of science and technology, people have greater and greater requirements on electronic products, the quality of the products and the use experience, and particularly consumer electronics such as mobile phones, PADs and the like. The contradiction between product miniaturization and performance enhancement is increasingly irreconcilable. The switching power supply is used as a power center of electronic products, and from the prior discrete power supply modules to the present and a special power supply IC, the integration level of the switching power supply is higher and higher from the original external inductor to the present integration of the inductor into the IC, which is an inevitable requirement for miniaturization of consumer electronic products and other electronic products with special scenes on the other hand. Electronic products are powerful in performance, the operating frequency of an IC is required to be increased, the power consumption of the IC is required to be increased, and at present, due to the fact that the electronic products are environment-friendly and are partially powered by batteries, the low power consumption is strongly required. Therefore, the IC necessarily uses advanced IC technology, such as the mainstream mobile phone SOC chip of high-pass, haisi, etc., and the chip has been designed using 7nm technology. The IC produced by the advanced process is usually low-voltage and high-current, and can particularly meet the power requirements of 0.7V and 15A at present, so that PMU (power Manager unit) for supplying power correspondingly can provide such high power, and because the volume of the mobile phone is limited, the PMU needs to be as small as possible, and increasing the switching frequency of the switching power supply becomes an effective method. With the increase of the switching frequency, a series of problems are brought, such as efficiency reduction caused by the increase of the switching power consumption, heat generation of a power supply chip, stability of a power supply loop and the like.

At present, the main method for simulating the stability of a power supply loop is to use a SPICE model of a power supply IC through transistor-level simulation tools such as H-SPICE and the like, configure peripheral circuits aiming at pins of the SPICE model, build a circuit netlist of the whole power supply IC, and then simulate to obtain two most important parameter curves representing the stability of the power supply loop: phase curves and gain curves as shown in figure 1. The specific simulation process is shown in fig. 2: firstly, confirming a simulation network; secondly, confirming a simulation model of the device, and extracting RLC parameters of the simulation network in a segmented manner; thirdly, checking the correctness of the simulation model and the simulation network RLC parameters; fourthly, building a simulation netlist; and fifthly, ending if the simulation passes, and executing the second step again if the simulation does not pass. In the simulation method in the prior art, a simulation process, an abstract topological graph, and an obtained phase curve and gain curve, which take a PCB layout as an example, are respectively shown in fig. 3, fig. 4, and fig. 5. In fig. 3, the switching power supply and the load chip are located as shown, with a complete power plane from the output of the switching power supply to the load chip. In the power supply network, the capacitors are distributed in three regions in a centralized way, the regional capacitors are C0-bit power supply output ends, and the capacitors are mainly capacitors with larger capacitance value and play a role in smoothing and filtering; the regional capacitor C1 is positioned at the periphery of the load chip, and is mainly a capacitor with larger capacitance value and used for suppressing the transient effect when the decoupling effect of the chip decoupling small capacitor is insufficient; the area capacitor C2 is mainly a decoupling capacitor for meeting the AC performance requirement of the load chip, and mainly uses small capacitors of 1uF, and these small-capacitance decoupling capacitors are all placed as close as possible to the power supply pin, so as to reduce the influence of ESL and optimize the AC performance of the load chip. The analysis of the simulation power supply network is integrated, the PCB layout is abstracted into a topological structure which can be simulated, in the modeling process, the discrete capacitors cannot be modeled one by one, the frequency of the power supply network is mainly concentrated in a low-frequency band, a lumped structure is adopted, the place where the capacitors are concentrated is taken as a point, the place where the capacitors are dispersed is ignored, and according to the principle, the abstracted topological structure is shown in figure 4. R0 and L0 are parasitic parameters of wiring from an output pin of the switching power supply to a first large capacitor, and C0 is an output capacitor which is closest to the power supply, and the number of the output capacitors can be one or more; r1 and L1 are parasitic parameters of the power network between the region of the capacitor C0 and the region of the capacitor C1; r2 and L2 are power supply network parasitic parameters between the capacitor area C1 and the capacitor area C2, and the number of capacitors in each capacitor area is actually set; r3 and R4 are jumper resistances for far end feedback and near end feedback point switching, and the two tracks are a pair of differential tracks. Thus, the confirmation of the network topology is completed, and the simulation topology is built. Next, it is required to obtain the SPICE model of the switching power supply and the RLC parameters of the segmented power supply network (C is high impedance at low frequency, and may be approximated as an open circuit, and only the parameter RL is considered here), and for the consideration of the accuracy of the simulation parameters, HFSS Q3D from ANSYS company is selected here as a parameter extraction object, parasitic parameters of each segment of the power supply network in the topology are respectively extracted, and the parameters are set as: frequency range: 10 KHz-10 MHz, step size: 100 KHz. After the extracted parasitic parameters are obtained, an SPICE netlist is built according to the determined network topology, simulation is started, and finally a gain curve and a phase curve representing the stability of the loop are obtained. Thereby determining whether the power supply feedback loop is stable. Generally, under normal load conditions, the closed loop gain is 0dB, the phase margin should be greater than 45 degrees, and if the input voltage, load and temperature variation range is very large, the phase margin should not be less than 30 degrees. When the phase is close to 0deg, the gain margin of the closed loop should be larger than 7dB, and for being far away from an unstable point, the gain margin is preferably larger than 12dB to ensure the stability of the loop. If the simulation result is not ideal, the loop parameters such as the capacitance position, the feedback routing and other influencing factors can be adjusted, and then the simulation is carried out again until the simulation result meets the loop stability judgment standard.

In summary, from the whole simulation process, we analyze the simulation method in terms of both simulation accuracy and simulation time. From the simulation precision, although the extraction precision of Q3D based on the finite element analysis is guaranteed, due to the RLC parameter-based analysis method, in the switching power supply output network, if the output capacitance distribution is very dispersed, and the load end has a plurality of power supply pins which are discretely distributed, the network topology is not easy to model, the topology structure is generally simplified, and a main point is selected as a simulation object, which may greatly deviate from the actual topology, thereby causing simulation errors to a certain extent. From the simulation time, since Q3D is based on finite element analysis, the extraction accuracy completely depends on the accuracy of grid division, so the extraction will take a lot of time, if the switch power supply is far from the load, the length of the related network is increased to some extent, the included grid will be more, if the power supply network is a large board project, the extraction of RLC parameters will take half a month or more, and at the same time, the Spice simulation itself will take a long simulation time. This severely impacts the progress of the project, further impacting the efficiency and cost of the research and development companies. Therefore, the inventor provides a simple and efficient simulation method, which gives consideration to the accuracy of the topology while sacrificing a certain extraction precision, and ensures the accuracy of the whole extraction parameters to a certain extent. In the above-described prior simulation, a three-week period is continued from the start of the simulation to the completion of the simulation, wherein the extraction of RLC parasitic parameters takes about two weeks.

Disclosure of Invention

The invention aims to improve the simulation efficiency and shorten the simulation time on the premise of not losing the simulation precision.

In order to achieve the above object, the present invention provides a new method for fast power loop stability simulation, which comprises the following steps:

the method comprises the steps of firstly, confirming a power supply network needing to be simulated, and determining a topological structure of the power supply network;

secondly, confirming a simulation model, and extracting s parameters of the power supply network;

thirdly, checking the correctness of the simulation model and the s parameter;

fourthly, building a simulation netlist;

and fifthly, ending if the simulation passes, and executing the second step again if the simulation does not pass.

Further, in the first step, determining the topology of the power supply network by adopting a distributed method;

further, in a second step, the S-parameters of the power network are extracted using PowerSI.

Because the extraction of the parasitic parameters of the power supply network takes a large amount of time in the existing simulation method, the invention provides a more concise and effective method, which shortens the simulation time of a plurality of weeks to be finished in one day and ensures the correctness of the simulation result.

Drawings

FIG. 1 is a prior art phase curve and gain curve characterizing the stability of a power supply loop;

FIG. 2 is a flow diagram of a prior art simulation process for power loop stability;

FIG. 3 is an exemplary prior art PCB layout for simulation of power loop stability;

FIG. 4 is a topological structure diagram according to the exemplary PCB layout shown in FIG. 3;

FIG. 5 is a phase curve and a gain curve obtained by simulating the PCB layout shown in FIG. 4 using the simulation process shown in FIG. 2;

FIG. 6 is a flow diagram of a simulation process for power loop stability according to the present invention;

FIG. 7 is a topology abstracted for the exemplary PCB layout of FIG. 3 using the method of the present invention;

FIG. 8 is an S-parameter plot extracted according to the method of the present invention;

FIG. 9 is a phase curve and a gain curve obtained by simulating a network topology (as shown in FIG. 7) determined by abstract modeling according to the simulation method of the present invention;

fig. 10 is a graph comparing a phase curve and a gain curve obtained by simulation using the prior art and the method of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features mentioned in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.

FIG. 6 is a flow chart of a simulation process for power loop stability according to the present invention. Since the SPICE model is provided by the IC development department and cannot be modified by the simulation engineer, further optimization can only be made for modeling of the simulated network topology. The lumped model in the original approach is changed to be handled using a distributed model. The accuracy of the distributed model is not higher than that of the lumped model in a low frequency band, but the distributed model does not have the step of segmenting an abstract model, so that the problem of inaccurate segmentation processing under the lumped model is counteracted to a certain extent.

The exemplary PCB layout in fig. 3 is taken as a specific embodiment, a new modeling method is adopted to model the exemplary PCB layout, and a distributed method is adopted to abstract out a topological structure to be simulated, as shown in fig. 7. The switching power supplies are the same power supply modules, R0 and L0 are the same as the original method, the power supply modules are generally very close to the output large capacitor, and the extraction does not take much time basically, so the method is the same as the original method. The S parameter is an S parameter of 4 ports acquired using a distributed modeling manner. The method uses PowerSI of Cadence company to extract S parameters of the network, uses the positive and negative electrodes of an output capacitor of a power supply module as a port 1, uses the positive and negative pins of a power supply at the side of a load chip as a port 2, uses the feedback differential input of a switching power supply as a port 3, and uses the feedback differential output at the side of the load as a port 4. In the PowerSI extraction, all capacitors in the power supply network are loaded with corresponding capacitor models, so that the method comprises all capacitors and position information of the capacitors, and is more accurate than a method of neglecting scattered capacitors in the original method modeling.

The simulated extraction ranges from 10KHz to 100MHz, and the resulting S-curve plot 8 is shown.

After the S parameters are extracted, the correctness of the S parameters is further checked by checking curve characteristics such as insertion return loss, and then the SPICE netlist is built according to the topological structure of fig. 7, and the phase curve and the gain curve obtained through simulation are shown in fig. 9. Fig. 10 is a graph comparing a phase curve and a gain curve obtained by simulation using the prior art and the method of the present invention. Therefore, the simulation time is 7 working days by using the new method, wherein the extraction time of the S parameter is one day, and the simulation time is greatly shortened compared with the original method. From comparison of simulation results, the simulation precision is slightly worse than that of the original method, and judgment and evaluation of normal simulation results are not influenced. By comparing the simulation results of the original method and the new method, the simulation time of the used new simulation method is greatly shortened, the simulation efficiency is improved, and the research and development speed of the product is further accelerated under the condition of ensuring the simulation precision.

When the stability of the power supply loop is simulated, the method for modeling by using the distributed model and extracting the S parameters is not limited to the method for extracting the S parameters by using the PowerSI, and the protection of the method is provided by using the distributed model only by using any S parameter extraction tool.

It will be understood by those skilled in the art that the foregoing is only a preferred embodiment of the invention and is not intended to limit the invention, and that any modification, equivalent replacement, or improvement made within the spirit and principle of the invention should be included in the scope of the invention.

Claims

1. A new method for simulating the stability of a fast power supply loop comprises the following steps:

A. confirming a power supply network needing simulation, and determining a topological structure of the power supply network;

B. confirming a simulation model, and extracting s parameters of the power supply network;

C. checking the correctness of the simulation model and the s parameter;

D. building a simulation netlist;

E. if the simulation passes, the simulation is finished, and if the simulation does not pass, the step B is executed again.

2. The method for new fast power loop stability simulation of claim 1 wherein the topology of the power network is abstracted in a distributed manner.

3. The method for new fast power loop stability simulation of claim 1 wherein PowerSI is used to extract S-parameters of the power network.