CN111274199A

CN111274199A - FPGA (field programmable Gate array) on-track reconstruction implementation method for injecting directional modification on difference

Info

Publication number: CN111274199A
Application number: CN202010076029.3A
Authority: CN
Inventors: 呼红阳; 谢元禄; 张坤; 霍长兴; 刘璟; 张君宇; 毕津顺
Original assignee: Institute of Microelectronics of CAS
Current assignee: Institute of Microelectronics of CAS
Priority date: 2020-01-23
Filing date: 2020-01-23
Publication date: 2020-06-12

Abstract

The invention provides an FPGA (field programmable gate array) on-track reconstruction implementation method for injecting directional modification on difference, which comprises the following steps of: step S1: carrying out XOR processing on the new matched code and the original matched code on the ground to generate a difference matched code; step S2: transmitting the difference configuration code generated in the step S1 through ground track communication and storing the difference configuration code in an FPGA configuration memory or a system buffer area; and step S3: and generating a new configuration code through readback decoding, wherein the new configuration code is used for directionally modifying the difference part in the original configuration code, and completing the FPGA on-orbit reconstruction of directionally modifying the difference. The method only carries out erasing operation on the unit needing to be modified, greatly reduces the number of sectors needing to be erased, effectively saves on-track reconstruction time, reduces the overall abrasion degree of the memory, and improves the reliability.

Description

FPGA (field programmable Gate array) on-track reconstruction implementation method for injecting directional modification on difference

Technical Field

The disclosure relates to the technical field of satellite data transmission and processing, in particular to an FPGA (field programmable gate array) on-orbit reconstruction implementation method for injecting directional modification on difference.

Background

At present, with the continuous development of satellite technology, the continuous improvement of user technical indexes and the increasingly intense market competition, the integration and the light miniaturization of functionality have become a mainstream trend of satellite-borne electronic equipment. The adoption of the miniaturization technology can reduce the volume, the weight and the power consumption of the satellite-borne electronic equipment, and improve the capability of the spacecraft for bearing the effective load and the efficiency ratio. The size of the printed board can be reduced and the number of pads can be reduced by adopting a high-function integrated miniaturized device. FPGA is an important realization mode for the miniaturization of satellite-borne digital circuits. In a satellite-borne FPGA application system, when a satellite is assembled and is transmitted by the satellite, the FPGA is difficult to reconstruct, the main bottleneck is that the data volume of the FPGA is too large, the speed of on-orbit signal transmission is very low, and for some satellite-borne single machines, one-time complete transmission of the FPGA code allocation needs to be performed for hundreds of on-orbit tasks theoretically, and the feasibility is lacked in actual operation.

In order to solve the above problems, the proposed solution is to compress the original data, for example, by using zero-run algorithm, etc., to reduce the data size to 1/5-1/3, but still needs to perform an on-track whole erase and rewrite operation on the memory chip.

BRIEF SUMMARY OF THE PRESENT DISCLOSURE

Technical problem to be solved

Based on the above problems, the present disclosure provides an FPGA on-track reconfiguration implementation method with directional modification noted in difference, so as to alleviate technical problems in the prior art, such as too large data amount of FPGA configuration, slow on-track signal transmission speed, and the need of performing operations of erasing and rewriting a memory chip on track.

(II) technical scheme

The invention provides an FPGA (field programmable gate array) on-track reconstruction implementation method for injecting directional modification on difference, which comprises the following steps of: step S1: carrying out XOR processing on the new matched code and the original matched code on the ground to generate a difference matched code; step S2: transmitting the difference configuration code generated in the step S1 through ground track communication and storing the difference configuration code in an FPGA configuration memory or a system buffer area; and step S3: and generating a new configuration code through readback decoding, wherein the new configuration code is used for directionally modifying the difference part in the original configuration code, and completing the FPGA on-orbit reconstruction of directionally modifying the difference.

In the embodiment of the present disclosure, step S3 includes: substep S31: a read-back process; substep S32: a decoding process; and sub-step S33: and (4) directional erasing process.

In the embodiment of the present disclosure, the format of the differential code matching is: the address add-or result.

In the embodiment of the present disclosure, the address refers to a complete address or a partial address corresponding to the difference configuration code in the FPGA configuration memory.

In the embodiment of the present disclosure, step S2 includes:

substep S21: if the transmission bandwidth allows, the differential configuration code can be stored in the FPGA configuration memory or the buffer area completely, and a one-time transmission mode can be adopted.

In the embodiment of the present disclosure, step S2 includes: substep S22: if the bandwidth is not allowed, the memory space of the FPGA configuration memory is limited, address judgment is carried out and directional erasing and writing are carried out on the FPGA configuration memory in a block mode in a multi-transmission mode, the difference of the addresses in the blocks is uploaded until the memory block unit is updated, and difference uploading of the next address block unit is carried out.

In the embodiment of the disclosure, when a one-time transmission mode is adopted, the difference matching codes of the complete addresses are uploaded to the satellite-borne single machine.

In the embodiment of the disclosure, when the differential configuration code is transmitted in the fractional transmission mode, a partial address or a complete address is adopted.

In the embodiment of the present disclosure, during decoding, the data bits of the original parity bits corresponding to the bits whose xor result is 1 are inverted, so as to obtain a new code.

In the embodiment of the present disclosure, the block size is self-defined according to the actual scene.

(III) advantageous effects

According to the technical scheme, the FPGA on-track reconstruction implementation method based on the difference of the present disclosure has at least one or part of the following beneficial effects:

(1) the difference matching code is generated through the XOR coding, so that the data volume is greatly reduced, and the transmission and the storage are convenient;

(2) only the unit needing to be modified is erased and written, the number of the sectors needing to be erased and written is greatly reduced, which is equivalent to 13.7 percent of the address space in the complete code allocation, and the on-track reconstruction time is effectively saved.

(3) Only the unit to be modified is erased and written, so that the overall abrasion degree of the memory is reduced, and the reliability is improved.

Drawings

Fig. 1 is a schematic flow chart of an FPGA on-track reconfiguration implementation method with directional modification noted differently in an embodiment of the present disclosure.

Fig. 2 is a schematic diagram of a reconstruction path of an FPGA on-track reconstruction implementation method with directional modification noted in difference in the embodiments of the present disclosure.

FIG. 3 is a schematic diagram of a logic architecture of an FPGA on-track reconfiguration implementation method with directional modification noted differently in an embodiment of the present disclosure; FIG. 3(a) is a schematic diagram of a logic architecture when a one-time transmission scheme is adopted; fig. 3(b) is a schematic diagram of a logic architecture when the fractional transmission method is adopted.

Detailed Description

The invention provides an FPGA (field programmable gate array) on-track reconstruction implementation method for difference upward injection directional modification, which adopts a difference upward injection mode and only modifies the difference part in a memory in a directional modification mode. The differential coding reduces the on-track transmitted matched data to 0.25% -1.8% of the original data, compared with the complete matched data erasing, the erasing address space is shortened to about 10% of the original data, and the on-track reconstruction time is shortened.

For the purpose of promoting a better understanding of the objects, aspects and advantages of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings.

In an embodiment of the present disclosure, a method for implementing FPGA on-rail reconstruction through difference injection and directional modification is provided, which is shown in fig. 1 to 3, and includes:

step S1: carrying out XOR processing on the new matched code and the original matched code on the ground to generate a difference matched code;

in the embodiment of the disclosure, the original configuration code is the configuration code stored in the configuration memory of the satellite-borne FPGA, and is the configuration code to be erased and replaced. The method mainly aims at that the original configuration code and the new configuration code are completely the same in data quantity, most data are the same, only a small part of byte data are different, byte records with the exclusive OR result not being 0 are recorded through exclusive OR processing and are used as a part of the differential configuration code to be transmitted to the orbiting satellite. As shown in table 1 below, the principle of the method for obtaining the xor result by performing xor processing on the original configuration code and the new configuration code is as follows:

address information	00	01	02	03	04	05
							Original matching code	00	32	02	31	40	20
New code	00	31	02	30	40	20
							XOR result	00	03	00	01	00	00

Table 1

Because the differential code matching format is as follows: address + xor result. The other part of the differential matching code is the corresponding address of the differential byte in the memory, and the address has two formats, one is a complete address, and for the SPI Flash memory, the general address is 3bytes, namely A [ 23: 0 ]. The second is a local address, and for an SPI Flash memory, the block erase address range can be taken as the local address range. For example, the minimum erase unit is 4KB, and the local address is A [ 11: 0 ].

The address refers to a complete address or a partial address corresponding to the difference byte in the memory, and the address only needs to be correctly mapped to a configuration position needing to be updated during decoding.

Step S2: transmitting the difference configuration code generated in the step S1 through ground track communication and storing the difference configuration code in an FPGA configuration memory or a system buffer area;

step S2 includes:

substep S21: if the transmission bandwidth is allowed, the differential configuration code can be completely uploaded to a satellite-borne single machine in a one-time transmission mode, namely, after all the differential results of one configuration file are uploaded to a satellite, erasing and writing work of the original configuration code of the configuration memory is carried out, and in the mode, the address format in the transmitted differential configuration code is required to be a complete address. The xor processing results in the difference code as shown in table 2 below:

all differential addresses	24’h01	24’h03
			Difference matching code	03	01

Table 2

Substep S22: if the transmission bandwidth is not allowed, a mode of transmitting for multiple times can be adopted, namely the difference result of the unit block address is uploaded, and the directional modification of the unit block address is completed. The process is then repeated for the next block of area updates.

The block size in step S22 is not limited, and may be defined by itself according to the actual scene.

In this case, the differential parity address format may use local addresses, as shown in table 3 below:

differential addresses between blocks	12’h01	12’h03
			Difference matching code	03	01

Table 3

When the differential matching code is transmitted in a multi-transmission mode, the complete address can also be adopted.

The function of the address judgment is to realize the directional erasing operation, namely, only the unit needing erasing operation is subjected to erasing operation, and the size of the address interval block of single operation is not limited.

The address judging function can be realized by the storage controller or can be realized by the control on the ground.

Step S3: and generating a new configuration code by reading back and decoding the difference configuration code, wherein the configuration code is used for directionally modifying the original configuration code storage area. Step S3, including:

substep S31: a read-back process;

the read-back process is to read back the encoding data in the memory (for example, SPI Flash in fig. 2) through the memory controller, and store the encoding data in the buffer area. The pairing code should be identical to the original pairing code used for the differential encoding.

The storage controller can simultaneously read the original configuration code and the uploaded difference configuration code in the satellite-borne FPGA configuration storage;

substep S32: a decoding process;

the decoding process is a process of modifying the cache data according to the difference matched codes and generating new matched codes. The specific decoding process is to invert the meta-configuration data bit corresponding to the bit with the XOR result of 1 according to the address information and the XOR information recorded by the differential configuration code, so as to obtain a new configuration code; the new configuration code can be obtained by decoding the address information, the original configuration code and the exclusive or result in the following table 4:

address information	00	01	02	03	04	05
							Original matching code	00	32	02	31	40	20
XOR result	00	03	00	01	00	00
							New code	00	31	02	30	40	20

Table 4

Substep S33: and (4) directional erasing process.

In this process, only the cells that need to be erased and written are erased and written. The directional erasing operation is performed after the read-back decoding is completed, and the size of the block interval of the directional erasing is not limited.

So far, the embodiments of the present disclosure have been described in detail with reference to the accompanying drawings. It is to be noted that, in the attached drawings or in the description, the implementation modes not shown or described are all the modes known by the ordinary skilled person in the field of technology, and are not described in detail. Further, the above definitions of the various elements and methods are not limited to the various specific structures, shapes or arrangements of parts mentioned in the examples, which may be easily modified or substituted by those of ordinary skill in the art.

From the above description, those skilled in the art should clearly recognize that the implementation method of the FPGA on-rail reconstruction with the directional modification is different from the present disclosure.

In summary, the present disclosure provides an implementation method for on-track reconstruction of an FPGA with directionally modified differences, which greatly reduces the amount of data of the difference configuration generated by xor encoding according to the statistical result. Taking the FPGA model XC5VFX200T as an example, the complete code size is 8857179B. In the experiment, a plurality of codes with different functions are subjected to exclusive-or coding. The experimental result shows that the larger the difference of the code matching function is, the larger the difference code matching data amount after the exclusive-or coding is, but the difference position shows the characteristic of appearing in a segmented manner, so that the characteristic of directional modification in the patent is met, and erasing operation is not required for consistent data. The experiment analyzes a plurality of code matching files with different functions, the maximum difference number is 32228B, and the minimum difference number is 11580B. According to the encoding mode of the complete address + difference result, the ratio of the size of the difference code to the original code is 32228 × 5/8857179-1.8%. During the directional erasing operation, the number of the block intervals (e.g. sectors) to be erased is 254, which is compared with 11.7% of the complete code allocation address space. If the partial address + difference result is used, taking the code with the difference number of 11580B as an example, the ratio of the size of the difference code to the original code is 11580 × 2.5/8857179-0.3%. In the process of directional erasing operation, the number of the required erasing block intervals (e.g. sectors) is 297, which is equivalent to 13.7% of the complete code allocation address space, and the on-track reconstruction time is effectively reduced.

It should also be noted that directional terms, such as "upper", "lower", "front", "rear", "left", "right", and the like, used in the embodiments are only directions referring to the drawings, and are not intended to limit the scope of the present disclosure. Throughout the drawings, like elements are represented by like or similar reference numerals. Conventional structures or constructions will be omitted when they may obscure the understanding of the present disclosure.

And the shapes and sizes of the respective components in the drawings do not reflect actual sizes and proportions, but merely illustrate the contents of the embodiments of the present disclosure. Furthermore, in the claims, any reference signs placed between parentheses shall not be construed as limiting the claim.

Unless otherwise indicated, the numerical parameters set forth in the specification and attached claims are approximations that can vary depending upon the desired properties sought to be obtained by the present disclosure. In particular, all numbers expressing quantities of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term "about". Generally, the expression is meant to encompass variations of ± 10% in some embodiments, 5% in some embodiments, 1% in some embodiments, 0.5% in some embodiments by the specified amount.

Furthermore, the word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements.

The use of ordinal numbers such as "first," "second," "third," etc., in the specification and claims to modify a corresponding element does not by itself connote any ordinal number of the element or any ordering of one element from another or the order of manufacture, and the use of the ordinal numbers is only used to distinguish one element having a certain name from another element having a same name.

In addition, unless steps are specifically described or must occur in sequence, the order of the steps is not limited to that listed above and may be changed or rearranged as desired by the desired design. The embodiments described above may be mixed and matched with each other or with other embodiments based on design and reliability considerations, i.e., technical features in different embodiments may be freely combined to form further embodiments.

Those skilled in the art will appreciate that the modules in the device in an embodiment may be adaptively changed and disposed in one or more devices different from the embodiment. The modules or units or components of the embodiments may be combined into one module or unit or component, and furthermore they may be divided into a plurality of sub-modules or sub-units or sub-components. All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any method or apparatus so disclosed, may be combined in any combination, except combinations where at least some of such features and/or processes or elements are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Also in the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware.

Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the disclosure, various features of the disclosure are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various disclosed aspects. However, the disclosed method should not be interpreted as reflecting an intention that: that is, the claimed disclosure requires more features than are expressly recited in each claim. Rather, as the following claims reflect, disclosed aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this disclosure.

The above-mentioned embodiments are intended to illustrate the objects, aspects and advantages of the present disclosure in further detail, and it should be understood that the above-mentioned embodiments are only illustrative of the present disclosure and are not intended to limit the present disclosure, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present disclosure should be included in the scope of the present disclosure.

Claims

1. An FPGA on-orbit reconstruction implementation method for differentially injecting directional modification comprises the following steps:

step S2: transmitting the difference configuration code generated in the step S1 through ground track communication and storing the difference configuration code in an FPGA configuration memory or a system buffer area; and

step S3: and generating a new configuration code through readback decoding, wherein the new configuration code is used for directionally modifying the difference part in the original configuration code, and completing the FPGA on-orbit reconstruction of directionally modifying the difference.

2. The on-track reconstruction implementation method of a differentially-oriented modified FPGA of claim 1, step S3, comprising:

substep S31: a read-back process;

substep S32: a decoding process; and

substep S33: and (4) directional erasing process.

3. The on-track reconstruction implementation method of a differentially injection oriented modified FPGA of claim 1, the differential code allocation format being: the address add-or result.

4. The method according to claim 3, wherein the address is a complete address or a partial address corresponding to the difference configuration code in the FPGA configuration memory.

5. The on-track reconstruction implementation method of a differentially injection oriented modified FPGA of claim 1, step S2 comprising:

6. The on-track reconstruction implementation method of a differentially injection oriented modified FPGA of claim 1, step S2 comprising:

substep S22: if the bandwidth is not allowed, the memory space of the FPGA configuration memory is limited, address judgment is carried out and directional erasing and writing are carried out on the FPGA configuration memory in a block mode in a multi-transmission mode, the difference of the addresses in the blocks is uploaded until the memory block unit is updated, and difference uploading of the next address block unit is carried out.

7. The method for realizing on-track reconstruction of FPGA with directionally modified difference injection according to claim 5, wherein the difference code of the complete address is uploaded to the satellite-borne single machine in a one-time transmission mode.

8. The method for realizing on-track reconstruction of FPGA with directionally modified difference injection according to claim 6, wherein a partial address or a complete address is adopted when the difference matching code is transmitted in a time-sharing transmission mode.

9. The method for realizing on-track reconstruction of the FPGA with the difference-up-injection directional modification as claimed in claim 2, wherein the meta-configuration data bits corresponding to the bit bits with the XOR result of 1 are inverted during decoding, so as to obtain a new configuration code.

10. The on-orbit reconstruction implementation method of a differentially injected directionally modified FPGA of claim 6, the block size being self-defined according to the actual scene.