CN106843191A - The in-orbit maintaining methods of FPGA and device - Google Patents
The in-orbit maintaining methods of FPGA and device Download PDFInfo
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- CN106843191A CN106843191A CN201611172737.7A CN201611172737A CN106843191A CN 106843191 A CN106843191 A CN 106843191A CN 201611172737 A CN201611172737 A CN 201611172737A CN 106843191 A CN106843191 A CN 106843191A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B23/00—Testing or monitoring of control systems or parts thereof
- G05B23/02—Electric testing or monitoring
- G05B23/0205—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults
- G05B23/0208—Electric testing or monitoring by means of a monitoring system capable of detecting and responding to faults characterized by the configuration of the monitoring system
- G05B23/0213—Modular or universal configuration of the monitoring system, e.g. monitoring system having modules that may be combined to build monitoring program; monitoring system that can be applied to legacy systems; adaptable monitoring system; using different communication protocols
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/24—Pc safety
- G05B2219/24065—Real time diagnostics
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Abstract
The present invention is applied to technical field of data processing, there is provided a kind of in-orbit maintaining methods of FPGA and device, methods described include：Data flow is noted in generation；Wherein, the upper note data flow includes that original configuration stream file configures the difference frame of stream file with target；According to the absolute starting address corresponding to the difference frame in the upper note data flow, by the upper note data storage area of the upper note data flow writing controller FPGA carries；According to restructuring directive, the upper note data flow is read from the upper note data storage area, and the upper note data flow is loaded onto in FPGA.Methods described can greatly reduce note data volume, be noted in shortening the time, and power is formed in raising.
Description
Technical field
Technical field of data processing of the present invention, and in particular to a kind of in-orbit maintaining methods of FPGA and device.
Background technology
Although space electronic product, by various strict tests and verification experimental verification, still may on ground during in-orbit flight
Unforeseen failure occurs.In these failures, FPGA (Field Programmable Gate are frequently can lead to
Array, field programmable gate array) in-orbit mission requirements change, or in-orbit amendment FPGA design mistake, therefore defend
The in-orbit upper note technology of star is arisen at the historic moment.
In-orbit upper note technology can greatly improve reliability and the operation on orbit life-span of electronic product.By upper note FPGA technology
Apply has many advantages, such as in aerospace electron product：Software for Design mistake is for example changed after vehicle launch, with fault-tolerant as mesh
In-orbit upper note, software realizes modification and renewal of algorithm etc., and it is complicated and changeable that in-orbit upper note technology can adapt to system
Tasks of science, realizes that the exploitation between different task is reused.
During realizing by invention, inventor has found that prior art at least has problems with：Communicated by the world
Telemetry system noted in data, due to the reason such as the bandwidth limitation of telemeter communication, when the whole configuration files of upper note, it is necessary to consume
Take long time, and because upper note data volume is big, when telemeter communication is interfered, its transmission reliability is low, often needs
Largely to transmit repeatedly, so as to cause in-orbit upper note technology of the prior art, the upper note time in space environment is long, reliable
Property is low.
The content of the invention
In view of this, the embodiment of the present invention provides the in-orbit maintaining methods of FPGA or device, solves upper note number in the prior art
According to the amount technical problem that above the note time is long, reliability is low caused by big.
A kind of embodiment of the present invention first aspect, there is provided in-orbit maintaining methods of FPGA, including：
Data flow is noted in generation；Wherein, the upper note data flow includes that original configuration stream file configures stream file with target
Difference frame；
According to the absolute starting address corresponding to the difference frame in the upper note data flow, by the upper note data flow write-in
In the upper note data storage area of controller FPGA carries；
According to restructuring directive, the upper note data flow is read from the upper note data storage area, and by the upper note number
It is loaded onto in FPGA according to stream.
A kind of embodiment of the present invention second aspect, there is provided in-orbit attending devices of FPGA, including：
Upper note data flow generation module, for generating upper note data flow；Wherein, the upper note data flow includes original configuration
Stream file configures the difference frame of stream file with target；
Writing module, for according to the absolute starting address corresponding to the difference frame in the upper note data flow, by described in
In the upper note data storage area of upper note data flow writing controller FPGA carries；
Upper injection molding block, for according to restructuring directive, the upper note data flow being read from the upper note data storage area, and
The upper note data flow is loaded onto in FPGA.
Using above-mentioned technical proposal, the present invention can at least obtain following technique effects：By generating that differentiation is small, including
Original configuration stream file with the upper note data flow of the difference frame of target configuration stream file noted on increment, after function is changed
The difference frame of fresh code and original code configuration stream file as upper note minimum primitive, and telemetry bus by On-Star system connect
The different frame data file of astigmat, finally stores into nonvolatile memory FLASH under the manipulation of processor and controller FPGA,
So as to quickly realize that loading is noted and completed on in-orbit increment, realize to the in-orbit maintenances of FPGA.The method can greatly reduce note number
According to amount, noted in shortening the time, power is formed in raising, be that the in-orbit execution multitasks of SRAM type FPGA and task flexibly change offer
Approach, meets high flexibility, high reliability, the demand of implementation capacity high of the aerospace applications such as contemporary satellite.
Brief description of the drawings
Technical scheme in order to illustrate more clearly the embodiments of the present invention, institute in being described to the embodiment of the present invention below
The accompanying drawing for needing to use is briefly described, it should be apparent that, drawings in the following description are only some implementations of the invention
Example, for those of ordinary skill in the art, on the premise of not paying creative work, can also implement according to the present invention
The content and these accompanying drawings of example obtain other accompanying drawings.
Fig. 1 is the flow chart of the in-orbit maintaining methods of FPGA described in the present embodiment；
Fig. 2 is the flow chart that data flow is noted in generation described in the present embodiment；
Fig. 3 is the another flow chart that data flow is noted in generation described in the present embodiment；
Fig. 4 is that the frame address described in the present embodiment maps schematic diagram with FLASH memory spaces；
Fig. 5 is the configuration data stream process chart described in the present embodiment；
Fig. 6 is the structured flowchart of the in-orbit attending devices of FPGA described in the present embodiment；
Fig. 7 is the structured flowchart of the upper note data flow generation module described in the present embodiment.
Specific embodiment
The disclosure for providing description referring to the drawings to help comprehensive understanding to be limited by claim and its equivalent
Various embodiments.Hereinafter description includes the various details for helping understand, but these details will be considered as only being example
Property.Therefore, it will be appreciated by those of ordinary skill in the art that do not depart from the scope of the present disclosure and spirit in the case of, can be right
Various embodiments described herein makes various changes and modifications.In addition, in order to clear and succinct, known function and construction are retouched
Stating to be omitted.
Term and vocabulary used in following description and claims are not limited to document implication, but only by inventor
For enabling the disclosure clearly and as one man to be understood.Therefore, to those skilled in the art it should be apparent that carrying
The description of various embodiments of this disclosure is merely to exemplary purpose under being provided with, and it is unrestricted by appended claims and its
The purpose of the disclosure that equivalent is limited.
It should be understood that unless context is clearly indicated in addition, otherwise singulative also includes plural.Thus, for example,
Reference to " assembly surface " includes the reference to one or more such surfaces.
Embodiment one
Fig. 1 is the flow chart of the in-orbit maintaining methods of the present embodiment FPGA.Wherein, the FPGA in the embodiment of the present invention specifically may be used
Think SRAM type FPGA, but be not limited thereto.SRAM type FPGA is the Virtex-4 of Xilinx companies, Virtex-5,
The Series FPGAs such as Virtex-6 and other companies manufacture can the type such as frame support structure burning configuration file FPGA.With
In lower embodiment, illustrated by taking SRAM type FPGA as an example.
With reference to Fig. 1, the in-orbit maintaining methods of FPGA described in the present embodiment may include steps of：
Step S101, notes data flow in generation.
Wherein, the upper note data flow can include that original configuration stream file configures the difference frame of stream file with target.
Referring to Fig. 2, in one embodiment, step S101 may comprise steps of：
Step S201, according to address distribution, by target configuration stream file configuration data area's insertion frame address, shape
Stream file is configured into the upper note with frame as minimum unit.
Specifically, after by coding change, the target that meets new task demand configuration stream file * .bit, according to its address
The method of salary distribution, frame address is inserted by bit stream file configuration datas area, forms the complete configuration stream of the upper note with frame as minimum unit
File.Will be by taking Virtext-4XQR4VSX55 as an example, it has 17304 configuration frames, and it is 41 words that the length per frame is.Frame ground
Location length is a word, and length of the data frame per frame is no longer 41 words behind configuration data area insertion address, but 42 words.Institute
The upper note configuration stream file of insertion frame address is stated, is the complete stream text in system required for controller FPGA loading SRAM types FPGA
Part.
The upper note * .bit stream files for generating are carried out the extraction of configuration data section, one is obtained and complete is comprised only FPGA
The stream file of internal resource use information.The stream file is carried out into insertion frame address according to the minimum particle size of FPGA configuration data to grasp
Make, wherein 41 configuration data words are a frame, intubating length is a frame address for word, the configuration of each frames of FPGA before each frame
Data one frame address of unique correspondence, the address indicates the logical resource represented by the frame configuration data in the position of FPGA bottoms
Distribution.The configuration data stream inserted after frame address is combined, as shown in Figure 4 the configuration flow data after insertion frame address.Most
Afterwards by this combine after comprising frame address configuration data stream file insertion on note bit stream files, as shown in Figure 5.The step is generated
Bit stream files be complete burning bit stream files, the bit stream files of original configuration data field FLASH1 storages are spacecrafts
First performed according to the step before transmitting and produce and be burned onto in the FLASH1 of original configuration data field.
Step S202, the upper note configuration stream file is contrasted with the original configuration stream file, in units of frame
Two difference frames of configuration stream file are extracted, the upper note data flow is formed.
In this step, by the upper note configuration data stream text of the available configuration data area insertion frame address of step S201
Part, it is in the same size with original configuration stream file.The upper note configuration data stream file and original configuration number of new task demand will be met
Contrasted according to stream file, two discrepant frames of configuration data stream are extracted in units of frame, data frame collection is noted in formation.Then
Upper note data frame or multiframe data combination piecemeal, formation are waited to note data frame or data block, as described upper note data flow.
By taking Virtext-4XQR4VSX55 as an example, it has 17304 configuration frames, and FPGA code is carried out to meet conventional existing
After note demand change amount makes change on rail, its otherness frame is generally 300~2000 frames, and changing frame after modification code accounts for original
Less than the 20% of bit files, can be substantially reduced the frame sequence otherness quantity generated after conventional change code.
Further, before step S201, step S101 can also be comprised the following steps：
Step S301, the FPGA internal resources to being used after original code placement-and-routing carry out range constraint.
Specifically, can be on the basis of source code using the design software Planahead interacted with ISE, to primary
The FPGA internal resources used after code placement-and-routing carry out range constraint, and the layout of fpga logic resource has been used to lock.
The corresponding FPGA internal logics of original source code are carried out into delamination area constraint and execution logic placement-and-routing
Lock function so that ensure that the logical wiring that module is not changed in code change keeps constant, the inside modules of change are rung
The logic change amount answered is minimum, and being routed in each logical layer in FPGA inside changes minimum under conditions of meeting sequential.
Special instruction, when FPGA internal logics hierarchical layout is constrained, is wrapped in the layer that each section is divided
The resource quantities such as the logic unit and RAM (random access memory, random access memory) core that contain will fully meet
Resource requirement needed for the module, so in follow-up coding change, the work schedule and other performances for not interfering with FPGA refer to
Mark, and the success rate of FPGA underlying resources placement-and-routing can be improved.
Step S302, the code module to needing to change in original code carries out delamination area again and constrains.
In this step, on the basis of step S301 is completed, the code module to needing this dynamic carries out delamination area again
Constraint, it is therefore intended that the functional module for needing to change is constrained to less scope, makes variation code module use resource
Distribution is controllable.
Specifically, to entering row constraint by internal logic newly-generated after coding change, comprehensive realization.By by original
UCF unbound documents be modified, mask the internal logic constraint of the failure for having changed, and newly-generated to the module patrol
Collect unit carries out range constraint again, its newly-generated internal logic is responded in the range constraint of the module, reduces this and changes
The fpga logic resource that dynamic model block is used generates new upper note configuration bit stream files in the layout change of bottom.
Step S303, based on the original code after locking FPGA internal resources, changes the target mould for needing and changing
Block, generates the target configuration stream file.
It is baseline to lock the code engineering after FPGA underlying resources after execution of step S302 in this step, change step
The object module that the needs in rapid S302 are changed, changes its interior section code, " synthesis ", " placement-and-routing ".Cross herein
Failure constraint sentence suggested during placement-and-routing is shielded in journey, the error flag the change that FPGA internal resources are used, shielded
Cover.Meanwhile, the fuzzy region to changing module is added in original area unbound document and constrains sentence, it is therefore intended that will be new
The FPGA resource for using is constrained in controlled range, then generates target configuration stream file.
It should be understood that while making not done inside FPGA the logic unit section layout wiring fixation changed, to generation
Code transfer portion is constrained again, the corresponding logic unit in code change part is also kept minimum change.Based on this principle
Newly-generated FPGA configuration file and original contrast difference, according to the behaviour of code change when noting on satellite in orbit in the past
Make, according to code change amount situation, the frame difference of note configuration stream file and original configuration stream file is within 20% thereon.
By step S301 to S303, the functional module do not changed in fixed code FPGA bottoms layout, maximum limit
The resource region that uses of holding change inside modules of degree is constant, and the FPGA internal resources newly used due to coding change
It is controllable in predetermined region.So make fresh code minimum in the change of FPGA Lower level logicals resource placement so that newly-generated configuration is literary
Part and original difference are minimum, when mission requirements change needs the in-orbit upper notes of FPGA, only by original configuration stream file and new life
Into configuration stream file difference frame carry out on increment note, file data amount needed for note is greatly reduced.
Step S102, according to the absolute starting address corresponding to the difference frame in the upper note data flow, by the upper note
In the upper note data storage area of data flow writing controller FPGA carries.
In this step, upper note data frame or data block are sent to telemetry bus according to communication protocol, processor passes through
Upper note data frame is write and gives controller FPGA by EMIF interfaces, and then controller FPGA is by upper note data frame, according to the upper note number
According to the absolute starting address corresponding to the difference frame in stream, by the upper supreme note configuration data memory block of note data flow storage
In FLASH2, and can at least back up three parts.
Wherein, the first wife that system is included puts data storage area FLASH1 and upper note configuration data storage FLASH2, in boat
Before the transmitting of its device, each frame in identical original FPGA configurations stream file, and configuration data stream file can be stored in
Storage location of the data in FLASH1 with FLASH2 is consistent.
It should be understood that the upper note data flow for being recombinated by telemetry bus interface ground, having been split, by processor
And controller FPGA, upper note data flow three is backed up and note memory block on write-in FLASH2, realizing that SRAM type FPGA is in-orbit can be top
Note, it is possible to increase the memory reliability of the in-orbit upper note data of SRAM type FPGA
Step S103, according to restructuring directive, reads the upper note data flow from the upper note data storage area, and by institute
Note data flow is stated to be loaded onto in FPGA.
Preferably, can be upper note unit with the difference frame of the upper note data flow in this step, by the upper note data
Stream is loaded onto in FPGA.I.e., it is possible to every frame difference frame of the upper note data flow is separately carried out into upper note, it is loaded onto in FPGA.
Specifically, upper note frame by frame can be carried out according to the mapping relations of each frame data and FLASH memory spaces, if difference
Frame is more concentrated can then be carried out variance data collection piecemeal being noted on block-by-block in units of data block.The whole process of upper note is pressed
The Success Flag of upper note data is transmitted and received according to telemetry bus host-host protocol, if noting failure on certain frame, to the failure
Frame carries out again upper note, until being completed being noted in difference frame whole.
Preferably, note on described data storage area be stored with three parts it is described on note the Backup Data of data flow.Step
S103 is specially：
By three parts it is described it is upper note data flow Backup Datas one by one retaking of a year or grade and calculate verification and, if at least two parts upper notes
The verification of the Backup Data of data flow and verification when being sent with ground and consistent, then carry out noting the upper of data flow on next frame
Note, otherwise sends to ground control terminal check results.
It should be understood that this step is based on note in frame structure data, the three supreme note configuration data areas of backup storage simultaneously
In FLASH2, and realize the backup loadings of SRAM type FPGA tri-, can greatly improve the success rate of note, increase system reliability and
Extend the in-orbit life-span.For propping up that the Series FPGAs such as Virtex-4, Virtex-5, Virtex-6 and other companies are manufactured
The FPGA of frame structure burning configuration file type is held, only need to be by changing specific parameter, you can realize compatible Series FPGA high
In-orbit maintenance function.
It is upper note minimum data unit with the minimum frame of FPGA configuration stream files, only by the otherness frame with original
Note, upper on year-on-year basis to note whole configuration files, data volume will reduce more than 80%.In terms of the upper note time, due to daily upper note window
Mouthful open hour are about 4 hours, in upper note, by the bandwidth of telemetry communication limit and external environment interference etc. influence because
Element, upper note whole configuration files need the time of several days to complete, and the design is due to substantially reducing the number of upper explanatory notes part
According to amount, the upper note time can be shortened more than 80%, the time required to greatly reducing note, improve the success rate of note operation
With reliability.
The above-mentioned in-orbit maintaining methods of FPGA, by generating that differentiation is small, being configured including original configuration stream file and target
The upper note data flow of the difference frame of stream file noted on increment, and the fresh code after function is changed configures stream file with original code
Difference frame as the minimum primitive of upper note, and difference frame data file is received by the telemetry bus of On-Star system, in treatment
Finally stored into nonvolatile memory FLASH under the manipulation of device and controller FPGA, so as to quickly realize on in-orbit increment
Loading is noted and completed, is realized to the in-orbit maintenances of FPGA.The method can greatly reduce note data volume, be noted in shortening the time, improve
On form power, be that in-orbit multitask and the tasks of performing of SRAM type FPGA flexibly changes offer approach, meet the boats such as contemporary satellite
The high flexibility of empty AEROSPACE APPLICATION, high reliability, the demand of implementation capacity high.
Embodiment two
Corresponding to the in-orbit maintaining methods of FPGA described in foregoing embodiments, Fig. 6 shows provided in an embodiment of the present invention
The structured flowchart of the in-orbit attending devices of FPGA.For convenience of description, part related to the present embodiment is illustrate only, with reality above
Apply in place of the in-orbit maintaining methods of the FPGA described in example are repeated and be not repeated.
Fig. 6 is the structured flowchart of the in-orbit attending devices of FPGA described in the present embodiment.Referring to Fig. 6, FPGA is in-orbit to safeguard dress
Putting can include upper note data flow generation module 601, writing module 602 and upper injection molding block 603.Wherein：
Upper note data flow generation module 601, for generating upper note data flow.Wherein, the upper note data flow includes original
Configuration stream file configures the difference frame of stream file with target.
Writing module 602, for according to the absolute starting address corresponding to the difference frame in the upper note data flow, by institute
State note data flow writing controller FPGA carries upper note data storage area in.
Upper injection molding block 603, for according to restructuring directive, the upper note data being read from the upper note data storage area
Stream, and the upper note data flow is loaded onto in FPGA.
Preferably, referring to Fig. 7, the upper note data flow generation mould 601 can include first processing units 701 and difference frame
Unit 702.Wherein：
First processing units 701, for root according to address distribution, by target configuration stream file configuration data area
Insertion frame address, forms the upper note configuration stream file with frame as minimum unit.
Difference frame unit 702, for the upper note configuration stream file to be contrasted with the original configuration stream file, with
Frame is that unit extracts two difference frames of configuration stream file, forms the upper note data flow.
Further, referring to Fig. 7, the upper note data flow generation module 601 can also include the first constraint element 703,
Second constraint element 704 and second processing unit 705.Wherein：
First constraint element 703, for carrying out region about to the FPGA internal resources used after original code placement-and-routing
Beam.
Second constraint element 704, constrains for carrying out delamination area again to the code module for needing to change in original code.
Second processing unit 705, based on the original code after locking FPGA internal resources, changes the needs and changes
Dynamic object module, generates the target configuration stream file.
Preferably, the upper note unit 603 is upper note unit with difference frame, the upper note data flow is loaded onto FPGA
In.
In one embodiment, the upper note unit 603 can be specifically for：
By three parts it is described it is upper note data flow Backup Datas one by one retaking of a year or grade and calculate verification and, if at least two parts upper notes
The verification of the Backup Data of data flow and verification when being sent with ground and consistent, then carry out noting the upper of data flow on next frame
Note, otherwise sends to ground control terminal check results.
The above-mentioned in-orbit attending devices of FPGA, by generating that differentiation is small, being configured including original configuration stream file and target
The upper note data flow of the difference frame of stream file noted on increment, and the fresh code after function is changed configures stream file with original code
Difference frame as the minimum primitive of upper note, and difference frame data file is received by the telemetry bus of On-Star system, in treatment
Finally stored into nonvolatile memory FLASH under the manipulation of device and controller FPGA, so as to quickly realize on in-orbit increment
Loading is noted and completed, is realized to the in-orbit maintenances of FPGA.The method can greatly reduce note data volume, be noted in shortening the time, improve
On form power, be that in-orbit multitask and the tasks of performing of SRAM type FPGA flexibly changes offer approach, meet the boats such as contemporary satellite
The high flexibility of empty AEROSPACE APPLICATION, high reliability, the demand of implementation capacity high.
It should be noted that the various embodiments of the disclosure as described above are generally related to input data to a certain extent
Treatment and output data generation.The treatment of this input data and output data generation can be in hardware or soft with combination of hardware
Realized in part.For example, can in mobile device or similar or related circuit using specific electronic components for realize with
The function of the various embodiments association of the disclosure as described above.Alternatively, according to the instruction for being stored operate one or more
Multiple processors can realize the function of being associated with the various embodiments of the disclosure as described above.If it is, then these instructions
Can be stored on one or more non-transitory processor readable mediums, this is in the scope of the present disclosure.Processor can
The example for reading medium includes read-only storage (ROM), random access memory (RAM), CD-ROM, tape, floppy disk and optics number
According to storage device.In addition, for realizing that functional computer program, instruction and the instruction segment of the disclosure can be by disclosure arts
Programmer easily explain.
Although the various embodiments with reference to the disclosure have shown and described the disclosure, those skilled in the art will manage
Solution, in the case where the spirit and scope of the present disclosure being defined by the appended claims and the equivalents thereof are not departed from, can enter to it
Various changes in row form and details.
Claims (10)
1. in-orbit maintaining methods of a kind of FPGA, it is characterised in that including：
Data flow is noted in generation；Wherein, the upper note data flow includes that original configuration stream file configures the difference of stream file with target
Different frame；
According to the absolute starting address corresponding to the difference frame in the upper note data flow, by the upper note data flow write-in control
In the upper note data storage area of device FPGA carries；
According to restructuring directive, the upper note data flow is read from the upper note data storage area, and by the upper note data flow
It is loaded onto in FPGA.
2. method as claimed in claim 1, it is characterised in that data flow is noted in the generation to be included：
According to address distribution, target configuration stream file configuration data area's insertion frame address is formed with frame as minimum
The upper note configuration stream file of unit；
The upper note configuration stream file is contrasted with the original configuration stream file, two configuration streams are extracted in units of frame
The difference frame of file, forms the upper note data flow.
3. method as claimed in claim 2, it is characterised in that described according to address distribution, the target configured and is flowed
Frame address is inserted in file configuration data field, before forming the upper note configuration stream file with frame as minimum unit, also includes：
FPGA internal resources to being used after original code placement-and-routing carry out range constraint；
Code module to needing to change in original code carries out delamination area again and constrains；
Based on original code after locking FPGA internal resources, the object module for needing and changing is changed, generate the mesh
Standard configuration puts stream file.
4. method as claimed in claim 1, it is characterised in that with difference frame be upper note unit, by the upper note data flow loading
Into FPGA.
5. method as claimed in claim 4, it is characterised in that note on described data storage area be stored with three parts it is described on note number
According to the Backup Data of stream；It is described to read the upper note data flow from the upper note data storage area, and by the upper note data
Stream is specially in being loaded onto FPGA：
By three parts it is described it is upper note data flow Backup Datas one by one retaking of a year or grade and calculate verification and, if at least two parts upper note data
The verification of the Backup Data of stream and verification when being sent with ground and consistent, then carry out being noted on next frame the upper note of data flow, no
Then check results are sent to ground control terminal.
6. in-orbit attending devices of a kind of FPGA, it is characterised in that including：
Upper note data flow generation module, for generating upper note data flow；Wherein, the upper note data flow includes original configuration stream text
Part configures the difference frame of stream file with target；
Writing module, for according to the absolute starting address corresponding to the difference frame in the upper note data flow, by the upper note
In the upper note data storage area of data flow writing controller FPGA carries；
Upper injection molding block, for according to restructuring directive, reading the upper note data flow from the upper note data storage area, and by institute
Note data flow is stated to be loaded onto in FPGA.
7. device as claimed in claim 6, it is characterised in that the upper note data flow generation module includes：
First processing units, for root according to address distribution, by target configuration stream file configuration data area's insertion frame
Address, forms the upper note configuration stream file with frame as minimum unit；
Difference frame unit, for the upper note configuration stream file to be contrasted with the original configuration stream file, with frame as single
Two difference frames of configuration stream file are extracted in position, form the upper note data flow.
8. device as claimed in claim 7, it is characterised in that the upper note data flow generation module also includes：
First constraint element, for carrying out range constraint to the FPGA internal resources used after original code placement-and-routing；
Second constraint element, constrains for carrying out delamination area again to the code module for needing to change in original code；
Second processing unit, based on the original code after locking FPGA internal resources, changes the mesh for needing and changing
Mark module, generates the target configuration stream file.
9. device as claimed in claim 6, it is characterised in that the upper note unit with difference frame be upper note unit, on described
Note data flow is loaded onto in FPGA.
10. device as claimed in claim 9, it is characterised in that the upper note unit specifically for：
By three parts it is described it is upper note data flow Backup Datas one by one retaking of a year or grade and calculate verification and, if at least two parts upper note data
The verification of the Backup Data of stream and verification when being sent with ground and consistent, then carry out being noted on next frame the upper note of data flow, no
Then check results are sent to ground control terminal.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201611172737.7A CN106843191A (en) | 2016-12-18 | 2016-12-18 | The in-orbit maintaining methods of FPGA and device |
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| CN201611172737.7A CN106843191A (en) | 2016-12-18 | 2016-12-18 | The in-orbit maintaining methods of FPGA and device |
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| CN108021530A (en) * | 2017-12-22 | 2018-05-11 | 北京卫星信息工程研究所 | The in-orbit reconstructing method of general signal processing platform based on SOC |
| CN110705060A (en) * | 2019-09-19 | 2020-01-17 | 上海卫星工程研究所 | On-board data processing system architecture design method and system |
| CN111274199A (en) * | 2020-01-23 | 2020-06-12 | 中国科学院微电子研究所 | FPGA (field programmable Gate array) on-track reconstruction implementation method for injecting directional modification on difference |
| CN111309668A (en) * | 2020-01-23 | 2020-06-19 | 中国科学院微电子研究所 | On-track reconstruction implementation method of differentially injected erasing-free FPGA (field programmable Gate array) |
| CN113312305A (en) * | 2021-06-15 | 2021-08-27 | 西安微电子技术研究所 | FPGA-based aerospace electronic system on-orbit reconstruction method and system |
| CN113778487A (en) * | 2021-09-10 | 2021-12-10 | 深圳朴生智能科技有限公司 | Software uploading system and method of intelligent processing module |
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| CN110705060A (en) * | 2019-09-19 | 2020-01-17 | 上海卫星工程研究所 | On-board data processing system architecture design method and system |
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| CN113312305A (en) * | 2021-06-15 | 2021-08-27 | 西安微电子技术研究所 | FPGA-based aerospace electronic system on-orbit reconstruction method and system |
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| CN113778487A (en) * | 2021-09-10 | 2021-12-10 | 深圳朴生智能科技有限公司 | Software uploading system and method of intelligent processing module |
| CN114994637A (en) * | 2022-07-28 | 2022-09-02 | 北京一径科技有限公司 | Programmable logic device configuration and programmable logic device |
| CN114994637B (en) * | 2022-07-28 | 2022-11-15 | 北京一径科技有限公司 | Programmable logic device configuration and programmable logic device |
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