CN111244185B - Fin type transverse double-diffusion power device - Google Patents

Fin type transverse double-diffusion power device Download PDF

Info

Publication number
CN111244185B
CN111244185B CN202010084930.5A CN202010084930A CN111244185B CN 111244185 B CN111244185 B CN 111244185B CN 202010084930 A CN202010084930 A CN 202010084930A CN 111244185 B CN111244185 B CN 111244185B
Authority
CN
China
Prior art keywords
region
semiconductor
fin
gate
dielectric
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202010084930.5A
Other languages
Chinese (zh)
Other versions
CN111244185A (en
Inventor
姚佳飞
张振宇
郭宇锋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nanjing University Of Posts And Telecommunications Nantong Institute Co ltd
Original Assignee
Nanjing University Of Posts And Telecommunications Nantong Institute Co ltd
Nanjing University of Posts and Telecommunications
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nanjing University Of Posts And Telecommunications Nantong Institute Co ltd, Nanjing University of Posts and Telecommunications filed Critical Nanjing University Of Posts And Telecommunications Nantong Institute Co ltd
Priority to CN202010084930.5A priority Critical patent/CN111244185B/en
Publication of CN111244185A publication Critical patent/CN111244185A/en
Application granted granted Critical
Publication of CN111244185B publication Critical patent/CN111244185B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/66803—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with a step of doping the vertical sidewall, e.g. using tilted or multi-angled implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7855—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with at least two independent gates

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention discloses a fin type transverse double-diffusion power device.A fin type structure is prepared in an active region above a substrate, then high-dielectric-constant media are adopted to cover the two sides and the surface of the fin type active region, and the active region is modulated from three directions; the tri-gate replaces the original surface gate, so that the channel control capability is better, and the leakage current of the device during closing is reduced; changing a commonly used silicon oxide gate dielectric into a high-k gate dielectric can have a thicker physical oxide layer and improve the problem of gate leakage current. The invention has the advantages of high voltage resistance, low on resistance, low leakage current and the like, and is suitable for the high-voltage and high-frequency field.

Description

Fin type transverse double-diffusion power device
Technical Field
The invention relates to the technical field of semiconductor power devices, in particular to a fin type transverse double-diffusion power device.
Background
With the development of power chip design technology, power integrated circuits also put higher demands on the performance of semiconductor power devices, and as one of core devices of power integrated circuits, a lateral semiconductor power device needs to provide high breakdown voltage and low on-resistance to reduce power consumption, and may also require to have better sub-threshold characteristics and avoid short channel effect. The LDMOS has good process compatibility, excellent conversion performance, high power performance, high gain and linearity, and low manufacturing cost, and is widely used in DC-DC converters and radio frequency base stations.
The increase in breakdown voltage of the LDMOS tends to increase the on-resistance at the same time. This contradictory relationship limits the application of such devices in the high voltage and high current fields. With the increasing design requirements of semiconductor devices, the semiconductor device structure is promoted to expand to a three-dimensional structure, such as a fin field effect transistor. In a Fin type process, an LDMOS semiconductor device is changed into a Fin type three-dimensional structure, for example, Amin Pak, Ali A. Orouji.compact Modeling of Fin-LDMOS Based on the Surface Potential, Silicon, 2019, pp.1-6 relate to a Fin type LDMOS device, but the device only adopts a tri-gate structure to perform channel modulation, and no improvement is made on a drift region. The central international integrated circuit manufacturing (shanghai) limited proposed a lateral double diffused semiconductor device (CN104576732B) of parasitic FinFET that uses fin-like gate, source, and drain regions to improve device performance, but also has no modulating effect on the drift region.
Disclosure of Invention
The invention aims to: the invention aims to provide a fin type transverse double-diffusion power device, which utilizes two side surfaces and a top surface to modulate a fin type active region in three directions, not only can improve the grid control capability, but also can improve the breakdown voltage of the device and reduce the on-resistance of the device.
The technical scheme is as follows: the fin type transverse double-diffusion power device comprises a semiconductor substrate located at the lowest part, a buried layer located on the semiconductor substrate, and a fin type active region located above the buried layer; the fin active region comprises a fin part which is in a convex shape; the fin portion comprises a semiconductor drain region, a semiconductor drift region and a semiconductor well region, the semiconductor well region is located on one side of the semiconductor drift region, and the semiconductor drain region is located above the other side of the semiconductor drift region; the semiconductor well region comprises a semiconductor source region, a semiconductor body contact region and a channel region positioned between the semiconductor drift region and the semiconductor source region; the number of the fins may be one or more.
In the fin type active region, two sides and the surface of a fin part are covered with materials to form a medium region, a tri-gate electrode is arranged on two sides and the top of a channel region, a gate medium layer is arranged between the tri-gate electrode and the channel region, and the gate medium layer is a part of the medium region;
the fin type lateral double-diffused power device further comprises drain metal and source metal which are located above the active region, the drain metal is in contact with the semiconductor drain region, and the source metal is in contact with the semiconductor source region and the semiconductor body contact region.
The medium of the channel region tri-gate structure is the same high dielectric constant medium, so that the high dielectric constant medium material only needs to be filled once, and the high dielectric constant medium is adopted as the gate medium, so that the gate leakage current of the device can be improved; the three sides of the channel region are provided with the gate electrodes, a three-gate structure is formed, the channel control capability is better, the leakage current of the device during closing can be reduced, the short channel effect is inhibited, the hysteresis of the threshold voltage is greatly reduced, and the transconductance is obviously improved.
The dielectric region is made of a dielectric material with the dielectric constant higher than that of silicon, the electric potential and electric field distribution of the drift region of the device can be modulated from the surface and the side face to obtain higher breakdown voltage, and meanwhile, the auxiliary depletion effect of the high-dielectric-constant dielectric material on the drift region can improve the doping concentration of the drift region to reduce the on-resistance of the device.
Preferably, the fin active region comprises a number of discrete fins.
Wherein, three sides of the channel region are provided with gate electrodes to form a tri-gate structure; the depth of the gate electrodes on two sides of the channel region is the same as the thickness of the fin type active region.
The width of the fin portion can be 0.5-2 microns, and the width of the groove between the fin portions can be 0.5-2 microns.
The invention principle is as follows: according to the transverse power device, the active region above the substrate is prepared into a fin structure, and then the high-dielectric-constant medium is covered on the two sides and the surface of the fin active region, so that the active region is modulated from three directions. Meanwhile, the invention replaces the original surface gate with the tri-gate, has better channel control capability and reduces the leakage current when the device is closed. In addition, the common silicon oxide gate dielectric is changed into a high-K gate dielectric, so that the gate dielectric has a thicker physical oxide layer and the problem of gate leakage current is solved. The device prepared by the invention has the advantages of high voltage resistance, low on-resistance, low leakage current and the like, and is suitable for the high-voltage and high-frequency field.
Has the advantages that: according to the invention, high-dielectric-constant dielectric materials are introduced into two side surfaces and surfaces of the fin-type active region, three gate electrodes are formed on two side surfaces and surfaces of the channel region, and the gate dielectric between the electrode and the channel region is a high-dielectric-constant dielectric. On one hand, the high-dielectric-constant media introduced into the two side surfaces and the surface can modulate the drift region from three directions, firstly, the surface electric field and the longitudinal electric field of the drift region are adjusted, so that the breakdown voltage of the device is improved, and secondly, the doping concentration of the drift region can be greatly improved, so that the on-resistance of the device is reduced; on the other hand, the tri-gate structure is adopted to replace the original surface gate structure, so that good channel control capability can be provided, the leakage current of the device during closing can be reduced, the short channel effect is inhibited, the hysteresis of the threshold voltage is greatly reduced, and the transconductance is obviously improved. In addition, the high-dielectric constant dielectric is used as the gate dielectric between the three-gate electrode and the channel, so that a thicker physical oxide layer is provided, and the problem of gate leakage current can be improved.
Drawings
FIG. 1 is a schematic diagram of a conventional LDMOS structure;
fig. 2 is a schematic structural diagram of a fin-type double diffused power device according to the present invention;
FIG. 3 is a schematic diagram of the device structure after only the fin active region is fabricated;
fig. 4 is a schematic cross-sectional view of the finfet structure of the present invention along line a in fig. 2;
fig. 5 is a cross-sectional view of the finfet structure of the invention along line B1 in fig. 2, where line B1 is located directly above the semiconductor body contact region;
fig. 6 is a cross-sectional view of the fin-based double diffused power device structure of the present invention taken along line B2 in fig. 2, wherein line B2 is located directly above the semiconductor source region;
FIG. 7 is a cross-sectional view of the fin-based double diffused power device structure of the present invention taken along line B3 in FIG. 2, wherein line B3 is directly above the tri-gate electrode;
fig. 8 is a cross-sectional view of the finfet structure of the present invention taken along line B4 in fig. 2;
fig. 9 is a cross-sectional view of the finfet structure of the present invention taken along line B5 in fig. 2;
FIG. 10 is a cross-sectional view of a fin-based DMOS device structure along line A after forming a channel region;
fig. 11 is a cross-sectional view of the fin-based double diffused power device structure along line B3 after forming a channel region.
Detailed Description
The present invention will be described in further detail with reference to examples.
As shown in fig. 2, the LDMOS device includes a semiconductor substrate 1 located at the bottom, a buried layer 2 on the substrate, and a fin active region 3 located above the buried layer;
as shown in fig. 3, the fin active region 3 includes a plurality of discrete fin portions in a convex shape, three fin portions are shown in fig. 3, and both sides of each fin portion are provided with a dielectric groove region; each fin portion comprises a semiconductor drain region 4, a semiconductor drift region 5 and a semiconductor well region 8, wherein the semiconductor well region 8 is located on one side of the semiconductor drift region 5, and the semiconductor drain region 4 is located above the other side of the semiconductor drift region 5; wherein the semiconductor well region 8 comprises a semiconductor source region 6 and a semiconductor body contact region 7, and a channel region 15 located between the semiconductor drift region 5 and the semiconductor source region 6, i.e. the semiconductor body contact region 7 is located at the outer side and the semiconductor source region 6 is located at the inner side.
Two sides and the surface of a fin part of the fin active region 3 are both dielectric regions 9 which are made of dielectric materials with dielectric constants higher than that of silicon; the triple-gate electrode 10 is arranged at two sides and the top of the channel region 15, and the gate dielectric layer between the triple-gate electrode 10 and the channel region 15 is a part of the dielectric region 9. The fin type lateral double-diffused power device further comprises a drain metal 11 and a source metal 12 which are positioned above the active region 3, the drain metal 11 is in contact with the semiconductor drain region 4, and the source metal 12 is in contact with the semiconductor source region 6 and the semiconductor body contact region 7.
In the lateral double-diffused metal oxide semiconductor field effect transistor of the embodiment, an N-type drift region is taken as an example, as shown in fig. 2, a fin-type LDMOS semiconductor device of the present invention is shown, and compared with the structure schematic diagram of a conventional LDMOS device shown in fig. 1, the conventional lateral double-diffused metal oxide semiconductor LDMOS structure employs a surface metal gate electrode 13 and a silicon dioxide gate dielectric 14; according to the invention, the active region 3 above the substrate is changed into a fin structure, and then the high-dielectric-constant medium is adopted to cover the two sides and the surface of the fin active region 3, so that the active region is modulated from three directions. Meanwhile, the invention replaces the original surface gate with the tri-gate, has better channel control capability and reduces the leakage current when the device is closed. In addition, changing the commonly used silicon oxide gate dielectric into a high-k gate dielectric can have a thicker physical oxide layer and improve the problem of gate leakage current.
In this embodiment, the drift region 5 of the fin-type lateral double diffused power device is an N-type drift region, and the structure of the fin-type LDMOS semiconductor device in this embodiment is specifically described below.
The fin type LDMOS semiconductor device is formed on an SOI substrate, the thickness of top silicon of the SOI substrate is less than 1 micron, and the concentration range of the top silicon on the SOI substrate can be 1015 atoms/cm 3-1018 atoms/cm 3.
In the specific implementation mode of the invention, a silicon oxide layer, a silicon nitride layer and a photoresist layer are sequentially deposited on the surface of an SOI substrate, a pattern is formed on the photoresist by photoetching, the photoresist layer is used as a mask, a region without the photoresist mask is etched by adopting dry etching, a fin type active region 3 structure is formed on the top silicon of the SOI substrate, and the photoresist layer is removed. The width of the fin active region 3 may be 0.5 to 2 microns, and the width of the trench between the fins may be 0.5 to 2 microns.
And forming a P-well region, a semiconductor body contact region 7, a semiconductor source region 6 and a semiconductor drain region 4 on the fin type active region 3 by standard ion implantation through a mask. And forming a channel region by an annealing process.
The dielectric material is deposited and filled into the trenches 16 by magnetron sputtering, and completely covers the entire device surface, and then the dielectric material on the surface is polished to a certain thickness, such as 0.1 to 2 microns. The dielectric material surrounds the active region 3 from three directions, surface and two sides.
And etching contact holes in the dielectric materials on two sides of the channel region 15, wherein the depth of the contact holes is consistent with the thickness of the fin type active region 3. And etching the dielectric material at the source end and the drain end to form a contact hole, wherein the depth of the contact hole is consistent with the thickness of the surface dielectric material.
And depositing metal into the contact hole, and etching the metal to form a metal gate electrode, a metal source electrode and a metal drain electrode. The metal gate electrode surrounds the channel region from the surface and two sides to form a tri-gate structure, and the gate dielectric of the tri-gate structure is the high-dielectric-constant dielectric material. The source metal 12 forms a metal source electrode, crosses the active region 3 and the dielectric groove region, and contacts with the semiconductor source region 6 and the body contact region 7; the drain metal 11 forms a metal drain electrode that spans the active region 3 and the dielectric trench region and contacts the semiconductor drain region 4.
The channel region 15 is formed by the inversion of the p-well region into n-type after the gate voltage is increased, the position and size of the channel region are not fixed, and the channel region is also formed on both sides under the influence of the tri-gate, as shown in fig. 10 and 11.
The method for manufacturing the fin type lateral double-diffused metal oxide semiconductor field effect transistor comprises the following steps:
a, forming a fin type active region 3 structure on an SOI substrate by adopting dry etching;
b, injecting P-type impurities on the fin type active region 3 by adopting an ion injection process to form a P-type well region, namely a semiconductor well region 8;
c, injecting P-type impurities into the P-type trap by adopting an ion injection process to form a semiconductor body contact region 7;
d, injecting N-type impurities into the P-type well region and the N-type drift region 5 by adopting an ion injection process to form an N-type semiconductor source region 6 and a semiconductor drain region 4;
e, depositing and filling a dielectric material into the groove 16 and completely covering the whole device surface;
f, adopting chemical mechanical polishing to enable the surface of the dielectric layer to be flat and have a certain thickness;
step g, etching contact holes, wherein the depth of the contact holes on two sides of the channel region 15 is consistent with the thickness of the fin type active region 3; a contact hole of the source drain region reaches the surface of the active region 3;
step h: and depositing metal in the contact hole, and etching the metal to form a channel region triple gate electrode 10, a source electrode and a drain electrode.
The embodiments shown above are only examples of the LDMOS of the N-type drift region, and can also be applied to the LDMOS of the P-type drift region, and can also be applied to the lateral IGBT device.

Claims (2)

1. A fin type transverse double-diffused power device is characterized in that: the semiconductor device comprises a semiconductor substrate (1) positioned at the lowest part, a buried layer (2) positioned above the substrate and a fin type active region (3) positioned above the buried layer; the fin type active region (3) comprises a plurality of discrete fin parts, each fin part comprises a semiconductor drain region (4), a semiconductor drift region (5) and a semiconductor well region (8), wherein the semiconductor drain region (4) is located at one end of the semiconductor drift region (5), the semiconductor well region (8) is located at the other end of the semiconductor drift region (5), the semiconductor well region (8) comprises a semiconductor source region (6) and a semiconductor body contact region (7), channel regions (15) are formed on two sides and surfaces of the semiconductor well region (8), gate dielectric layers cover two sides and surfaces of each channel region (15), three gate electrodes (10) are formed on two sides and surfaces of each gate dielectric layer, and the depth of the three gate electrodes on two sides of each channel region (15) is the same as the thickness of the fin type active region (3); both sides and the surface of the fin part are covered with high-K dielectric materials to form a dielectric region (9), and the gate dielectric layer is a part of the dielectric region (9); the semiconductor structure further comprises a drain metal (11) and a source metal (12) which are located above the fin type active region (3), the drain metal (11) is in contact with the semiconductor drain region (4), and the source metal (12) is in contact with the semiconductor source region (6) and the semiconductor body contact region (7).
2. The fin-type lateral double diffused power device of claim 1, wherein: the width of the fin portion is 0.5-2 micrometers, and the width of the groove between the fin portion and the fin portion is 0.5-2 micrometers.
CN202010084930.5A 2020-02-10 2020-02-10 Fin type transverse double-diffusion power device Active CN111244185B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202010084930.5A CN111244185B (en) 2020-02-10 2020-02-10 Fin type transverse double-diffusion power device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202010084930.5A CN111244185B (en) 2020-02-10 2020-02-10 Fin type transverse double-diffusion power device

Publications (2)

Publication Number Publication Date
CN111244185A CN111244185A (en) 2020-06-05
CN111244185B true CN111244185B (en) 2022-07-08

Family

ID=70866244

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202010084930.5A Active CN111244185B (en) 2020-02-10 2020-02-10 Fin type transverse double-diffusion power device

Country Status (1)

Country Link
CN (1) CN111244185B (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112750911B (en) * 2021-02-03 2022-06-17 南京邮电大学 LDMOS with controllable three-dimensional electric field and preparation method thereof
CN113871489B (en) * 2021-12-02 2022-02-22 南京邮电大学 Full-surrounding multi-channel drift region transverse power device and manufacturing method thereof
CN115966596B (en) * 2023-03-13 2023-06-16 南京邮电大学 Separation groove transverse double-diffusion power device and manufacturing method thereof
CN117614432B (en) * 2023-10-30 2024-05-28 南京邮电大学 Dynamic back gate control system for improving performance of bulk silicon LDMOS and manufacturing method of bulk silicon LDMOS

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103000691A (en) * 2011-09-14 2013-03-27 美国博通公司 Half-FinFET semiconductor device and related method
CN106129116A (en) * 2016-07-27 2016-11-16 西安电子科技大学 One has change K medium and folds lateral double diffusion metal oxide semiconductor field effect transistor
CN110534566A (en) * 2019-09-05 2019-12-03 电子科技大学 A kind of IGBT power device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110416307A (en) * 2019-07-17 2019-11-05 上海华力集成电路制造有限公司 Semiconductor devices

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103000691A (en) * 2011-09-14 2013-03-27 美国博通公司 Half-FinFET semiconductor device and related method
CN106129116A (en) * 2016-07-27 2016-11-16 西安电子科技大学 One has change K medium and folds lateral double diffusion metal oxide semiconductor field effect transistor
CN110534566A (en) * 2019-09-05 2019-12-03 电子科技大学 A kind of IGBT power device

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
Folded-Accumulation LDMOST: New Power MOS Transistor With Very Low Specific On-Resistance;Baoxing Duan等;《IEEE ELECTRON DEVICE LETTERS》;20091120;第30卷;全文 *
Simulation-Based Study of Hybrid Fin/Planar LDMOS Design for FinFET-Based System-on-Chip Technology;Yi-Ting Wu等;《IEEE TRANSACTIONS ON ELECTRON DEVICES》;20170920;第64卷;正文第4193-4195页 *

Also Published As

Publication number Publication date
CN111244185A (en) 2020-06-05

Similar Documents

Publication Publication Date Title
CN111244185B (en) Fin type transverse double-diffusion power device
CN108807548B (en) Extensible SGT architecture with improved FOM
US7033891B2 (en) Trench gate laterally diffused MOSFET devices and methods for making such devices
US8803235B2 (en) Lateral-diffused metal oxide semiconductor device (LDMOS) and fabrication method thereof
WO2010036942A2 (en) Power mosfet having a strained channel in a semiconductor heterostructure on metal substrate
KR20040068203A (en) Trenched semiconductor devices and their manufacture
US11322617B2 (en) Semiconductor device
CN112164719B (en) Low resistance device with equipotential floating groove and manufacturing method thereof
WO2019228069A1 (en) Lateral semiconductor device having shallow trench isolation structure arranged in staggered and interdigital manner
CN108598166B (en) Depletion type enhanced integrated power device based on super junction self-isolation and manufacturing method
CN105097922A (en) Structure of SOI power LDMOS field effect transistor and manufacturing method thereof
KR20070032995A (en) High voltage device and method of forming the same
CN117542880B (en) Lateral double-diffusion field effect transistor, manufacturing method, chip and circuit
CN103311272B (en) There is the (Silicon-on-insulator) MOSFET lateral of dielectric isolation groove
CN108389895B (en) Super junction-based integrated power device and manufacturing method thereof
CN107546274B (en) LDMOS device with step-shaped groove
CN112993021B (en) Lateral double-diffusion metal oxide semiconductor field effect transistor
CN113078066A (en) Manufacturing method of split gate power MOSFET device
CN110600552B (en) Power semiconductor device with fast reverse recovery characteristic and manufacturing method thereof
CN111785774A (en) CMOS device in BCD process and manufacturing method thereof
CN111785637A (en) Fin type transistor with gate surrounding structure and manufacturing method thereof
CN112750911B (en) LDMOS with controllable three-dimensional electric field and preparation method thereof
CN115642182A (en) Transverse double-diffusion field effect transistor, manufacturing method, chip and circuit
CN115528115A (en) LDMOS power device and preparation method thereof
CN114695517A (en) Semiconductor device and method for manufacturing the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
CB02 Change of applicant information

Address after: 210003 Gulou District, Jiangsu, Nanjing new model road, No. 66

Applicant after: NANJING University OF POSTS AND TELECOMMUNICATIONS

Address before: Yuen Road Qixia District of Nanjing City, Jiangsu Province, No. 9 210046

Applicant before: NANJING University OF POSTS AND TELECOMMUNICATIONS

CB02 Change of applicant information
TA01 Transfer of patent application right

Effective date of registration: 20210428

Address after: Building 9 and 10, Yunyuan, No.33, Xinkang Road, Nantong City, Jiangsu Province, 226000

Applicant after: NANJING University OF POSTS AND TELECOMMUNICATIONS

Applicant after: NANJING UNIVERSITY OF POSTS AND TELECOMMUNICATIONS NANTONG INSTITUTE Co.,Ltd.

Address before: 210003 Gulou District, Jiangsu, Nanjing new model road, No. 66

Applicant before: NANJING University OF POSTS AND TELECOMMUNICATIONS

TA01 Transfer of patent application right
GR01 Patent grant
GR01 Patent grant