CN117614432B - Dynamic back gate control system for improving performance of bulk silicon LDMOS and manufacturing method of bulk silicon LDMOS - Google Patents
Dynamic back gate control system for improving performance of bulk silicon LDMOS and manufacturing method of bulk silicon LDMOS Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
- H03K17/6871—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors the output circuit comprising more than one controlled field-effect transistor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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Abstract
The invention provides a dynamic back gate control system for improving the performance of a bulk silicon LDMOS and a manufacturing method of the bulk silicon LDMOS, wherein the system comprises the bulk silicon LDMOS, and comprises a gate metal and a back gate metal; the dynamic back gate control circuit comprises a waveform generator, a three-level inverter, a negative voltage converter and a level converter which are electrically connected in sequence; the negative voltage converter comprises a negative voltage output end and a zero voltage output end; the negative voltage output end is connected with the first input end of the level converter, and the zero voltage output end is connected with the second input end of the level converter and grounded; the first output end of the level shifter is connected with the grid metal, and the second output end of the level shifter is connected with the back grid metal. The invention has independent back gate electrode, by applying bias on the derived back gate electrode, inducing interface charge, modulating the electric field distribution of the epitaxial layer, increasing the electric field of the internal leakage end, so as to improve breakdown voltage, and the drift region adopts heavy doping and has low specific on-resistance, thus improving the trade-off relationship between the two.
Description
Technical Field
The invention belongs to the technical field of semiconductor power devices, and particularly relates to a dynamic back gate control system for improving the performance of a bulk silicon LDMOS and a manufacturing method of the bulk silicon LDMOS.
Background
Bulk silicon LDMOS is used as a core device of a power integrated circuit, and a great deal of researches are carried out on the bulk silicon LDMOS by a plurality of researchers at home and abroad, and the researches mainly focus on how to improve the breakdown voltage of the bulk silicon LDMOS and reduce the specific on-resistance of the bulk silicon LDMOS.
Apples et al in document "HV THIN LAYER DEVICES" propose a technique of reducing the surface field (Reduce Surface Field, RESURF for short), which is one of the techniques commonly used in the design of devices with low-ratio on-resistance at high lateral voltages, which reduces the peak value of the electric field at the position where the n+/N-junction and the p+n-junction are formed on the surface of the device due to the mutual depletion action of the longitudinal N-P-junction formed between the epitaxial layer N and the village bottom P-sub, and allows the breakdown to occur by leading the originally smaller in-vivo longitudinal electric field peak value to reach an extreme value earlier than the surface electric field peak value during normal operation of the device, so that the originally breakdown point on the surface is turned to breakdown in the device, and the breakdown voltage is improved, however, in order to obtain the optimal breakdown voltage, the technique sacrifices a certain specific on-resistance, transconductance, saturation current and the like.
In response to this problem, guo Yufeng et al propose CN202111035555.6 an adaptive substrate voltage regulation circuit with optimized LDMOS performance, which improves the off-state breakdown voltage while ensuring the on-state performance unchanged, improving the trade-off relationship between the two, however, the SOI structure has no independent back gate electrode, and cannot perform better voltage regulation on the device.
Disclosure of Invention
The invention aims to provide a dynamic back gate control system for improving the performance of a bulk silicon LDMOS and a manufacturing method of the bulk silicon LDMOS, wherein the system is provided with an independent back gate electrode, and the breakdown voltage of a device is improved by applying bias on a derived back gate electrode, inducing interface charge and modulating the electric field distribution of an epitaxial layer. Meanwhile, as the drift region of the bulk silicon LDMOS is heavily doped, the performances of direct current, radio frequency and the like of the bulk silicon LDMOS can be improved. In order to achieve the above purpose, the following technical scheme is adopted:
A dynamic back gate control system that improves the performance of a bulk silicon LDMOS, comprising:
the body silicon LDMOS comprises a grid metal 13 and a back grid metal 14;
the dynamic back gate control circuit comprises a waveform generator 15, a three-level inverter 16, a negative voltage converter 17 and a level converter 18 which are electrically connected in sequence;
Wherein the negative voltage converter 17 comprises a negative voltage output terminal and a zero voltage output terminal; the level shifter 18 includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal;
the negative voltage output end is connected with the first input end of the level shifter 18, and the zero voltage output end is connected with the second input end of the level shifter 18 and grounded;
The first output end of the level shifter 18 is connected with the grid metal 13, and the second output end of the level shifter is connected with the back grid metal 14;
depending on the magnitude of the voltage applied to the gate 13 at the first output of the level shifter 18, the second output of the level shifter 18 applies a zero or negative voltage to the back gate metal 14.
Preferably, the bulk silicon LDMOS further comprises:
A substrate 1;
A well region 2 located in the substrate 1;
The epitaxial layer 3 is positioned on the upper surface of the well region 2 and comprises a source region 4, a body region 5, a channel region 6, a drift region 7, a drain region 8 and a back gate region 9;
Wherein the drift region 7 is positioned on the upper surface of the well region 2;
The back gate region 9, the body region 5 and the drain region 8 are all positioned on the drift region 7; the body region 5 is positioned between the back gate region 9 and the drain region 8;
the back gate region 9 and the body region 5 are both in contact with the upper surface of the drift region 7; the back gate region 9 and the drain region 8 are both in contact with the lower surface of the gate dielectric layer 10;
the source region 4 and the channel region 6 are positioned on the body region 5, and the source region 4 is arranged close to the back gate region 9; the inner side surface of the channel region 6 is in contact with the inner side surface of the source region 4;
The gate dielectric layer 10 is contacted with the top surfaces of the source region 4, the body region 5, the channel region 6, the drift region 7, the drain region 8 and the back gate region 9, and is provided with a source metal 11, a drain metal 12, the gate metal 13 and a back gate metal 14;
The source metal 11 is in contact with the top surfaces of the source region 4 and the channel region 6; the drain metal 12 is in contact with the top surface of the drain region 8;
A gate metal 13 is arranged above the body region 5 and the channel region 6; the back gate metal 14 is in contact with the top surface of the back gate region 9.
Preferably, the drift region 7 is heavily doped.
Preferably, the waveform generator 15 includes:
the positive input end of the comparator I is connected with the reference voltage, the negative input end of the comparator I is connected with the positive input end of the first capacitor C1 and the comparator II, and the output end of the comparator I is connected with the first resistor R1, the second resistor R2 and the third resistor R3;
the other end of the second resistor R2 is connected with a first capacitor C1; the first capacitor C1 is grounded;
The positive input end of the second comparator is connected with the negative input end of the first comparator and the first capacitor C1, the negative input end of the second comparator is connected with the reference voltage, and the output end of the second comparator is connected with the fourth resistor R4 and the three-level inverter 16;
the other end of the fourth resistor R4 is connected with a main power supply VDD;
a voltage stabilizer is arranged between the first resistor R1 and the fourth resistor R4.
Preferably, the three-level inverter 16 includes:
the source electrode of the PMOS tube is connected with the main power supply VDD, the drain electrode of the PMOS tube is connected with the drain electrode of the NMOS tube, and the grid electrode of the PMOS tube is connected with the output end of the comparator II of the waveform converter;
and the source electrode of the NMOS tube is grounded, the drain electrode of the NMOS tube is connected with the drain electrode of the PMOS tube, and the grid electrode of the NMOS tube is connected with the output end of the comparator II of the waveform converter.
Preferably, the negative voltage converter 17 includes:
The anode of the second capacitor C2 is connected with the three-level inverter 16, and the cathode of the second capacitor C2 is connected with the cathode of the first diode D1 and the anode of the second diode D2;
the anode of the first diode D1 is connected with the cathode of the third capacitor C3 and the negative voltage output end;
the cathode of the second diode D2 is connected with the anode of the third capacitor C3, the zero voltage output end and the ground; the zero voltage output terminal is grounded.
A manufacturing method of a bulk silicon LDMOS comprises the following steps:
Step1, ion implantation is carried out on a substrate 1 to form a well region 2;
step 2, ion implantation is carried out on the well region 2 for a plurality of times to form an epitaxial layer 3;
Step 3, growing an oxide layer on the epitaxial layer 3 to form a gate dielectric layer 10;
and 4, etching a contact groove on the gate dielectric layer 10 to form a preset position, and arranging a source electrode metal 11, a drain electrode metal 12, a gate electrode metal 13 and a back gate metal 14 on the preset position.
Compared with the prior art, the invention has the advantages that:
1. the independent back gate lead-out structure can better regulate the performance of each device in the circuit. Compared with the traditional LDMOS device, the device has a separate back gate electrode, and the interface charge is induced by applying negative voltage on the derivative back gate electrode, so that the electric field distribution of the epitaxial layer 3 is modulated, and the electric field of the internal drain terminal is increased.
When negative voltage is applied to the back gate electrode, interface charge can be induced, and the electric field of the source end of the body is improved, so that the longitudinal withstand voltage limit of a conventional structure is broken through, the potential is effectively regulated, and the breakdown voltage of the device is improved.
The drift region of the semiconductor device is heavily doped, so that the semiconductor device has low specific on-resistance, and the compromise relationship between the drift region and the drift region is improved.
2. Compared with the traditional bulk silicon LDMOS, the drift region is heavily doped, so that the on-resistance is reduced, and the transconductance and the cut-off frequency are improved.
3. The circuit is simple, the technology can be realized by using a conventional CMOS process, no extra process flow is needed, and the preparation is simple and the cost is low.
Drawings
FIG. 1 is a three-dimensional block diagram of a dynamic back gate control system that improves the performance of bulk silicon LDMOS;
FIG. 2 is a two-dimensional block diagram of a bulk silicon LDMOS with a back-gate electrode;
FIG. 3 is a schematic diagram of an embodiment of a dynamic back gate control circuit;
FIG. 4 is a graph showing a two-dimensional potential distribution diagram of a bulk silicon LDMOS breakdown using conventional techniques;
FIG. 5 is a graph of two-dimensional potential distribution of a bulk silicon LDMOS breakdown using the technique of the present invention;
FIG. 6 is a graph showing the electric field distribution of a bulk silicon LDMOS using conventional techniques and the present invention technique, respectively;
FIG. 7 is a graph showing the variation of the breakdown voltage and specific on-resistance of a bulk silicon LDMOS with the concentration of a drift region;
FIG. 8 is a graph showing the breakdown voltage of a bulk silicon LDMOS as a function of the back-gate voltage;
FIG. 9 is a graph showing output characteristics of a bulk silicon LDMOS employing conventional techniques and the present invention technique, respectively;
Fig. 10 is a graph of percentage improvement in bulk silicon LDMOS performance using the technique of the present invention.
The semiconductor device comprises a 1-substrate, a 2-well region, a 3-epitaxial layer, a 4-source region, a 5-body region, a 6-channel region, a 7-drift region, an 8-drain region, a 9-back gate region, a 10-gate dielectric layer, 11-source metal, 12-drain metal, 13-gate metal, 14-back gate metal, a 15-waveform generator, a 16-three-level inverter, a 17-negative voltage converter and an 18-level converter.
Description of the embodiments
The dynamic back-gate control system for improving the performance of a bulk silicon LDMOS and the method of fabricating a bulk silicon LDMOS of the present invention will be described in more detail below with reference to the drawings, wherein preferred embodiments of the present invention are shown, it being understood that one skilled in the art may modify the invention described herein while still achieving the advantageous effects of the invention. Accordingly, the following description is to be construed as broadly known to those skilled in the art and not as limiting the invention.
As shown in fig. 1-2, the dynamic back gate control system for improving the performance of the bulk silicon LDMOS comprises a bulk silicon LDMOS and a dynamic back gate control circuit.
The dynamic back gate control circuit can control the voltage of the independent back gate electrode of the bulk silicon LDMOS. Compared with a conventional device, the body silicon LDMOS has the advantages of improving breakdown voltage, reducing specific on-resistance, improving the compromise relationship between the body silicon LDMOS and the specific on-resistance, and improving the performances of direct current, radio frequency, switch and the like of the body silicon LDMOS.
The independent back gate leading-out structure can better regulate the performance of each device in the circuit. Compared with the traditional LDMOS device, the device has a separate back gate electrode, and the interface charge is induced by applying negative voltage on the derivative back gate electrode, so that the electric field distribution of the epitaxial layer 3 is modulated, and the electric field of the internal drain terminal is increased. As shown in fig. 5-6.
When negative voltage is applied to the back gate electrode, interface charge can be induced, and the electric field of the source end of the body is improved, so that the longitudinal withstand voltage limit of a conventional structure is broken through, the potential is effectively regulated, and the breakdown voltage of the device is improved.
When the device is in an on state, the back gate electrode is not applied with voltage, so that the body silicon LDMOS is not affected, and the on-resistance of the drift region of the device is obviously lower than that of the traditional technology because the drift region of the device is heavily doped.
The body silicon LDMOS comprises a substrate 1, a well region 2, an epitaxial layer 3, a gate dielectric layer 10, a source metal 11, a drain metal 12, a gate metal 13 and a back gate metal 14.
The substrate 1 is a semiconductor and is lowermost.
Well region 2 is located in substrate 1. The well region 2 functions as: the back gate electrode may be provided independently, with the electrodes being independent.
The epitaxial layer 3 is positioned on the upper surface of the well region 2 and comprises a source region 4, a body region 5, a channel region 6, a drift region 7, a drain region 8 and a back gate region 9; the drift region 7 is heavily doped.
Specifically, the drift region 7 is located on the upper surface of the well region 2.
The back gate region 9, the body region 5 and the drain region 8 are all located on the drift region 7. The body region 5 is located between the back gate region 9 and the drain region 8.
The back gate region 9 and the body region 5 are both in contact with the upper surface of the drift region 7; the back gate region 9 and the drain region 8 are both in contact with the lower surface of the gate dielectric layer 10.
Source region 4 and channel region 6 are located on body region 5, source region 4 being located adjacent back gate region 9, the inner side of channel region 6 being in contact with the inner side of source region 4. In fig. 1, the boundary between the source region 4 and the channel region 6 is not shown.
In this embodiment, the "inner side" is the "outer side" with respect to the side outside the bulk silicon LDMOS, i.e., the side near the outside of the bulk silicon LDMOS, and the side near the inside of the silicon LDMOS is the "inner side".
The gate dielectric layer 10 is simultaneously in contact with the top surfaces of the source region 4, the body region 5, the channel region 6, the drift region 7, the drain region 8 and the back gate region 9.
A source metal 11, a drain metal 12, a gate metal 13 and a back gate metal 14 are disposed on the gate dielectric layer 10.
Source metal 11 (corresponding to voltage V s) is in contact with the top surfaces of source region 4 and channel region 6; the drain metal 12 (corresponding to voltage V D) is in contact with the top surface of the drain region 8.
Gate metal 13 (corresponding to voltage V G) is placed over body region 5, channel region 6 and is not in contact; the back gate metal 14 (corresponding to voltage V BG) is in contact with the top surface of the back gate 9.
In particular, the well region 2 of the bulk silicon LDMOS must be deep and the back-gate electrode (back-gate metal 14) must be located far from the source (source metal 11).
The reason why the depth of the well region of the bulk silicon LDMOS is larger is that: if the depth of the p-well is too shallow, the probability of meeting electrons and holes in the channel region is increased, electron-hole pairs are easily formed, the depletion region is out of control, the rate of meeting electrons and holes in the p-well is excessively high, a punch-through effect is formed, and the performance of the bulk silicon LDMOS is reduced.
However, if the depth of the p-well is deep enough, the probability of meeting electrons and holes in the channel region is reduced, and the formation of a depletion region is more stable, so that the reliability and the working efficiency of the bulk silicon LDMOS are improved.
The reason why the back gate electrode is disposed far from the source is that: the effect of the source current on the device can be reduced.
In summary, the well region of the bulk-silicon LDMOS must be deep, and the back-gate electrode must be located far from the source, so as to improve the performance and reliability of the bulk-silicon LDMOS and reduce the influence of the source-drain current on the bulk-silicon LDMOS.
Wherein the substrate 1 is made of a semiconductor material. The individual layers or regions of the semiconductor body silicon LDMOS may be composed of materials known to those skilled in the art. Semiconductor materials include, for example, group III-V semiconductors such as gallium arsenide, gallium nitride, silicon carbide, and group IV semiconductors such as silicon, germanium. The gate conductor, electrode layer may be formed of various conductive materials such as a metal layer, a doped polysilicon layer, or other conductive materials such as tantalum carbide, shackle, tungsten, and combinations thereof.
As shown in fig. 1-2, the dynamic back gate control circuit is provided with a voltage supplied by a main power supply VDD, and includes a level shifter 18, a waveform generator 15, a three-level inverter 16 and a negative voltage shifter 17.
A first output terminal of the level shifter 18 is connected to the gate metal 13;
A second output of the level shifter 18 is connected to the back gate metal 14;
The first input end of the level shifter 18 is connected to the negative voltage output end of the negative voltage shifter 17, and the second input end thereof is connected to the zero voltage output end of the negative voltage shifter 17.
The output end of the waveform generator 15 is connected with the input end of the three-level inverter 16, and the output end of the three-level inverter 16 is connected with the input end of the negative voltage converter 17.
The manufacturing method of the bulk silicon LDMOS with the back gate electrode specifically comprises the following steps:
Step1, ion implantation is carried out on a substrate 1 to form a well region 2;
Step 2, performing ion implantation on the well region 2 for a plurality of times to form an epitaxial layer 3 (a source region 4, a body region 5, a channel region 6, a drift region 7, a drain region 8 and a back gate region 9);
Step 3, growing an oxide layer on the epitaxial layer 3 to form a gate dielectric layer 10;
and 4, etching a contact groove on the gate dielectric layer 10 to form a preset position, and arranging a source electrode metal 11, a drain electrode metal 12, a gate electrode metal 13 and a back gate metal 14 on the preset position.
The embodiment controls the back-gate voltage V BG of the bulk silicon LDMOS by implementing a dynamic back-gate control circuit.
Action of the waveform generator 15: outputting square wave signals. Specifically, the basic characteristics of the comparator are utilized to charge and discharge the capacitor, triangular waves are generated, and then square wave signals are output by utilizing the characteristics of the comparator that the comparator is opened and leaked.
Function of three-level inverter 16: the direct-current voltage can be converted into alternating-current voltage by controlling the on and off of the switching tube, and zero-point voltage and negative voltage can be generated, so that the requirement of negative voltage output is met;
The function of the negative voltage converter 17: the negative voltage output can be realized, the output voltage and the waveform can be controlled, and the output voltage quality can be improved.
The function of the level shifter 18: the signal level of one circuit is converted into the signal level required by the other circuit to adapt to the circuits of different levels, prevent signal loss, enhance the transmission distance of signals and save the cost of the interface circuit.
Depending on the magnitude of the voltage applied to the gate 13 at the first output of the level shifter 18 (greater or less than the threshold voltage of the bulk silicon LDMOS), the second output of the level shifter 18 is selected to output either a zero voltage or a negative voltage.
As shown in fig. 3, the specific structure of the dynamic back gate control circuit is as follows:
The waveform generator 15 includes two comparators, four resistors, and a capacitor.
The waveform generator 15 charges and discharges the capacitor by utilizing the basic characteristic of the comparator to generate triangular waves, and outputs square wave signals by utilizing the characteristic of open-drain output of the comparator;
the positive input end of the comparator I is connected with the reference voltage, the negative input end of the comparator I is connected with the positive electrode of the first capacitor C1 and the positive input end of the comparator II, and the output end of the comparator I is connected with the first resistor R1, the second resistor R2 and the third resistor R3.
The other end of the second resistor R2 is connected with the anode of the first capacitor C1. The negative electrode of the first capacitor C1 is grounded.
The positive input end of the second comparator is connected with the negative input end of the first comparator and the positive electrode of the first capacitor C1, the negative input end of the second comparator is connected with the reference voltage, and the output end of the second comparator is connected with the fourth resistor R4 and the three-level inverter 16.
The other end of the fourth resistor R4 is connected with the main power supply VDD.
A voltage stabilizer is arranged between the first resistor R1 and the fourth resistor R4.
The three-level inverter 16 includes a PMOS transistor and an NMOS transistor.
The source electrode of the PMOS tube (MP 1) is connected with the main power supply VDD, the drain electrode is connected with the drain electrode of the NMOS tube, and the grid electrode is connected with the second output end of the comparator of the waveform converter;
The source electrode of the NMOS tube (MN 1) is grounded, the drain electrode is connected with the drain electrode of the PMOS tube, and the grid electrode is connected with the second output end of the comparator of the waveform converter.
The negative voltage converter 17 includes two capacitors, two diodes.
The positive electrode of the second capacitor C2 is connected to the drain electrode of the three-level inverter 16, and the negative electrode is connected to the negative electrode of the first diode D1 and the positive electrode of the second diode D2.
The anode of the diode D1 is connected to the cathode of the third capacitor C3 and the negative voltage output end (one output end of the negative voltage converter 17), and the cathode of the diode D2 is connected to the anode of the third capacitor C3 and the zero voltage output end (the other output end of the negative voltage converter 17) and grounded.
The zero voltage output terminal is grounded.
The negative voltage output is based on the charge pump principle: the square wave forming high-low level conversion is generated by the waveform generator 15 and output to the three-level inverter 16, and then the charging and discharging process switching of the switched capacitor network is realized by control, so that the negative voltage converter 17 obtains a stable output negative voltage.
The level shifter 18 has two different inputs, zero voltage (second input output) and negative voltage (first input output), respectively.
There are two outputs, one end to which the gate metal is connected (first output) and one end to which the back gate electrode is connected (second output), respectively, and therefore two cases need to be considered:
Case 1 when the gate voltage V G is less than the threshold voltage, the back-gate voltage V BG of the bulk-silicon LDMOS is a negative voltage.
Case 2 when the gate voltage V G is greater than the threshold voltage, the back-gate voltage V BG of the bulk-silicon LDMOS is zero.
One end (a first output end) of the level shifter 18 connected with the gate metal 13 outputs a square wave, and when the gate voltage is greater than the threshold voltage, the bulk silicon LDMOS is turned on, i.e. the bulk silicon LDMOS is in an on state; when the gate voltage is less than the threshold voltage, the bulk silicon LDMOS is turned off, i.e., the bulk silicon LDMOS is in an off state.
One end (second output end) of the level shifter connected with the back gate metal outputs the rule: when the body silicon LDMOS is in an off state, a negative voltage is output, and when the body silicon LDMOS is in an on state, a zero voltage is output.
The dynamic back gate control system for improving the performance of the bulk silicon LDMOS has the working principle that:
when the comparator outputs a high level, the current passes through the first resistor R1 and the third resistor R3 to charge the first capacitor C1 through the second resistor R2.
When the level output is low, the first capacitor C1 discharges through the second resistor R2.
The second output square wave of the comparator drives the p-channel mos transistor MP1 and the n-channel mos transistor MN1 to charge and discharge to the second capacitor C2. Specifically:
When the square wave output by the second comparator is at a low level, the p-channel mos transistor MP1 is conducted to charge the second capacitor C2, and the left side, the right side and the left side are conducted to 0V through the diode D2.
When the square wave output by the second comparator is at a high level, the n-channel mos tube MN1 is conducted, and the first diode D1 generates negative 15V voltage after reversing because the capacitance energy of the second capacitor C2 cannot be suddenly changed.
(1) When the bulk silicon LDMOS is in an off state, i.e. the gate voltage is less than the threshold voltage, the back gate voltage is the negative output voltage of the level shifter, and negative charge is induced by applying the negative voltage to the back gate to compensate for the heavily doped ionized acceptor in the drift region, the breakdown voltage of the structure is higher than that of the conventional technology.
(2) When the body silicon LDMO is in an on state, namely the grid voltage is greater than the threshold voltage, the back grid voltage is zero voltage of the level converter, the back grid voltage does not affect the device, and the on resistance is obviously lower than that of the traditional technology due to the adoption of heavy doping in the drift region. Therefore, the technology can realize the compromise of breakdown voltage and on-resistance, and has low specific on-resistance, large saturation current, high transconductance, high cut-off frequency and the like compared with the traditional technology.
CN202310208764.9 is a back gate assisted RESURF system based on a double SOI structure, which has a back gate electrode but which uses buried oxide layer materials, such as silicon dioxide, for isolation, which can affect charge flow and thus device impact, such as threshold voltage, etc.
The technology can reduce specific on-resistance while increasing breakdown voltage, and improves the trade-off relationship between breakdown voltage and on-resistance. In addition, the body silicon LDMOS has an independent back gate lead-out structure, and can better adjust the breakdown voltage, specific on-resistance and other performances of each device in the circuit.
To demonstrate the beneficial effects of embodiments of the present invention, FIGS. 4-10 analyze the structure of the present invention and the conventional structure.
Fig. 4 and 5 show two-dimensional potential profiles for bulk silicon LDMOS breakdown using conventional techniques and using the techniques of the present invention, respectively. As can be seen from the figure, after the back gate voltage is applied to the bulk silicon LDMOS adopting the technology, the potential lines of the drift region are distributed more densely, so that the breakdown voltage of the bulk silicon LDMOS adopting the technology is slightly higher than that of the conventional technology.
Fig. 6 shows electric field distribution diagrams of bulk silicon LDMOS using conventional technology and the technology of the present invention, respectively, in which the electric field strength using the technology of the present invention is higher than that using the conventional technology.
Fig. 7 is a graph showing the variation trend of the breakdown voltage and the specific on-resistance of the bulk silicon LDMOS with the drift region concentration according to the conventional technology, and it can be seen from the graph that the breakdown voltage reaches the maximum value 46.85 when the drift region concentration is 2.5E16 th power, and the specific on-resistance is 0.67. 0.67 m Ω ∙ cm 2.
Fig. 8 is a graph showing the variation trend of the bulk silicon LDMOS breakdown voltage with the back gate voltage, and it can be seen that when the back gate voltage V BG reaches-15V, the breakdown voltage can reach 51V, and because the drift region concentration is 4.5E16, the on-resistance is 0.41 m Ω ∙ cm 2 as shown in fig. 7, therefore, compared with the bulk silicon LDMOS breakdown voltage of the conventional technology, the on-resistance is improved by 8.23%, and the on-resistance is reduced by 38.8%.
Fig. 9 shows a graph of bulk-silicon LDMOS output characteristics comparing device performance using conventional techniques and the inventive technique. When the gate voltage V G =3v, the saturation current of the bulk silicon LDMOS adopting the technology of the invention is increased by 390.62%, reaching 58.63 μa, while the saturation current of the bulk silicon LDMOS adopting the conventional technology is only 11.95 μa. Therefore, under the same condition, the device adopting the technology of the invention has larger on-current.
Fig. 10 is a graph of percentage improvement of performance of a bulk silicon LDMOS adopting the technology of the invention, which is obtained by TCAD simulation tools, and it can be seen from the graph that the breakdown voltage of the bulk silicon LDMOS adopting the technology of the invention is improved by 8.23%, the specific on-resistance is reduced by 38.8%, the transconductance is improved by 26.29%, the cut-off frequency is improved by 35.4%, and the FOM value is improved by 100% compared with that of the bulk silicon LDMOS adopting the conventional technology.
The foregoing is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any person skilled in the art will make any equivalent substitution or modification to the technical solution and technical content disclosed in the invention without departing from the scope of the technical solution of the invention, and the technical solution of the invention is not departing from the scope of the invention.
Claims (7)
1. A dynamic back gate control system for improving the performance of a bulk silicon LDMOS, comprising:
The body silicon LDMOS comprises a grid metal (13) and a back grid metal (14);
the dynamic back gate control circuit comprises a waveform generator (15), a three-level inverter (16), a negative voltage converter (17) and a level converter (18) which are electrically connected in sequence;
Wherein the negative voltage converter (17) comprises a negative voltage output and a zero voltage output; the level shifter (18) comprises a first input terminal, a second input terminal, a first output terminal and a second output terminal;
the negative voltage output end is connected with the first input end of the level converter (18), and the zero voltage output end is connected with the second input end of the level converter (18) and grounded;
the first output end of the level shifter (18) is connected with the grid metal (13), and the second output end of the level shifter is connected with the back grid metal (14);
the second output of the level shifter (18) applies a zero or negative voltage to the back gate metal (14) depending on the magnitude of the voltage applied to the gate (13) at the first output of the level shifter (18).
2. The dynamic back-gate control system of claim 1, wherein the bulk-silicon LDMOS further comprises:
A substrate (1);
A well region (2) located in the substrate (1);
The epitaxial layer (3) is positioned on the upper surface of the well region (2) and comprises a source region (4), a body region (5), a channel region (6), a drift region (7), a drain region (8) and a back gate region (9);
wherein the drift region (7) is positioned on the upper surface of the well region (2);
The back gate region (9), the body region (5) and the drain region (8) are all positioned on the drift region (7); the body region (5) is positioned between the back gate region (9) and the drain region (8);
The back gate region (9) and the body region (5) are both contacted with the upper surface of the drift region (7); the back gate region (9) and the drain region (8) are both contacted with the lower surface of the gate dielectric layer (10);
The source region (4) and the channel region (6) are positioned on the body region (5), and the source region (4) is close to the back gate region (9); the inner side surface of the channel region (6) is contacted with the inner side surface of the source region (4);
The gate dielectric layer (10) is simultaneously contacted with the top surfaces of the source region (4), the body region (5), the channel region (6), the drift region (7), the drain region (8) and the back gate region (9), and a source metal (11), a drain metal (12), the gate metal (13) and a back gate metal (14) are arranged on the gate dielectric layer;
The source metal (11) is contacted with the top surfaces of the source region (4) and the channel region (6); the drain metal (12) is in contact with the top surface of the drain region (8);
the grid metal (13) is arranged above the body region (5) and the channel region (6); the back gate metal (14) is in contact with the top surface of the back gate region (9).
3. Dynamic back-gate control system to improve the performance of bulk-silicon LDMOS according to claim 2 characterized in that the drift region (7) is heavily doped.
4. The dynamic back gate control system of claim 1, wherein the waveform generator (15) comprises:
the positive input end of the comparator I is connected with the reference voltage, the negative input end of the comparator I is connected with the positive input end of the first capacitor C1 and the comparator II, and the output end of the comparator I is connected with the first resistor R1, the second resistor R2 and the third resistor R3;
the other end of the second resistor R2 is connected with a first capacitor C1; the first capacitor C1 is grounded;
The positive input end of the comparator II is connected with the negative input end of the comparator I and the first capacitor C1, the negative input end of the comparator II is connected with the reference voltage, and the output end of the comparator II is connected with the fourth resistor R4 and the three-level inverter (16);
the other end of the fourth resistor R4 is connected with a main power supply VDD;
a voltage stabilizer is arranged between the first resistor R1 and the fourth resistor R4.
5. The dynamic back gate control system for improving the performance of a bulk silicon LDMOS as recited in claim 1 wherein said three-level inverter (16) comprises:
the source electrode of the PMOS tube is connected with the main power supply VDD, the drain electrode of the PMOS tube is connected with the drain electrode of the NMOS tube, and the grid electrode of the PMOS tube is connected with the output end of the comparator II of the waveform converter;
and the source electrode of the NMOS tube is grounded, the drain electrode of the NMOS tube is connected with the drain electrode of the PMOS tube, and the grid electrode of the NMOS tube is connected with the output end of the comparator II of the waveform converter.
6. Dynamic back-gate control system to improve the performance of bulk-silicon LDMOS according to claim 1, characterized in that the negative voltage converter (17) comprises:
The anode of the second capacitor C2 is connected with the three-level inverter (16), and the cathode of the second capacitor C is connected with the cathode of the first diode D1 and the anode of the second diode D2;
the anode of the first diode D1 is connected with the cathode of the third capacitor C3 and the negative voltage output end;
the cathode of the second diode D2 is connected with the anode of the third capacitor C3, the zero voltage output end and the ground; the zero voltage output terminal is grounded.
7. A method for manufacturing a bulk silicon LDMOS based on the dynamic back gate control system for improving the performance of the bulk silicon LDMOS according to any of claims 1 to 6, comprising the steps of:
step 1, performing ion implantation on a substrate (1) to form a well region (2);
step 2, ion implantation is carried out on the well region (2) for a plurality of times to form an epitaxial layer (3);
step 3, growing an oxide layer on the epitaxial layer (3) to form a gate dielectric layer (10);
and 4, etching a contact groove on the gate dielectric layer (10) to form a preset position, and arranging a source electrode metal (11), a drain electrode metal (12), a gate electrode metal (13) and a back gate metal (14) on the preset position.
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