CN111244032A - Manufacturing method of semiconductor device and semiconductor device - Google Patents
Manufacturing method of semiconductor device and semiconductor device Download PDFInfo
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- CN111244032A CN111244032A CN202010232317.3A CN202010232317A CN111244032A CN 111244032 A CN111244032 A CN 111244032A CN 202010232317 A CN202010232317 A CN 202010232317A CN 111244032 A CN111244032 A CN 111244032A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
Abstract
The application provides a manufacturing method of a semiconductor device and the semiconductor device. The method comprises the following steps: providing a substrate with an insulating medium layer; forming a metal connecting line layer on the surface of the insulating medium layer; etching at least part of the metal connecting line layer, forming a plurality of filling grooves at least in the metal connecting line layer, wherein metal connecting lines are arranged on two sides of the filling grooves; at least part of the filling groove is filled with a medium to form a medium part. According to the method, the metal connecting line part is formed by deposition and etching, and due to the fact that the deposited width is relatively large, holes are not easy to generate in the deposition process, and the formed structural layer is compact. Therefore, compared with the prior art that the metal is filled in the groove to form the metal connecting part, the method reduces the probability of generating holes in the metal connecting part, and further improves the electric mobility, thereby improving the performance of the device.
Description
Technical Field
The present disclosure relates to the field of semiconductors, and in particular, to a method for manufacturing a semiconductor device and a semiconductor device.
Background
In the prior art, a process for forming a metal line in a semiconductor device generally includes: generally, an isolation dielectric layer is firstly arranged on a substrate, then the isolation dielectric layer and an insulation dielectric layer of the substrate are etched to form a groove, and then metal is filled in the groove to form a metal wire. However, as the number of layers of the device is increased in multiples, the spacing between the metal lines is smaller and smaller, so that the filling process is more and more difficult, holes are easily generated, the electric mobility is reduced, and the performance of the device is poor or even fails. In particular, in a three-dimensional memory (3D NAND), voids may cause exponential deterioration in resistance-capacitance (RC) delay of a device, thereby causing a response speed of the device to be slow.
The above information disclosed in this background section is only for enhancement of understanding of the background of the technology described herein and, therefore, certain information may be included in the background that does not form the prior art that is already known in this country to a person of ordinary skill in the art.
Disclosure of Invention
The present disclosure provides a method for manufacturing a semiconductor device and a semiconductor device, so as to solve the problem that a hole is easily generated in a metal connection portion formed by a filling process in the prior art.
In order to achieve the above object, according to an aspect of the present application, there is provided a method of manufacturing a semiconductor device, the method including: providing a substrate with an insulating medium layer; forming a metal connecting line layer on the surface of the insulating medium layer; etching at least part of the metal connecting line layer, forming a plurality of filling grooves at least in the metal connecting line layer, wherein metal connecting lines are arranged on two sides of the filling grooves; and filling a medium in at least part of the filling groove to form a medium part.
Further, at least etching away part of the metal connecting line layer, and forming a plurality of filling grooves in at least the metal connecting line layer, including: and sequentially removing part of the insulating medium layer and the metal connecting line layer, and forming a plurality of filling grooves in the insulating medium layer and the metal connecting line layer.
Further, after forming the plurality of spaced metal wire portions and before forming the dielectric portion, the method further includes: forming a barrier layer at least on the inner wall of the filling groove, filling a medium in at least part of the filling groove, and forming a medium part, wherein the method comprises the following steps: and filling the remaining part of the filling groove with a medium to form the medium part.
Further, filling a dielectric in at least a part of the filling groove to form a dielectric part, including: and forming a capping layer at least above the filling groove, wherein the capping layer and the inner wall of the filling groove form a closed space, and the closed space is provided with air.
Further, forming a capping layer at least in a remaining portion of the fill trench, comprising: and forming the capping layer in the rest part of the filling groove and on the metal connecting parts at two sides of the filling groove.
Further, the material of the capping layer comprises a silicon-oxygen compound and/or a silicon-nitrogen compound.
Further, the material of the metal wiring layer comprises at least one of copper, tungsten, cobalt, ruthenium, molybdenum, osmium and iridium.
In order to achieve the above object, according to one aspect of the present application, there is provided a semiconductor device including: a substrate having an insulating dielectric layer; the metal connecting lines are positioned on the insulating medium layer, a space is formed between any two metal connecting lines, at least part of the space forms a filling groove, and the metal connecting lines are formed by etching; a dielectric portion in at least part of the filling groove
Furthermore, the insulating medium layer is provided with a plurality of grooves, the metal connecting line is positioned on the insulating medium layer at two sides of the grooves, the interval is positioned above the grooves, and at least part of the interval and at least part of the grooves form the filling grooves.
Further, the semiconductor device further includes: and the barrier layer is at least positioned between the side wall of the metal wire part and the medium part.
Further, the medium part includes: air located in the filling groove; and the top sealing layer and the inner wall of the filling groove form a closed space, and the air is positioned in the closed space.
Further, the material of the capping layer comprises a silicon-oxygen compound and/or a silicon-nitrogen compound.
According to the technical scheme, in the manufacturing method, a metal connecting line layer is formed on a substrate with an insulating medium layer, then a plurality of filling grooves are formed in the metal connecting line layer at least through etching, so that two sides of each filling groove are respectively provided with one metal connecting line part, and finally, at least part of each filling groove is filled with a medium to form a medium part. According to the method, the metal connecting line part is formed by deposition and etching, and due to the fact that the deposited width is relatively large, holes are not easy to generate in the deposition process, and the formed structural layer is compact. Therefore, compared with the prior art that the metal connecting part is formed by filling metal in the groove, the method reduces the probability of generating holes in the metal connecting part, and further improves the electric mobility, so that the performance of the device is improved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:
fig. 1 shows a flow diagram of a method of fabricating a semiconductor device according to an embodiment of the present application;
FIG. 2 shows a schematic view of a substrate comprising an insulating dielectric layer according to an embodiment of the present application;
FIG. 3 is a schematic view showing a metal wiring layer formed on the surface of the insulating dielectric layer of FIG. 2;
FIG. 4 is a schematic diagram showing a filled trench formed by etching away a portion of the insulating dielectric layer and the metal wiring layer in the structure of FIG. 3;
FIG. 5 shows a schematic diagram of the formation of a barrier layer in the structure of FIG. 4; and
fig. 6 shows a schematic diagram of the formation of a capping layer in the structure of fig. 5.
Wherein the figures include the following reference numerals:
10. a substrate; 11. an insulating dielectric layer; 20. a metal wiring layer; 21. a metal wiring portion; 30. filling the groove; 40. a barrier layer; 50. sealing the top layer; 60. and (4) closing the space.
Detailed Description
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Also, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.
As mentioned in the background, the filling process in the prior art is prone to generate voids in the metal connecting portion, and in order to solve the above technical problems, in an exemplary embodiment of the present application, a method for manufacturing a semiconductor device and a semiconductor device are provided.
According to an embodiment of the present application, there is provided a method for manufacturing a semiconductor device, as shown in fig. 1, the method including the steps of:
step S101, providing a substrate 10 with an insulating medium layer 11, as shown in FIG. 2;
step S102, forming a metal interconnection layer 20 on the surface of the insulating dielectric layer 11, as shown in fig. 3;
step S103, etching at least a portion of the metal interconnection layer 20, forming a plurality of filling grooves 30 in at least the metal interconnection layer 20, wherein metal interconnection portions 21 are disposed on two sides of the filling grooves 30, as shown in fig. 4;
in step S104, a dielectric is filled in at least a part of the filling groove 30 to form a dielectric portion, as shown in fig. 6.
In the manufacturing method, a metal connecting line layer is formed on a substrate with an insulating medium layer, then a plurality of filling grooves are formed in the metal connecting line layer at least through etching, so that two sides of each filling groove are respectively provided with a metal connecting line part, and finally, at least part of each filling groove is filled with a medium to form a medium part. According to the method, the metal connecting line part is formed by deposition and etching, and due to the fact that the deposited width is relatively large, holes are not easy to generate in the deposition process, and the formed structural layer is compact. Therefore, compared with the prior art that the metal connecting part is formed by filling metal in the groove, the method reduces the probability of generating holes in the metal connecting part, and further improves the electric mobility, so that the performance of the device is improved.
In an embodiment of the present application, at least etching away a portion of the metal interconnect layer to form a plurality of filling grooves in the metal interconnect layer includes: a part of the insulating dielectric layer 11 and the metal interconnection layer 20 are sequentially removed, and a plurality of the filling grooves 30 are formed in the insulating dielectric layer 11 and the metal interconnection layer 20, as shown in fig. 4. Specifically, the method forms the filling groove 30 by etching the insulating dielectric layer 11 and the metal wiring layer 20, and forms the spaced metal wiring parts 21. The specific etching process may be determined according to actual conditions, for example, the specific etching process may be determined according to a specific material of the insulating dielectric layer, a specific material of the metal wiring layer, a specific thickness of the insulating dielectric layer, a specific thickness of the metal wiring layer, a specific width of a portion to be etched and removed, and the like, and includes the specific process, corresponding steps, time, and the like. The process may specifically adopt dry etching or wet etching, and those skilled in the art can select a specific etching process according to actual conditions.
In an embodiment of the present application, after forming the plurality of spaced metal wire portions 21 and before forming the dielectric portion, the manufacturing method further includes: a barrier layer 40 is formed at least on the inner wall of the filled trench. In the actual process, a barrier layer 40 may also be formed on the exposed surface of the metal wire portion, as shown in fig. 5. Filling at least a part of the filling groove 30 with a medium to form a medium part, including: the remaining part of the filling groove 30 is filled with a medium to form the medium portion. The barrier layer 40 can prevent the metal of the metal wire part from diffusing to other areas, thereby further ensuring that the device has good electrical performance.
Specifically, the formation process of the barrier layer may be determined according to actual conditions, such as the material and thickness of the barrier layer.
In order to further ensure that the barrier layer has a good diffusion-preventing effect on the metal, in an embodiment of the present application, the material of the barrier layer is a material with a uniform filling property and a good high barrier property, and specifically may be one or more of aluminum nitride, aluminum oxide, and hafnium oxide.
In an embodiment of the present application, a dielectric is filled in at least a part of the filling groove to form a dielectric portion, including: a capping layer 50 is formed at least above the filling groove 30, and the capping layer 50 and the inner wall of the filling groove 30 form a closed space 60, and the closed space 60 contains air, as shown in fig. 6. The air bubble with the lowest dielectric constant is selected to replace the isolation dielectric layer in the prior art, so that the capacitance is minimized, the dielectric breakdown is reduced, and the device has better electrical performance
Of course, the gas in the enclosed space is not limited to air, and may be other inert gases (herein, broadly, inert gases), such as nitrogen, etc. If other inert gases are in the enclosed space, in the actual process, the filling groove needs to be filled with the corresponding inert gases, which is complicated in process. Therefore, the most economical way is to fill the enclosed space with air, so that no additional process filling is needed in the manufacturing process, and no material cost is increased, because the air is filled in the groove.
The filling grooves are filled with the gas medium, so that the dielectric part between the metal connecting wire parts is further prevented from being broken down, and the reliability of the device is improved.
In one embodiment of the present application, forming a capping layer at least in the remaining portion of the filling trench includes: the capping layer 50 is formed on the metal wire 21 on both sides of the filled trench 30 and in the remaining part of the filled trench 30, as shown in fig. 6. Specifically, the capping layer not only forms the closed space 60 with the inner wall of the filling groove 30, but also covers the surface of the metal wire portion 21 to protect the metal wire portion 21, thereby ensuring stable device performance.
It should be noted that the capping layer is formed of a material with poor filling properties to further ensure the realization of air bubbles. The filling method can be realized by adopting a PECVD (Plasma Enhanced Chemical Vapor Deposition) process with poor filling capability.
It should be further noted that the specific manufacturing process of the capping layer may be determined according to actual situations, for example, the specific manufacturing process is determined according to the material of the capping layer and the size and shape of the filling trench, including the specific process and the corresponding steps and time.
In an embodiment of the present application, a material of the capping layer includes a silicon oxygen compound and/or a silicon nitrogen compound, where the silicon oxygen compound is a compound formed by silicon element and oxygen element, and may be specifically silicon oxide. The silicon nitrogen compound is a compound formed by silicon and nitrogen, and can be silicon nitride specifically. Of course, the capping layer is not limited to the silicon oxide layer, and those skilled in the art can select other suitable insulating materials to form the capping layer according to practical situations to prevent the metal wiring from being oxidized.
In one embodiment of the present application, the material of the metal interconnection layer includes at least one of copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), molybdenum (Mo), osmium (Ir), and iridium (Os). Specifically, the material can reduce the resistance of the metal wiring layer, and of course, the material of the metal wiring layer is not limited thereto, and those skilled in the art can select other suitable materials according to the actual situation.
In another exemplary embodiment of the present application, a semiconductor device is provided, which is manufactured by the above manufacturing method.
The semiconductor device is formed by adopting the method, namely the metal connecting line part is formed by depositing and then etching, and the deposited width dimension is relatively large, so that holes are not easy to generate in the deposition process, namely the formed metal connecting line part is relatively dense and has relatively few holes. Therefore, compared with the prior art in which a metal line part is formed by filling metal in a groove, the metal line part has fewer holes, and thus has higher electric mobility and better device performance, for example, the device is 3DNAND, the bit line metal line is the metal line part, the bit line metal line has fewer holes, the RC delay index of the device is higher, and the response speed of the device is higher.
According to an embodiment of the present application, there is provided a semiconductor device, as shown in fig. 6, including:
a substrate 10 having an insulating dielectric layer 11;
a plurality of metal wire portions 21, wherein the metal wire portions 21 are located on the insulating dielectric layer 11, a space is formed between any two of the metal wire portions 21, at least a part of the space forms a filling groove 30, and the metal wire portions 21 are formed by etching metal wire layers (the metal wire layers are formed by a general deposition process, a part of the metal wire layers are removed by subsequent etching, and the remaining metal wire layers form a plurality of metal wire portions);
and a dielectric portion located in at least a part of the filling groove 30.
In the semiconductor device, the plurality of metal connecting parts are formed by etching, a space is formed between any two metal connecting parts, at least part of the metal connecting parts are spaced to form a filling groove, the medium part is positioned in at least part of the filling groove, the metal connecting parts are formed by first depositing and then etching, and holes are not easy to generate in the depositing process due to the relatively large width size of the deposition. Therefore, compared with the prior art that the metal is filled in the groove to form the metal connecting part, the semiconductor device reduces the probability of holes generated by the metal connecting part, and further improves the electric mobility, so that the performance of the device is improved.
In addition, since the metal wire portion 21 of the present invention is formed by etching a metal wire layer, the shape of the metal wire portion 21 in the semiconductor device is narrow at the bottom and wide at the top, that is, the width of the portion of each metal wire portion 21 close to the substrate 10 is the smallest, and the width of the metal wire portion 21 is gradually increased in the direction away from the substrate 10, as shown in fig. 6. That is, the shape of the metal wire portion in the semiconductor device of the present application is different from the shape of the metal wire portion formed by filling metal in the related art, and the shape of the metal wire portion in the related art is wide at the bottom and narrow at the top, that is, the width of the portion of each metal wire portion close to the substrate is the largest, and the width of the metal wire portion is gradually reduced in the direction away from the substrate.
In one embodiment of the present application, a material of the metal wire portion includes at least one of copper (Cu), tungsten (W), cobalt (Co), ruthenium (Ru), molybdenum (Mo), osmium (Ir), and iridium (Os). Specifically, the material may reduce the resistance of the metal wiring portion, but the material of the metal wiring portion is not limited thereto, and those skilled in the art may select other suitable materials according to actual circumstances.
In one embodiment of the present invention, as shown in fig. 4, the insulating dielectric layer 11 has a plurality of grooves, the metal wire portions 21 are located on the insulating dielectric layer 11 on both sides of the grooves, the gap is located above the grooves, and at least a portion of the gap and at least a portion of the grooves form the filling groove 30. Specifically, the grooves and the spaces are obtained by etching the insulating medium layer 11 and the metal connecting line layer 20 respectively to form the filling grooves 30, so that the spaced metal connecting lines 21 are formed, the metal connecting lines 21 are prevented from being formed by filling metal, and the probability of holes generated by the metal connecting lines is further reduced.
In an embodiment of the present application, as shown in fig. 5, the semiconductor device further includes a barrier layer 40, and the barrier layer 40 is at least located between the sidewall of the metal line portion 21 and the dielectric portion. Specifically, in the actual process, the barrier layer 40 is also located on the exposed surface of the metal wire portion, as shown in fig. 5. The barrier layer 40 is positioned between the side wall of the metal wire part and the medium part, and the barrier layer 40 can prevent metal of the metal wire part from diffusing to other areas, so that the device is further ensured to have good electrical property.
In order to further ensure that the barrier layer has a good diffusion-preventing effect on the metal, in an embodiment of the present application, the material of the barrier layer is a material with a uniform filling property and a good high barrier property, and specifically may be one or more of hafnium nitride, aluminum oxide, and hafnium oxide.
In one embodiment of the present application, as shown in fig. 6, the dielectric portion comprises air and a capping layer 50, wherein the air is located in the filling groove 30; the capping layer 50 and the inner wall of the filling groove form a closed space 60, and the air is located in the closed space 60. The air bubbles with the lowest dielectric constant replace the isolation dielectric layer in the prior art, so that the capacitance is minimized, the dielectric breakdown is reduced, and the device has better electrical performance.
Of course, the gas in the enclosed space is not limited to air, and may be other inert gases (herein, broadly, inert gases), such as nitrogen, etc. If other inert gases are in the enclosed space, in the actual process, the filling groove needs to be filled with the corresponding inert gases, which is complicated in process. Therefore, the most economical way is to fill the enclosed space with air, so that no additional process filling is needed in the manufacturing process, and no material cost is increased, because the air is filled in the groove.
It should be noted that the capping layer is formed by a material with poor filling performance to further ensure the realization of the air bubbles, and specifically, the material may include a silicon oxide compound and/or a silicon nitride compound, where the silicon oxide compound is a compound formed by silicon element and oxygen element, and specifically may be silicon oxide. The silicon nitrogen compound is a compound formed by silicon and nitrogen, and can be silicon nitride specifically. Of course, the capping layer is not limited to the silicon oxide layer, and those skilled in the art can select other suitable insulating materials to form the capping layer according to practical situations to prevent the metal wiring from being oxidized.
The manufacturing method of the present application can be applied to any device requiring the manufacturing of a metal wire portion, and is not limited to the manufacturing method of a 3D NAND flash memory. The semiconductor device of the present application is not limited to the 3D NAND flash memory, and may be another semiconductor device including a metal wiring portion. When the corresponding semiconductor device is a 3D NAND flash memory, other structures included in the corresponding substrate are well known to those skilled in the art, and include, for example, a stacked structure and the like.
From the above description, it can be seen that the above-described embodiments of the present application achieve the following technical effects:
1) according to the manufacturing method, a metal connecting line layer is formed on a substrate with an insulating medium layer, then a plurality of filling grooves are formed in the metal connecting line layer at least through etching, so that two sides of each filling groove are respectively provided with one metal connecting line part, and finally, a medium is filled in at least part of each filling groove to form a medium part. According to the method, the metal connecting line part is formed by deposition and etching, and holes are not easy to generate in the deposition process due to the fact that the deposited width is relatively large. Therefore, compared with the prior art that the metal connecting part is formed by filling metal in the groove, the method reduces the probability of generating holes in the metal connecting part, and further improves the electric mobility, so that the performance of the device is improved.
2) In the semiconductor structure, the plurality of metal connecting parts are formed by etching, a space is formed between any two metal connecting parts, at least part of the metal connecting parts are spaced to form a filling groove, the medium part is positioned in at least part of the filling groove, the metal connecting parts are formed by firstly depositing and then etching, and holes are not easy to generate in the depositing process due to the fact that the depositing width is relatively large. Therefore, compared with the prior art that the metal is filled in the groove to form the metal connecting part, the semiconductor structure reduces the probability of generating holes in the metal connecting part, and further improves the electric mobility, so that the performance of the device is improved.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (12)
1. A method for manufacturing a semiconductor device, comprising:
providing a substrate with an insulating medium layer;
forming a metal connecting line layer on the surface of the insulating medium layer;
etching at least part of the metal connecting line layer, forming a plurality of filling grooves at least in the metal connecting line layer, wherein metal connecting lines are arranged on two sides of the filling grooves;
and filling a medium in at least part of the filling groove to form a medium part.
2. The method of claim 1, wherein etching at least a portion of the metal interconnect layer to form a plurality of filled trenches in at least the metal interconnect layer comprises:
and sequentially removing part of the insulating medium layer and the metal connecting line layer, and forming a plurality of filling grooves in the insulating medium layer and the metal connecting line layer.
3. The method of manufacturing according to claim 1,
after forming the plurality of spaced metal wire portions and before forming the dielectric portion, the method further includes:
forming a barrier layer at least on the inner wall of the filled trench,
filling a medium in at least part of the filling groove to form a medium part, and the method comprises the following steps:
and filling the remaining part of the filling groove with a medium to form the medium part.
4. The method of claim 1, wherein the step of filling at least a portion of the filling groove with a dielectric to form a dielectric portion comprises:
and forming a capping layer at least above the filling groove, wherein the capping layer and the inner wall of the filling groove form a closed space, and the closed space is provided with air.
5. The method of claim 4, wherein forming a capping layer at least in the remaining portion of the fill trench comprises:
and forming the capping layer in the rest part of the filling groove and on the metal connecting parts at two sides of the filling groove.
6. Method of manufacturing according to any of claims 4 or 5, characterized in that the material of the capping layer comprises a silicon-oxygen compound and/or a silicon-nitrogen compound.
7. The method of claim 1, wherein the metal interconnect layer comprises at least one of copper, tungsten, cobalt, ruthenium, molybdenum, osmium, and iridium.
8. A semiconductor device, comprising:
a substrate having an insulating dielectric layer;
the metal connecting line parts are positioned on the insulating medium layer, a gap is formed between at least two metal connecting line parts, at least part of the gap forms a filling groove, and the metal connecting line parts are formed by etching the metal connecting line layers;
a dielectric portion located in at least a portion of the filling groove.
9. The semiconductor device according to claim 8, wherein the insulating dielectric layer has a plurality of grooves therein, the metal line is located on the insulating dielectric layer on both sides of the grooves, the space is located above the grooves and at least a portion of the space and at least a portion of the grooves form the filling trench.
10. The semiconductor device according to claim 8 or 9, characterized by further comprising:
and the barrier layer is at least positioned between the side wall of the metal wire part and the medium part.
11. The semiconductor device according to claim 8 or 9, wherein the dielectric portion comprises:
air located in the filling groove;
and the top sealing layer and the inner wall of the filling groove form a closed space, and the air is positioned in the closed space.
12. The semiconductor device according to claim 11, wherein a material of the capping layer comprises a silicon-oxygen compound and/or a silicon-nitrogen compound.
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