CN111232915A

CN111232915A - Multilayer mask layer structure, preparation method thereof and MEMS device

Info

Publication number: CN111232915A
Application number: CN202010066075.5A
Authority: CN
Inventors: 梁立兴; 朱京; 张琳琳; 裴志强
Original assignee: Beijing Chenjing Electronic Co ltd
Current assignee: Beijing Chenjing Electronic Co ltd
Priority date: 2020-01-20
Filing date: 2020-01-20
Publication date: 2020-06-05
Anticipated expiration: 2040-01-20
Also published as: CN111232915B

Abstract

The invention discloses a multi-layer mask layer structure which comprises a base layer and at least three mask layers sequentially stacked on the base layer, wherein the thickness of an n +1 th mask layer is 1.2-3 times that of an n mask layer. The invention also discloses a preparation method of the multilayer mask layer structure, which comprises the steps of firstly carrying out a cleaning process and a drying process on the base layer; three or more mask layers are then plated on the base layer, each time the plating is completed being annealed with specific annealing parameters. The invention also discloses an MEMS device prepared by the multilayer mask layer structure. The invention starts with the design of the relative thickness among the multiple film layers of the multiple mask layers and the parameters of each process in the preparation method, thereby effectively avoiding the problems of the serial etching and the side etching uniformity of different pattern layers in the subsequent photoetching-etched pattern definition release etching process while ensuring the corrosion resistance of the multiple mask layers and avoiding the phenomena of peeling, delaminating or insecure adhesion.

Description

Multilayer mask layer structure, preparation method thereof and MEMS device

Technical Field

The invention relates to the field of MEMS device preparation, in particular to a multilayer mask layer structure, a preparation method thereof and an MEMS device.

Background

In recent years, with the development of Micro-Electro-Mechanical systems (MEMS) technology, the complexity of a simple device structure is becoming more and more complex, and the conventional Micro-processing lithography and other processes can basically solve the precise control of the in-plane two-dimensional structure of the MEMS device. However, precise control of the longitudinal depth of quartz and other substrates, and in particular of the multilayer depth structure, is still not well achieved due to equipment considerations. On one hand, the photoresist is generally selected to be defined layer by layer in the traditional planar multi-layer defining process, the technology is characterized in that the photoresist which is not interfered by the two-phase removal process is selected to realize multi-part graphic definition at one time, the technology has the defects that the types of the photoresist which is compatible with each other (the removal processes are not interfered with each other) are limited, the multi-layer photoresist matching process, especially the photoresist with more than three layers, is very difficult, the storage time of the photoresist is limited (or the storage condition is harsh), the significance of batch storage is not realized, the semi-finished product of the predefined layer is difficult to realize the related commercial purchase and exchange values of batch production, and the deep development of related industries cannot be promoted; on the other hand, the structure of the substrate (quartz) defined by one-time deep etching is damaged to a certain extent, and cannot bear two or even three-time pattern definition processes (such as photoetching, etching, bonding and the like).

The multi-layer predefined technology of the quartz substrate is an etching control technology which realizes accurate control of a three-dimensional structure of a device by pre-designing and defining multiple to-be-defined patterns in a quartz mask layer in advance and releasing corresponding defined layers and etching in a continuous single step in a subsequent etching process. Meanwhile, the stable and reliable available multi-layer mask manufacturing technology is an important basis of the method for ensuring the smooth implementation of the technology.

At present, Cr/Au or Ti/Au masks are generally preferred for the mask layer of the quartz substrate, wherein the Cr layer mainly plays a role in improving the bonding force between the Au layer and the quartz substrate, and the Au layer is mainly used for blocking the etching of the quartz by etching liquid. Although the actual literature has the research on the double-layer Cr/Au/Cr/Au thin film, the main research content generally focuses on the research on the deposition process of the thin film, and the compatibility design of the three or more Cr/Au thin films and the relative thickness and relative process parameters among the multiple thin films for the subsequent photoetching process is less. In the actual processing process, the main reason that the application of three or more Cr/Au thin films is limited is that the relative thickness parameters between the two layers of the traditional double-layer Cr/Au thin films are generally rarely considered in the preparation process, so that the more serious side etching phenomenon occurs in the subsequent photoetching process; meanwhile, the annealing temperature generally selected by the traditional annealing process is higher, and the annealing design for distinguishing the gradients of different coatings is not realized; when three or more Cr/Au films are manufactured, the relative thickness and relative processing technological parameters of the multiple films are required to be designed, otherwise, the phenomena of process layer series, inconsistent pattern edge lateral etching and the like appear between mask layers in the subsequent photoetching-etching layer definition technological process easily caused by unreasonable technological parameter design among the films, and even product failure caused by insufficient corrosion resistance of the films.

Disclosure of Invention

Therefore, the invention aims to overcome the defect that an MEMS device with three or more mask layers cannot be manufactured due to the fact that the parameter design is unreasonable and the problems of series layer etching and side etching uniformity are easy to occur in the subsequent pattern definition release etching process in the prior art, so that a multilayer mask layer structure, a preparation method thereof and the MEMS device are provided.

The invention adopts the following technical scheme:

the application provides a multilayer mask layer structure, includes:

a base layer, and,

and at least three mask layers are sequentially stacked on the base layer, wherein the thickness of the (n + 1) th mask layer is 1.2-3 times of that of the n mask layer, n is a natural number except 0, and the specific range is determined according to the redundancy limit of the actual process design.

Specifically, the base layer is quartz, AlN, ZnO or LiNbO₃、LiTaO₃Any one of functional materials of MEMS technology, metal, ceramic, glass and organic materials;

the mask layer is one of a metal film, ceramic, glass or an organic coating film, and the metal film is a single-layer or double-layer metal film formed by one or two of Au, Cr, Ti, Ni and W films.

Preferably, the base layer is made of any quartz cut type quartz material, including fused quartz.

Preferably, the mask layer is a double-layer metal film composed of an auxiliary layer formed by one of Cr or Ti and a gold layer formed by Au, and the auxiliary layer is arranged on one side of the mask layer close to the base layer.

Further, the thickness of the n +1 th auxiliary layer is 1.3-3 times of that of the n th auxiliary layer, and the thickness of the n +1 th gold layer is 1.2-3 times of that of the n th gold layer; preferably, the thickness of the first auxiliary layer in the first mask layer is 5-50nm, and the thickness of the first gold layer is 50-500 nm.

The application also provides a preparation method of the multilayer mask layer structure, which comprises the following steps:

s1: taking a functional material of the MEMS process with a smooth surface as a base layer, and performing a cleaning process and a drying process;

s2: three or more mask layers are plated on the base layer.

Specifically, the cleaning process in the step S1 comprises the steps of sequentially carrying out alcohol cleaning, alkali cleaning and acid cleaning for 15-25min respectively, then carrying out ultrasonic cleaning for 8-15min in deionized water, and washing for 2-5min with deionized water; the drying process comprises the steps of spin-drying and then drying.

Specifically, the plating in step S2 may be physical deposition such as sputtering, evaporation, electron beam, laser, etc., (vapor) chemical deposition, and printing, film pasting, etc., and is preferably performed by using a sputter coater, performing an activation process before each plating, performing an annealing process after each plating, and performing a cleaning process and a drying process.

Further, the activation process is wet activation or dry activation, and the dry activation comprises modes such as laser assistance, plasma assistance and the like; wet activation is generally chemically assisted, with weak acid cleaning being the dominant step, and is performed according to conventional thin film activation procedures.

In the annealing process, the first annealing temperature of annealing after the first mask layer is plated is 120-150 ℃, the first annealing time is more than or equal to 8 hours, the second annealing temperature of annealing after the last mask layer is plated is 80-100 ℃, the second annealing time is more than or equal to 24 hours, the annealing temperature of annealing after the middle mask layer is plated is less than or equal to the second annealing temperature, and the annealing time is less than or equal to the second annealing time.

Furthermore, after each cleaning process and drying process, other processes such as etching, film deposition, electroplating, stripping, bonding, through hole and the like can be carried out continuously.

The invention also provides a multi-MEMS device which is manufactured by adopting the multi-layer mask layer structure and then using a multi-layer predefined technology. The multi-layer predefined technology is characterized in that the multi-layer mask layer structure is predefined on the surface of a substrate, then in the subsequent substrate etching process, the layer to be etched is released timely according to the requirement, and finally, after complete etching, the MEMS device with the multi-layer stereoscopic effect can be realized.

The technical scheme of the invention has the following advantages:

1. compared with the existing single mask layer and double mask layers, the MEMS device with the multi-layer mask layer structure provided by the invention has the advantages that more layers can be defined, and the MEMS device with richer layers can be processed conveniently. The MEMS three-dimensional device can be realized by two layers generally; however, for complex MEMS devices and multifunctional integrated MEMS devices, more layers are needed to meet the requirements of the devices. The requirement of multiple layers belongs to the development trend of future MEMS devices.

2. According to the MEMS device with the multi-layer mask layer structure, the serious mismatch of the lateral etching size of the layer caused by multiple mask layer releasing steps is avoided through the design of the relative thickness of the inner film layer of each mask layer, and the accuracy of subsequent pattern etching is ensured.

3. According to the preparation method of the MEMS device with the multi-layer mask layer structure, the annealing process parameter intensity after the deposition of the annealing first layer film is maximum, and the annealing parameter of the first layer film is preferably 120-150 ℃ for more than 8 hours. The annealing process of the last layer of film is preferably 80-100 ℃ for more than 24 hours. The important principle is that the first annealing temperature is not too high, and the phenomenon of cross-layer etching in the subsequent film layering etching process caused by the temperature exceeding 150 ℃ is prevented, and the phenomenon is easier to occur when the number of film layers is more; on the other hand, the annealing parameters of the intermediate film layer should not exceed the annealing temperature and the annealing time of the last film, and the reason is that the annealing of the intermediate film layer only needs to alleviate the accumulated unevenness of the film layer surface to a certain extent, so as to reduce the interlayer etching and layer crossing phenomenon possibly caused by structural protrusion, and the stress release of the multi-layer mask layer is carried out at the same time of the last annealing, so that the stress relieving effect is better.

4. According to the preparation method of the MEMS device with the multi-layer mask layer structure, the activation step is carried out before each film coating, the surface oxidation passivation layer and the adsorption particles are removed, and meanwhile a certain amount of dangling bonds are formed on the surface of the film layer, so that the bonding force of the next layer of film to be coated is guaranteed. Meanwhile, in the preparation process of three or more layers of films, unnecessary high-temperature annealing process needs to be avoided, and the bonding force and integrity of the film layer can be improved through a reasonable activation process.

5. According to the invention, by adopting the multi-layer predefined technology, because the multi-layer is defined by layers in the mask layer before the substrate is etched, the problem that the structure of the substrate after deep etching cannot bear the risk of structural damage to the substrate due to secondary or even tertiary pattern definition processes such as spraying (throwing) photoresist, photoetching and the like because the structure of the substrate is damaged to a certain degree is solved, and the risks of drying the photoresist, damaging the photoresist and the like of the traditional photoresist mask in a long-time release-etching process are avoided. On the other hand, the product with the predefined multiple image layers can be stored for a long time in the later period and directly delivered to the first party for use or any image layer in the product is taken or rejected. Meanwhile, the Party A can perform electroplating, new pattern layer definition, etching, trimming, bonding and other additional MEMS processes which are randomly inserted into any corresponding pattern layer without the need of substitute work, is favorable for the Party A to meet the sufficient confidentiality requirement of the self process and design flow, and has very good commercial popularization characteristic.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings can be obtained by those skilled in the art without creative efforts.

Fig. 1 is a schematic structural diagram of a MEMS device with a multi-layer mask layer structure before performing a last step of continuous multi-step lithography-etching in embodiment 1 of the present invention.

Description of reference numerals:

1-a quartz substrate layer; 2-a first Cr layer; 3-a first Au layer; 4-a second Cr layer; 5-a second Au layer; 6-a third Cr layer; 7-third Au layer.

Detailed Description

The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.

In addition, the technical features involved in the different embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.

Example 1

The embodiment provides a preparation method of a MEMS device with a multi-layer mask layer structure, which comprises the following steps:

(1) taking a quartz substrate sample with a smooth surface as a base layer, sequentially carrying out alcohol washing, alkali washing and acid washing for 20min respectively according to a standard cleaning process flow, then carrying out ultrasonic cleaning for 10min in deionized water, washing for 3min in the deionized water, carrying out spin-drying and drying, and then activating for 3s by using 180W plasma;

(2) sequentially coating and depositing a first Cr layer with the thickness of 10nm and a first Au layer with the thickness of 100nm on a quartz wafer to be coated by adopting a sputtering coating machine, and then carrying out an annealing process on the wafer which is subjected to the first chromium-gold coating process, wherein the annealing parameters are 120 ℃ and 12 hours;

(3) repeating the cleaning process in the step (1), spin-drying, drying and activating, adopting a sputtering film plating machine to sequentially plate and deposit a second Cr layer with the thickness of 20nm and a second Au layer with the thickness of 200nm on the quartz wafer to be plated with the film, and then carrying out an annealing process on the wafer subjected to the first chrome gold film plating process, wherein the annealing parameters are 80 ℃ and 12 hours;

(4) repeating the cleaning process of the step (1), spin-drying, drying and activating, sequentially coating and depositing a third Cr layer with the thickness of 30nm and a third Au layer with the thickness of 250nm on the quartz wafer to be coated by adopting a sputtering coating machine, and then performing an annealing process on the wafer which is subjected to the first chrome gold coating process, wherein the annealing parameters are 80 ℃ and 24 hours, and the structure of the wafer is shown in figure 1;

(5) and (2) repeating the cleaning process in the step (1), spin-drying, drying and activating, and then completing corresponding Cr/Au layer definition release by a continuous multi-step photoetching-etching method according to the requirements of deep etching and layer release of the actual device, thereby finally obtaining the MEMS device with a multi-layer mask layer structure.

Example 2

(1) taking a quartz substrate sample with a smooth surface as a base layer, sequentially carrying out alcohol washing, alkali washing and acid washing for 20min respectively according to a standard cleaning process flow, then carrying out ultrasonic cleaning for 10min in deionized water, washing for 3min in deionized water, spin-drying, and then activating for 3s by using 180W plasma;

(2) sequentially coating and depositing a first Cr layer with the thickness of 5nm and a first Au layer with the thickness of 50nm on the quartz wafer to be coated by adopting a sputtering coating machine, and then carrying out an annealing process on the wafer which is subjected to the first chromium-gold coating process, wherein the annealing parameters are 120 ℃ and 12 hours;

(3) repeating the cleaning process in the step (1), spin-drying, drying and activating, adopting a sputtering film plating machine to sequentially plate and deposit a second Cr layer with the thickness of 15nm and a second Au layer with the thickness of 150nm on the quartz wafer to be plated with the film, and then carrying out an annealing process on the wafer subjected to the first chrome gold film plating process, wherein the annealing parameters are 80 ℃ and 12 hours;

(4) repeating the cleaning process in the step (1), spin-drying, drying and activating, sequentially coating and depositing a third Cr layer with the thickness of 25nm and a third Au layer with the thickness of 210nm on the quartz wafer to be coated by adopting a sputtering coating machine, and then performing an annealing process on the wafer subjected to the first chrome gold coating process, wherein the annealing parameters are 80 ℃ and 12 hours;

(5) repeating the cleaning process in the step (1), spin-drying, drying and activating, adopting a sputtering film plating machine to sequentially plate and deposit a fourth Cr layer with the thickness of 33nm and a fourth Au layer with the thickness of 260nm on the quartz wafer to be plated, and then carrying out an annealing process on the wafer subjected to the first chrome gold film plating process, wherein the annealing parameter is 80 ℃ and the annealing time is 24 hours;

(6) and (2) repeating the cleaning process in the step (1), spin-drying, drying and activating, and then completing corresponding Cr/Au layer definition release by a continuous multi-step photoetching-etching method according to the requirements of deep etching and layer release of the actual device, thereby finally obtaining the MEMS device with a multi-layer mask layer structure.

Example 3

(2) sequentially coating and depositing a first Cr layer with the thickness of 20nm and a first Au layer with the thickness of 200nm on the quartz wafer to be coated by adopting a sputtering coating machine, and then carrying out an annealing process on the wafer which is subjected to the first chromium-gold coating process, wherein the annealing parameters are 120 ℃ and 12 hours;

(3) repeating the cleaning process in the step (1), spin-drying, drying and activating, adopting a sputtering film plating machine to sequentially plate and deposit a second Cr layer with the thickness of 35nm and a second Au layer with the thickness of 240nm on the quartz wafer to be plated with the film, and then carrying out an annealing process on the wafer subjected to the first chrome gold film plating process, wherein the annealing parameters are 80 ℃ and 12 hours;

(4) repeating the cleaning process in the step (1), spin-drying, drying and activating, adopting a sputtering film plating machine to sequentially plate and deposit a third Cr layer with the thickness of 50nm and a third Au layer with the thickness of 300nm on the quartz wafer to be plated, and then carrying out an annealing process on the wafer subjected to the first chrome gold film plating process, wherein the annealing parameter is 80 ℃ and the annealing time is 24 hours;

Example 4

(2) sequentially coating and depositing a first Ti layer with the thickness of 10nm and a first Au layer with the thickness of 150nm on the quartz wafer to be coated by adopting a sputtering coating machine, and then carrying out an annealing process on the wafer which is subjected to the first chromium-gold coating process, wherein the annealing parameter is 150 ℃ and 12 hours;

(3) repeating the cleaning process in the step (1), spin-drying, drying and activating, adopting a sputtering film plating machine to sequentially plate and deposit a second Ti layer with the thickness of 15nm and a second Au layer with the thickness of 200nm on the quartz wafer to be plated with the film, and then carrying out an annealing process on the wafer subjected to the first chrome gold film plating process, wherein the annealing parameters are 80 ℃ and 12 hours;

(4) repeating the cleaning process in the step (1), spin-drying, drying and activating, adopting a sputtering film plating machine to sequentially plate and deposit a third Ti layer with the thickness of 35nm and a third Au layer with the thickness of 300nm on the quartz wafer to be plated with the film, and then carrying out an annealing process on the wafer subjected to the first chrome gold film plating process, wherein the annealing parameters are 80 ℃ and 12 hours;

(5) and (2) repeating the cleaning process in the step (1), spin-drying and drying, and then completing corresponding Ti/Au layer definition release by a continuous multi-step photoetching-etching method according to the requirements of deep etching and layer release of the actual device, thereby finally obtaining the MEMS device with a multi-layer mask layer structure.

Comparative example 1

The embodiment provides a method for preparing a MEMS device with a multi-layer mask layer structure, which is different from the embodiment 1 only in the thickness of each chromium-gold layer, and includes the following steps:

(2) sequentially coating and depositing a first Cr layer with the thickness of 10nm and a first Au layer with the thickness of 200nm on a quartz wafer to be coated by adopting a sputtering coating machine, and then carrying out an annealing process on the wafer which is subjected to the first chromium-gold coating process, wherein the annealing parameters are 120 ℃ and 12 hours;

(3) repeating the cleaning process in the step (1), spin-drying, drying and activating, adopting a sputtering film plating machine to sequentially plate and deposit a second Cr layer with the thickness of 10nm and a second Au layer with the thickness of 200nm on the quartz wafer to be plated, and then carrying out an annealing process on the wafer subjected to the first chrome gold film plating process, wherein the annealing parameters are 80 ℃ and 12 hours;

(4) repeating the cleaning process in the step (1), spin-drying, drying and activating, adopting a sputtering film plating machine to sequentially plate and deposit a third Cr layer with the thickness of 10nm and a third Au layer with the thickness of 200nm on the quartz wafer to be plated, and then carrying out an annealing process on the wafer subjected to the first chrome gold film plating process, wherein the annealing parameter is 80 ℃ and the annealing time is 24 hours;

Comparative example 2

The embodiment provides a method for preparing a MEMS device with a multi-layer mask layer structure, which is different from embodiment 1 only in the parameters of each annealing, and includes the following steps:

(3) repeating the cleaning process in the step (1), spin-drying, drying and activating, adopting a sputtering film plating machine to sequentially plate and deposit a second Cr layer with the thickness of 20nm and a second Au layer with the thickness of 200nm on the quartz wafer to be plated, and then carrying out an annealing process on the wafer subjected to the first chrome gold film plating process, wherein the annealing parameter is 80 ℃ and the annealing time is 10 hours;

(4) repeating the cleaning process in the step (1), spin-drying, drying and activating, sequentially coating and depositing a third Cr layer with the thickness of 30nm and a third Au layer with the thickness of 250nm on the quartz wafer to be coated by adopting a sputtering coating machine, and then performing an annealing process on the wafer subjected to the first chrome gold coating process, wherein the annealing parameter is 150 ℃ and 12 hours;

Test examples

The corrosion resistance and the like of the MEMS devices having the multi-layered mask structure obtained in examples 1 to 4 and comparative examples 1 to 2 were tested, and the results are shown in the following table:

TABLE 1

From the above table, the MEMS device with a multi-layer mask layer structure prepared by the preparation method provided by the present application has a minimum corrosion resistance time of more than 50 hours, and the difference in etching amount between the mask layers is less than 3 μm, and there is no phenomenon of process crosstalk. Compared with the example 1, each layer of Cr and Au film does not meet the requirement of the application, the corrosion resistance time is not influenced, but the interlayer side etching amount difference is greatly increased; compared with the example 1, the annealing parameters of the comparative example 2 do not meet the requirements of the application, the corrosion resistance duration is not influenced, but the phenomenon of uneven edges appears between layers, and the process cascade layer appears, so that the value and the using effect of the MEMS device are greatly reduced.

It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are within the scope of the invention.

Claims

1. A multi-layer masking layer structure, comprising:

a base layer, and,

and at least three mask layers are sequentially stacked on the base layer, wherein the thickness of the (n + 1) th mask layer is 1.2-3 times that of the n mask layer, and n is a natural number except 0.

2. The multi-layer mask layer structure of claim 1, wherein the base layer is quartz, AlN, ZnO, LiNbO₃、LiTaO₃Any one of functional materials of MEMS technology, metal, ceramic, glass and organic materials;

3. The structure of claim 2, wherein the substrate is made of quartz with any quartz cut.

4. The structure of a multi-layer mask layer according to claim 2, wherein the mask layer is a dual-layer metal film consisting of an auxiliary layer of one of Cr or Ti and a gold layer of Au, and the auxiliary layer is on a side of the mask layer adjacent to the base layer.

5. The multi-layer mask layer structure of claim 4, wherein the thickness of the (n + 1) th auxiliary layer is 1.3-3 times the thickness of the n-th auxiliary layer, and the thickness of the (n + 1) th gold layer is 1.2-3 times the thickness of the n-th gold layer; preferably, the thickness of the first auxiliary layer in the first mask layer is 5-50nm, and the thickness of the first gold layer is 50-500 nm.

6. The method of making a multilayer masking layer structure of any of claims 1-5, comprising the steps of:

s2: three or more mask layers are plated on the base layer.

7. The preparation method according to claim 6, wherein the cleaning process in step S1 comprises sequentially performing alcohol washing, alkali washing, and acid washing for 15-25min, respectively, then ultrasonically cleaning in deionized water for 8-15min, and rinsing with deionized water for 2-5 min;

the drying process comprises the steps of spin-drying and then drying.

8. The manufacturing method according to claim 6 or 7, wherein the plating in step S2 is plating using a sputter coater, an activation process is performed before each plating, an annealing process is performed after each plating, and a cleaning process and a drying process are performed.

9. The production method according to claim 8, wherein the activation process is wet activation or dry activation;

10. A MEMS device, characterized in that a multi-layer mask layer structure according to any of claims 1-5 is used.