CN111210752A - Shifting register unit, driving method, grid driving circuit and display device - Google Patents
Shifting register unit, driving method, grid driving circuit and display device Download PDFInfo
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- CN111210752A CN111210752A CN202010064642.3A CN202010064642A CN111210752A CN 111210752 A CN111210752 A CN 111210752A CN 202010064642 A CN202010064642 A CN 202010064642A CN 111210752 A CN111210752 A CN 111210752A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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Abstract
The invention provides a shift register unit, a driving method, a grid driving circuit and a display device. The shift register unit comprises a grid driving signal output end and an output noise amplifying circuit; the output noise discharging circuit is respectively electrically connected with the adjacent next-stage pull-up node, the output clock signal end and the gate driving signal output end and is used for controlling the gate driving signal output end and the output clock signal end to be communicated under the control of the potential of the adjacent next-stage pull-up node. The invention can pull down the grid driving signal output by the grid driving signal output end instantly and reduce the falling time of the grid driving signal.
Description
Technical Field
The invention relates to the technical field of display driving, in particular to a shift register unit, a driving method, a grid driving circuit and a display device.
Background
In the existing shift register unit, the duty ratio of an output clock signal accessed by a gate driving signal output circuit must be less than 50%, and when the duty ratio is equal to 50%, the shift register unit cannot timely discharge the gate driving signal output by the shift register unit, so that the fall time Tf of the gate driving signal is increased, a switching tube in a display area of a display panel cannot be timely turned off, and the wrong charging is caused, thereby causing poor display; moreover, even if the duty ratio of the output clock signal is less than 50%, under the condition that the fault-tolerant time is insufficient, poor screen flashing still occurs under the high-low temperature reliability test.
Disclosure of Invention
The invention mainly aims to provide a shift register unit, a driving method, a grid driving circuit and a display device, and solves the problems that in the conventional shift register unit, when the duty ratio of an output clock signal is equal to 50%, the shift register unit cannot timely discharge the output grid driving signal, so that the falling time of the grid driving signal is increased, a switching tube in a display area of a display panel cannot be timely turned off, and the wrong charging is caused, so that the display is poor; moreover, even if the duty ratio of the output clock signal is less than 50%, under the condition that the fault-tolerant time is insufficient, the problem of poor screen flashing still occurs under the high-low temperature reliability test.
In order to achieve the above object, the present invention provides a shift register unit, comprising a gate driving signal output terminal and an output noise amplifying circuit;
the output noise discharging circuit is respectively electrically connected with the adjacent next-stage pull-up node, the output clock signal end and the gate driving signal output end and is used for controlling the gate driving signal output end and the output clock signal end to be communicated under the control of the potential of the adjacent next-stage pull-up node.
In implementation, the shift register unit further comprises a pull-up noise-releasing end and a pull-up node noise-releasing circuit;
the pull-up node noise amplifying circuit is respectively electrically connected with a pull-up noise amplifying control end, a pull-up node at the current stage and a noise amplifying voltage end, and is used for controlling the connection between the pull-up node at the current stage and the noise amplifying voltage end under the control of a pull-up noise amplifying control signal provided by the pull-up noise amplifying control end;
and the pull-up noise-amplifying control end of the Nth-stage shift register unit is electrically connected with the gate drive signal output end of the (N +2) th-stage shift register unit, and N is a positive integer.
In implementation, the output noise amplifying circuit comprises an output noise amplifying transistor;
the control electrode of the output noise-releasing transistor is electrically connected with the adjacent pull-up node of the next stage, the first electrode of the output noise-releasing transistor is electrically connected with the output clock signal end, and the second electrode of the output noise-releasing transistor is electrically connected with the gate drive signal output end.
In implementation, the pull-up node noise-discharging circuit comprises a pull-up node noise-discharging transistor;
the control electrode of the noise-discharging transistor of the pull-up node is electrically connected with the noise-discharging control end, the first electrode of the noise-discharging transistor of the pull-up node is electrically connected with the pull-up node of the current stage, and the second electrode of the noise-discharging transistor of the pull-up node is electrically connected with the noise-discharging voltage end.
In practice, the shift register unit of the present invention further comprises a pull-up node control circuit, an energy storage circuit, a pull-down node control circuit and an output circuit, wherein,
the pull-up node control circuit is respectively electrically connected with an input end, a first level end, a second level end, a protected pull-up node and a pull-down node, is used for controlling the connection between the pull-up node of the current stage and the first level end under the control of an input signal provided by the input end, and is used for controlling the connection between the pull-up node of the current stage and the second level end under the control of the potential of the pull-down node;
the first end of the energy storage circuit is electrically connected with the pull-up node at the current stage, and the second end of the energy storage circuit is electrically connected with the grid driving signal output end and used for storing voltage;
the pull-down node control circuit is used for controlling the potential of the pull-down node under the control of the potential of the pull-up node at the current stage;
the output circuit is respectively electrically connected with the current-stage pull-up node, the pull-down node, the reset end, the gate drive signal output end, the output clock signal end and the second level end, and is used for controlling the gate drive signal output end to be communicated with the output clock signal end under the control of the potential of the current-stage pull-up node, controlling the gate drive signal output end to be communicated with the second level end under the control of the potential of the pull-down node, and controlling the gate drive signal output end to be communicated with the second level end under the control of the output reset signal provided by the reset end.
In practice, the pull-up node control circuit includes an input transistor and a pull-up node control transistor;
the control electrode of the input transistor is electrically connected with the input end, the first electrode of the input transistor is electrically connected with the first level end, and the second electrode of the input transistor is electrically connected with the pull-up node of the current stage;
a control electrode of the pull-up node control transistor is electrically connected with the pull-down node, a first electrode of the pull-up node control transistor is electrically connected with the pull-up node of the current stage, and a second electrode of the pull-up node control transistor is electrically connected with the second level end;
the energy storage circuit comprises a storage capacitor, wherein the first end of the storage capacitor is the first end of the energy storage circuit, and the second end of the storage capacitor is the second end of the energy storage circuit;
the pull-down node control circuit comprises a first pull-down node control transistor and a second pull-down node control transistor;
a control electrode of the first pull-down node control transistor and a first electrode of the first pull-down node control transistor are electrically connected with a power supply voltage end, and a second electrode of the first pull-down node control transistor is electrically connected with the pull-down node;
the control electrode of the second pull-down node control transistor is electrically connected with the pull-up node at the current stage, the first electrode of the second pull-down node control transistor is electrically connected with the pull-down node, and the second electrode of the second pull-down node control transistor is electrically connected with the second level end.
In practice, the output circuit includes an output transistor, an output pull-down transistor, and an output reset transistor, wherein,
the control electrode of the output transistor is electrically connected with the pull-up node of the current stage, the first electrode of the output transistor is electrically connected with the output clock signal end, and the second electrode of the output transistor is electrically connected with the gate drive signal output end;
a control electrode of the output pull-down transistor is electrically connected with the pull-down node, a first electrode of the output pull-down transistor is electrically connected with the gate drive signal output end, and a second electrode of the output pull-down transistor is electrically connected with the second level end;
the control electrode of the output reset transistor is electrically connected with the reset end, the first electrode of the output reset transistor is electrically connected with the grid drive signal output end, and the second electrode of the output reset transistor is electrically connected with the second level end.
The invention also provides a driving method of the shift register unit, which is applied to the shift register unit and comprises the following steps:
and the output noise amplifying circuit controls to switch on or switch off the connection between the grid driving signal output end and the output clock signal end under the control of the potential of the pull-up node of the next adjacent stage.
In implementation, the shift register unit further comprises a pull-up noise-amplifying end and a pull-up node noise-amplifying circuit; the driving method of the shift register unit further includes:
the pull-up node noise amplifying circuit is controlled to be connected or disconnected between the pull-up node and the noise amplifying voltage end under the control of a pull-up noise amplifying control signal provided by the pull-up noise amplifying control end.
The invention also provides a grid driving circuit, which comprises the shift register unit;
the shift register unit is electrically connected with the pull-up node of the current stage in the adjacent next-stage shift register unit, and the pull-up node of the current stage in the adjacent next-stage shift register unit is the adjacent next-stage pull-up node.
In implementation, the shift register unit further comprises a pull-up node noise-discharging circuit; the pull-up node noise amplifying circuit is electrically connected with the pull-up noise amplifying control end;
a pull-up node noise amplifying circuit included in the Nth-stage shift register unit is electrically connected with a grid driving signal output end of the (N +2) th-stage shift register unit; n is a positive integer.
The invention also provides a display device which comprises the grid drive circuit.
In implementation, the display device comprises two gate driving circuits; the display device further comprises a plurality of rows of gate lines;
the Nth-level grid driving signal output end of the first grid driving circuit is electrically connected with the 2N-1 th row of grid lines;
the Nth stage grid driving signal output end of the second grid driving circuit is electrically connected with the 2 Nth row of grid lines; n is a positive integer.
Compared with the prior art, the shift register unit, the driving method, the Gate driving circuit and the display device are additionally provided with the output noise-discharging circuit, the Gate driving signal output by the Gate driving signal output end can be instantly pulled down through the voltage of the pull-up node fed back by the adjacent next-stage shift register unit, the falling time of the Gate driving signal is reduced, the size of an output transistor in the shift register unit can be further reduced, the size of a Gate On Array (GOA) can be reduced, a narrow frame is realized, meanwhile, the charging time of pixels can be prolonged, the stability of the GOA in a high-low temperature reliability test can be improved, and the electronic defects of a flash screen and the like are solved.
Drawings
FIG. 1 is a block diagram of a shift register unit according to an embodiment of the present invention;
FIG. 2 is a block diagram of a shift register unit according to another embodiment of the present invention;
FIG. 3 is a block diagram of a shift register unit according to another embodiment of the present invention;
FIG. 4 is a circuit diagram of one embodiment of a shift register cell according to the present invention;
FIG. 5 is a timing diagram illustrating the operation of the shift register unit according to the present invention;
FIG. 6 is a waveform diagram of one embodiment of the first clock signal CLK1, the third clock signal CLK3, the fifth clock signal CLK5, and the seventh clock signal CLK7
Fig. 7 is a schematic connection diagram of four stages of shift register units in the gate driving circuit according to the embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The transistors used in all embodiments of the present invention may be transistors, thin film transistors, or field effect transistors or other devices with the same characteristics. In the embodiment of the present invention, in order to distinguish two poles of the transistor except the control pole, one pole is called a first pole, and the other pole is called a second pole.
In practical operation, when the transistor is a triode, the control electrode may be a base electrode, the first electrode may be a collector electrode, and the second electrode may be an emitter electrode; alternatively, the control electrode may be a base electrode, the first electrode may be an emitter electrode, and the second electrode may be a collector electrode.
In practical operation, when the transistor is a thin film transistor or a field effect transistor, the control electrode may be a gate electrode, the first electrode may be a drain electrode, and the second electrode may be a source electrode; alternatively, the control electrode may be a gate electrode, the first electrode may be a source electrode, and the second electrode may be a drain electrode.
As shown in fig. 1, the shift register unit according to the embodiment of the present invention includes a gate driving signal Output terminal Output _ N and an Output noise discharging circuit 10;
the Output noise amplifying circuit 10 is respectively electrically connected to the next-stage pull-up node PU (N +1), the Output clock signal terminal CLK and the gate drive signal Output terminal Output _ N, and is configured to control the gate drive signal Output terminal Output _ N and the Output clock signal terminal CLK to be communicated with each other under the control of the potential of the next-stage pull-up node PU (N + 1);
the output clock signal terminal CLK is used to provide an output clock signal.
The shift register unit described in the embodiment of the present invention is additionally provided with the Output noise discharging circuit 10, and the Gate driving signal Output by the Gate driving signal Output terminal Output _ N can be instantaneously pulled down by the voltage of the pull-up node fed back by the adjacent next stage of shift register unit, so as to reduce the fall time Tf of the Gate driving signal, and further reduce the size of the Output transistor (the control electrode of the Output transistor is electrically connected with the pull-up node of the present stage, the first electrode of the Output transistor is electrically connected with the Output clock signal terminal, and the second electrode of the Output transistor is electrically connected with the Gate driving signal Output terminal) in the shift register unit, so as to reduce the size of a Gate On Array (Gate driving circuit disposed On the Array substrate), realize a narrow frame, and simultaneously improve the charging time of the pixel, and most importantly, improve the stability of the GOA in a high and low temperature reliability test, solving the poor electrical property such as screen flashing and the like.
In specific implementation, since the shift register unit according to the embodiment of the invention can reduce the falling time of the gate driving signal, the overlapping time of the gate driving signal to turn on the corresponding gate line and the data line to provide the data voltage to the corresponding pixel can be properly increased, and thus the charging time can be increased.
In the related art, in the high and low temperature reliability test, the falling time Tf of the gate driving signal is increased, and crosstalk is caused, so that electrical defects such as a flash screen are caused.
Preferably, as shown in fig. 2, on the basis of the embodiment of the shift register unit shown in fig. 1, the shift register unit S0 according to the embodiment of the present invention may further include a pull-up noise-discharging terminal and a pull-up node noise-discharging circuit 20;
the pull-up node noise amplifying circuit 20 is respectively electrically connected with a pull-up noise amplifying control terminal, a pull-up node pu (n) of the current stage and a noise amplifying voltage terminal Vf, and is configured to control the connection between the pull-up node pu (n) of the current stage and the noise amplifying voltage terminal Vf under the control of a pull-up noise amplifying control signal provided by the pull-up noise amplifying control terminal;
and the pull-up noise-amplifying control end of the Nth-stage shift register unit is electrically connected with the gate driving signal Output end Output _ N +2 of the (N +2) th-stage shift register unit, and N is a positive integer.
In a specific implementation, the noise-discharging voltage terminal may be a low-level terminal or a ground terminal, but is not limited thereto.
The shift register unit according to the embodiment of the present invention electrically connects the pull-up noise-discharging control terminal of the nth stage shift register unit to the gate driving signal Output terminal Output _ N +2 of the (N +2) th stage shift register unit, so as to perform delay noise-discharging on the potential of the pull-up node pu (N) of the present stage, and thus, the Output _ N may be repeatedly discharged and pulled down by outputting the low potential of the clock signal itself.
Specifically, the output noise amplifying circuit may include an output noise amplifying transistor;
the control electrode of the output noise-releasing transistor is electrically connected with the adjacent pull-up node of the next stage, the first electrode of the output noise-releasing transistor is electrically connected with the output clock signal end, and the second electrode of the output noise-releasing transistor is electrically connected with the gate drive signal output end.
Specifically, the pull-up node noise-discharging circuit may include a pull-up node noise-discharging transistor;
the control electrode of the noise-discharging transistor of the pull-up node is electrically connected with the noise-discharging control end, the first electrode of the noise-discharging transistor of the pull-up node is electrically connected with the pull-up node of the current stage, and the second electrode of the noise-discharging transistor of the pull-up node is electrically connected with the noise-discharging voltage end.
In practical implementation, on the basis of the embodiment of the shift register unit shown in fig. 2, as shown in fig. 3, the shift register unit according to the embodiment of the present invention may further include a pull-up node control circuit 31, a tank circuit 32, a pull-down node control circuit 33, and an output circuit 34, wherein,
the pull-up node control circuit 31 is electrically connected to the Input terminal Input, the first level terminal Vt1, the second level terminal Vt2, the pull-up node pu (n) of the present stage, and the pull-down node PD, respectively, and is configured to control communication between the pull-up node pu (n) of the present stage and the first level terminal Vt1 under control of an Input signal provided by the Input terminal Input, and to control communication between the pull-up node pu (n) of the present stage and the second level terminal Vt2 under control of a potential of the pull-down node PD;
a first end of the energy storage circuit 32 is electrically connected to the pull-up node pu (N) of the current stage, and a second end of the energy storage circuit 32 is electrically connected to the gate driving signal Output end Output _ N for storing voltage;
the pull-down node control circuit 33 is electrically connected to the pull-up node pu (n) of the current stage and the pull-down node, respectively, and is configured to control the potential of the pull-down node PD under the control of the potential of the pull-up node pu (n) of the current stage;
the Output circuit 34 is electrically connected to the pull-up node pu (N), the pull-down node PD, the reset terminal RST, the gate driving signal Output terminal Output _ N, the Output clock signal terminal CLK, and the second level terminal Vt2, respectively, and is configured to control communication between the gate driving signal Output terminal Output _ N and the Output clock signal terminal CLK under control of a potential of the pull-up node pu (N), control communication between the gate driving signal Output terminal Output _ N and the second level terminal Vt2 under control of a potential of the pull-down node PD, and control communication between the gate driving signal Output terminal Output _ N and the second level terminal Vt2 under control of an Output reset signal provided by the reset terminal RST;
the output clock signal terminal CLK is used to provide an output clock signal.
In one implementation, the first level Vt1 can be a high level Vt, and the second level Vt2 can be a low level Vt, but not limited thereto.
When the shift register unit shown in fig. 3 works, the pull-up node control circuit 31 and the pull-up node noise-discharging circuit 20 control the potential of the pull-up node pu (N) of the present stage together, the pull-down node control circuit 33 controls the potential of the pull-down node PD (N) according to the potential of the pull-up node pu (N) of the present stage, and the Output circuit 34 controls the Output of the gate driving signal through the gate driving signal Output terminal Output _ N under the control of the potential of the pull-up node pu (N) of the present stage, the potential of the pull-down node PD and the Output reset signal provided by the reset terminal RST.
In specific implementation, the input terminal of the b-th stage shift register unit may be electrically connected to the gate driving signal output terminal of the b-2 th stage shift register unit, but not limited thereto;
b is an integer greater than 2.
Specifically, the pull-up node control circuit may include an input transistor and a pull-up node control transistor;
the control electrode of the input transistor is electrically connected with the input end, the first electrode of the input transistor is electrically connected with the first level end, and the second electrode of the input transistor is electrically connected with the pull-up node of the current stage;
a control electrode of the pull-up node control transistor is electrically connected with the pull-down node, a first electrode of the pull-up node control transistor is electrically connected with the pull-up node of the current stage, and a second electrode of the pull-up node control transistor is electrically connected with the second level end;
the energy storage circuit can comprise a storage capacitor, wherein the first end of the storage capacitor is the first end of the energy storage circuit, and the second end of the storage capacitor is the second end of the energy storage circuit;
the pull-down node control circuit may include a first pull-down node control transistor and a second pull-down node control transistor;
a control electrode of the first pull-down node control transistor and a first electrode of the first pull-down node control transistor are electrically connected with a power supply voltage end, and a second electrode of the first pull-down node control transistor is electrically connected with the pull-down node;
the control electrode of the second pull-down node control transistor is electrically connected with the pull-up node at the current stage, the first electrode of the second pull-down node control transistor is electrically connected with the pull-down node, and the second electrode of the second pull-down node control transistor is electrically connected with the second level end.
Specifically, the output circuit may include an output transistor, an output pull-down transistor, and an output reset transistor, wherein,
the control electrode of the output transistor is electrically connected with the pull-up node of the current stage, the first electrode of the output transistor is electrically connected with the output clock signal end, and the second electrode of the output transistor is electrically connected with the gate drive signal output end;
a control electrode of the output pull-down transistor is electrically connected with the pull-down node, a first electrode of the output pull-down transistor is electrically connected with the gate drive signal output end, and a second electrode of the output pull-down transistor is electrically connected with the second level end;
the control electrode of the output reset transistor is electrically connected with the reset end, the first electrode of the output reset transistor is electrically connected with the grid drive signal output end, and the second electrode of the output reset transistor is electrically connected with the second level end.
The shift register unit according to the present invention is described below with reference to an embodiment.
As shown in fig. 4, an embodiment of the shift register unit according to the present invention includes a gate driving signal Output terminal Output _ N, an Output noise discharging circuit 10, a pull-up noise discharging terminal, a pull-up node noise discharging circuit 20, a pull-up node control circuit, a tank circuit, a pull-down node control circuit, and an Output circuit,
the specific embodiment of the shift register unit shown in fig. 4 of the present invention may be an nth stage shift register unit included in the gate driving circuit, where N is a positive integer;
the output noise amplifying circuit 10 comprises an output noise amplifying transistor M9;
the gate of the Output noise-discharging transistor M9 is electrically connected to the adjacent next-stage pull-up node PU (N +1), the drain of the Output noise-discharging transistor M9 is electrically connected to the Output clock signal terminal CLK, and the source of the Output noise-discharging transistor M9 is electrically connected to the gate driving signal Output terminal Output _ N;
the pull-up node noise-discharging circuit comprises a pull-up node noise-discharging transistor M2;
the gate of the pull-up node noise-discharging transistor M2 is electrically connected to the gate driving signal Output terminal Output _ N +2 of the (N +2) th stage shift register unit, the drain of the pull-up node noise-discharging transistor M2 is electrically connected to the pull-up node pu (N) of the current stage, and the source of the pull-up node noise-discharging transistor M2 is electrically connected to the low level terminal; the low level end is used for providing a low level VGL;
the pull-up node control circuit includes an input transistor M1 and a pull-up node control transistor M7;
the gate of the Input transistor M1 is electrically connected to the Input terminal Input, the drain of the Input transistor M1 is electrically connected to the high level terminal, and the source of the Input transistor M1 is electrically connected to the current-stage pull-up node pu (n); the high level end is used for providing a high level VGH;
the gate of the pull-up node control transistor M7 is electrically connected to the pull-down node PD, the drain of the pull-up node control transistor M7 is electrically connected to the current-stage pull-up node pu (n), and the source of the pull-up node control transistor M7 is electrically connected to the low-level end;
the energy storage circuit comprises a storage capacitor C;
a first end of the storage capacitor C is electrically connected to the current-stage pull-up node pu (N), and a second end of the storage capacitor C is electrically connected to the gate driving signal Output end Output _ N;
the pull-down node control circuit includes a first pull-down node control transistor M5 and a second pull-down node control transistor M6;
a gate of the first pull-down node control transistor M5 and a drain of the first pull-down node control transistor M5 are electrically connected to a power supply voltage terminal, and a source of the first pull-down node control transistor M5 is electrically connected to the pull-down node PD; the power supply voltage end is used for providing power supply voltage VDD;
the gate of the second pull-down node control transistor M6 is electrically connected to the current-stage pull-up node pu (n), the drain of the second pull-down node control transistor M6 is electrically connected to the pull-down node PD, and the source of the second pull-down node control transistor M6 is electrically connected to the low-level terminal;
the output circuit includes an output transistor M3, an output pull-down transistor M8, and an output reset transistor M4, wherein,
the gate of the Output transistor M3 is electrically connected to the pull-up node pu (N) of the current stage, the drain of the Output transistor M3 is electrically connected to the Output clock signal terminal CLK, and the source of the Output transistor M3 is electrically connected to the gate driving signal Output terminal Output _ N;
the gate of the Output pull-down transistor M8 is electrically connected to the pull-down node PD, the drain of the Output pull-down transistor M8 is electrically connected to the gate driving signal Output terminal Output _ N, and the source of the Output pull-down transistor M8 is electrically connected to the low level terminal;
the gate of the Output reset transistor M4 is electrically connected to the reset terminal RST, the drain of the Output reset transistor M4 is electrically connected to the gate driving signal Output terminal Output, and the source of the Output reset transistor M4 is electrically connected to the low level terminal.
In the embodiment of the shift register unit shown in fig. 4, all the transistors are n-type thin film transistors, but not limited thereto.
In the embodiment of the shift register unit shown in fig. 4, the Input is electrically connected to the gate driving signal output terminal of the N-2 th stage shift register unit, but not limited thereto.
In the related art, M9 is not provided, when the duty ratio of the Output clock signal is equal to 50%, the gate driving signal Output by Output _ N cannot be timely discharged through M3, and the specific embodiment of the shift register unit according to the present invention can reduce the fall time Tf of the gate driving signal through M9, so that the gate driving signal can be timely discharged, and thus, the shift register unit can normally operate when the duty ratio of the Output clock signal is equal to 50%.
As shown in fig. 5, it is assumed that the output clock signal adopted by the nth stage shift register unit shown in fig. 4 is the first clock signal CLK1, and the output clock signal adopted by the (N +1) th stage shifter unit is the third clock signal CLK 3;
in operation of this particular embodiment of the shift register cell of the present invention,
in a first time period T1, CLK1 is low, Input provides high, M1 is on, VGH charges C through M1, so that the potential of pu (n) is pulled high, the potential of pu (n) becomes high, so that M6 is on to pull the potential of PD low, so that M7 and M8 are off;
in a second time period T2, Input provides a low level, CLK1 is a high level, M1 is turned off, the potential of pu (N) continues to be kept at a high level, M3 is turned on, the potential of pu (N) raises the voltage of the pull-up node pu (N) due to a bootstrap effect, Output _ N outputs a high level, at this time, the potential of pu (N) is a high level, M6 is still turned on, and the potential of PD is kept at a low level, so that M7 and M8 are kept off;
in a third time period T3, CLK1 and CLK3 are both at high level, the potential of PU (N +1) is also raised due to the bootstrap effect, and at this time, PU (N +1) feeds back a high level to the nth stage shift register unit, so that the gate driving signal Output by Output _ N can be enhanced, and the effect of maintaining the potential of PU (N) is achieved;
in the fourth time period T4, CLK1 is at a low level, the PU bootstrap effect disappears, at this time, PU (N +1) is still in a bootstrap pull-up state, the gate driving signal Output by Output _ N is pulled down to VGL, the falling edge Tf of the gate driving signal can be reduced for a GOA time sequence with a duty ratio not being 50%, and after the potential of the gate driving signal Output by Output (N) becomes a low level VGL, the potential of PU (N +1) still keeps the bootstrap pull-up state, so that the gate driving signal Output by Output _ N plays a role of continuously releasing noise, and the stability of the operation of the GOA is enhanced.
The driving method of the shift register unit according to the embodiment of the present invention is applied to the shift register unit described above, and the driving method of the shift register unit includes:
and the output noise amplifying circuit controls to switch on or switch off the connection between the grid driving signal output end and the output clock signal end under the control of the potential of the pull-up node of the next adjacent stage.
The driving method of the shift register unit according to the embodiment of the present invention can instantaneously pull down the Gate driving signal output from the Gate driving signal output terminal through the output noise discharging circuit and the voltage of the pull-up node fed back by the adjacent next stage of shift register unit, so as to reduce the fall time Tf of the Gate driving signal, and further reduce the size of the output transistor (the control electrode of the output transistor is electrically connected to the pull-up node of the present stage, the first electrode of the output transistor is electrically connected to the output clock signal terminal, and the second electrode of the output transistor is electrically connected to the Gate driving signal output terminal) in the shift register unit, so as to reduce the size of a Gate On Array (Gate driving circuit disposed On the Array substrate), realize a narrow frame, and simultaneously improve the charging time of the pixel, and most importantly, improve the stability of the GOA in a high and low temperature reliability test, solving the poor electrical property such as screen flashing and the like.
Preferably, the shift register unit may further include a pull-up noise-discharging end and a pull-up node noise-discharging circuit; the driving method of the shift register unit further includes:
the pull-up node noise amplifying circuit is controlled to be connected or disconnected between the pull-up node and the noise amplifying voltage end under the control of a pull-up noise amplifying control signal provided by the pull-up noise amplifying control end.
The driving method of the shift register unit can delay and discharge the noise of the potential of the pull-up node of the current stage, so that the grid driving signal can be repeatedly discharged and pulled down through the low potential of the output clock signal.
The gate drive circuit comprises the shift register unit;
the shift register unit is electrically connected with the pull-up node of the current stage in the adjacent next-stage shift register unit, and the pull-up node of the current stage in the adjacent next-stage shift register unit is the adjacent next-stage pull-up node.
Specifically, the shift register unit may further include a pull-up node noise-discharging circuit; the pull-up node noise amplifying circuit is electrically connected with the pull-up noise amplifying control end;
a pull-up node noise amplifying circuit included in the Nth-stage shift register unit is electrically connected with a grid driving signal output end of the (N +2) th-stage shift register unit; n is a positive integer.
The display device provided by the embodiment of the invention comprises the gate drive circuit.
In a specific implementation, the display device may include two of the gate driving circuits; the display device further comprises a plurality of rows of gate lines;
the Nth-level grid driving signal output end of the first grid driving circuit is electrically connected with the 2N-1 th row of grid lines;
the Nth stage grid driving signal output end of the second grid driving circuit is electrically connected with the 2 Nth row of grid lines; n is a positive integer.
In an embodiment of the present invention, the display device may include two gate driving circuits;
the first gate driving circuit can provide a gate driving signal for odd-numbered gate lines, and the second gate driving circuit can provide a gate driving signal for even-numbered gate lines;
that is, the gate driving signal output end of the first stage shift register unit included in the first gate driving circuit may be electrically connected to the first row of gate lines, the gate driving signal output end of the second stage shift register unit included in the first gate driving circuit is electrically connected to the third row of gate lines, the gate driving signal output end of the third stage shift register unit included in the first gate driving circuit is electrically connected to the fifth row of gate lines, and the gate driving signal output end of the fourth stage shift register unit included in the first gate driving circuit is electrically connected to the seventh row of gate lines;
the grid driving signal output end of the first-stage shift register unit included in the second grid driving circuit can be electrically connected with the second row of grid lines, the grid driving signal output end of the second-stage shift register unit included in the first grid driving circuit is electrically connected with the fourth row of grid lines, the grid driving signal output end of the third-stage shift register unit included in the first grid driving circuit is electrically connected with the sixth row of grid lines, and the grid driving signal output end of the fourth-stage shift register unit included in the first grid driving circuit is electrically connected with the eighth row of grid lines;
in a specific implementation, the first gate driving circuit, the second gate driving circuit and the gate lines of each row can be disposed on the display substrate;
the first gate driving circuit may be disposed at the left side of the display substrate, and the second gate driving circuit may be disposed at the right side of the display substrate; alternatively, the first gate driving circuit may be disposed on the right side of the display substrate, and the second gate driving circuit may be disposed on the left side of the display substrate.
In a specific implementation, the output clock signal received by the shift register unit of the 4a-3 th stage included in the first gate driving circuit may be the first clock signal CLK1, the output clock signal received by the shift register unit of the 4a-2 th stage included in the first gate driving circuit may be the third clock signal CLK3, the output clock signal received by the shift register unit of the 4a-1 th stage included in the first gate driving circuit may be the fifth clock signal CLK5, and the output clock signal received by the shift register unit of the 4a th stage included in the first gate driving circuit may be the seventh clock signal CLK 7; a is a positive integer;
the output clock signal received by the shift register unit of the 4a-3 th stage included in the second gate driving circuit may be the second clock signal CLK2, the output clock signal received by the shift register unit of the 4a-2 th stage included in the second gate driving circuit may be the fourth clock signal CLK4, the output clock signal received by the shift register unit of the 4a-1 th stage included in the second gate driving circuit may be the sixth clock signal CLK6, and the output clock signal received by the shift register unit of the 4a th stage included in the second gate driving circuit may be the eighth clock signal CLK 8;
FIG. 6 is a waveform diagram of one embodiment of CLK1, CLK3, CLK5, and CLK 7.
Fig. 7 shows an nth stage shift register unit SN, an N +1 th stage shift register unit SN +1, an N +2 th stage shift register unit SN +2, and an N +3 th stage shift register unit SN +3 included in the gate driving circuit according to the embodiment of the present invention; n is a positive integer;
in fig. 7, the reference numeral is Input, and the reference numeral is RES is pull-up noise-discharging reset terminal;
in fig. 7, a gate driving signal Output terminal denoted by Output _ N is SN, a gate driving signal Output terminal denoted by Output _ N +1 is SN +1, a gate driving signal Output terminal denoted by Output _ N +2 is SN +2, and a gate driving signal Output terminal denoted by Output _ N +3 is SN + 3; PU (N) is a pull-up node in SN, PU (N +1) is a pull-up node in SN +1, PU (N +2) is a pull-up node in SN +2, and PU (N +3) is a pull-up node in SN + 3;
SN is electrically connected with PU (N +1), SN +1 is electrically connected with PU (N +2), and SN +2 is electrically connected with PU (N + 3);
the pull-up noise-releasing control end of the SN is electrically connected with Output _ N +2, and the pull-up noise-releasing control end of the SN +1 is electrically connected with Output _ N + 3;
the input end of SN +2 is electrically connected with Output _ N, and the input end of SN +3 is electrically connected with Output _ N + 1;
and in the embodiment shown in fig. 7, N equals 1, the input of SN is connected to the first start signal STV1, the input of SN +1 is connected to the second start signal STV 3;
in the embodiment shown in fig. 7, N may also be other positive integers not equal to 1;
in fig. 7, CLK is the output clock signal terminal, VGH is high, VGL is low, and VSS is low;
in fig. 7, the output clock signal terminal of SN is connected to the first clock signal CLK1, the output clock signal terminal of SN +1 is connected to the third clock signal CLK3, the output clock signal terminal of SN +2 is connected to the fifth clock signal CLK5, and the output clock signal terminal of SN +3 is connected to the seventh clock signal CLK7, but not limited thereto.
The display device provided by the embodiment of the invention can be any product or component with a display function, such as a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (13)
1. A shift register unit is characterized by comprising a grid driving signal output end and an output noise amplifying circuit;
the output noise discharging circuit is respectively electrically connected with the adjacent next-stage pull-up node, the output clock signal end and the gate driving signal output end and is used for controlling the gate driving signal output end and the output clock signal end to be communicated under the control of the potential of the adjacent next-stage pull-up node.
2. The shift register cell of claim 1, further comprising a pull-up noise-discharging terminal and a pull-up node noise-discharging circuit;
the pull-up node noise amplifying circuit is respectively electrically connected with a pull-up noise amplifying control end, a pull-up node at the current stage and a noise amplifying voltage end, and is used for controlling the connection between the pull-up node at the current stage and the noise amplifying voltage end under the control of a pull-up noise amplifying control signal provided by the pull-up noise amplifying control end;
and the pull-up noise-amplifying control end of the Nth-stage shift register unit is electrically connected with the gate drive signal output end of the (N +2) th-stage shift register unit, and N is a positive integer.
3. The shift register cell of claim 1, wherein the output noise-discharging circuit comprises an output noise-discharging transistor;
the control electrode of the output noise-releasing transistor is electrically connected with the adjacent pull-up node of the next stage, the first electrode of the output noise-releasing transistor is electrically connected with the output clock signal end, and the second electrode of the output noise-releasing transistor is electrically connected with the gate drive signal output end.
4. The shift register cell of claim 2, wherein the pull-up node noise-discharging circuit comprises a pull-up node noise-discharging transistor;
the control electrode of the noise-discharging transistor of the pull-up node is electrically connected with the noise-discharging control end, the first electrode of the noise-discharging transistor of the pull-up node is electrically connected with the pull-up node of the current stage, and the second electrode of the noise-discharging transistor of the pull-up node is electrically connected with the noise-discharging voltage end.
5. The shift register cell of any one of claims 1-4, further comprising a pull-up node control circuit, a tank circuit, a pull-down node control circuit, and an output circuit, wherein,
the pull-up node control circuit is respectively electrically connected with an input end, a first level end, a second level end, a protected pull-up node and a pull-down node, is used for controlling the connection between the pull-up node of the current stage and the first level end under the control of an input signal provided by the input end, and is used for controlling the connection between the pull-up node of the current stage and the second level end under the control of the potential of the pull-down node;
the first end of the energy storage circuit is electrically connected with the pull-up node at the current stage, and the second end of the energy storage circuit is electrically connected with the grid driving signal output end and used for storing voltage;
the pull-down node control circuit is used for controlling the potential of the pull-down node under the control of the potential of the pull-up node at the current stage;
the output circuit is respectively electrically connected with the current-stage pull-up node, the pull-down node, the reset end, the gate drive signal output end, the output clock signal end and the second level end, and is used for controlling the gate drive signal output end to be communicated with the output clock signal end under the control of the potential of the current-stage pull-up node, controlling the gate drive signal output end to be communicated with the second level end under the control of the potential of the pull-down node, and controlling the gate drive signal output end to be communicated with the second level end under the control of the output reset signal provided by the reset end.
6. The shift register cell of claim 5, wherein the pull-up node control circuit comprises an input transistor and a pull-up node control transistor;
the control electrode of the input transistor is electrically connected with the input end, the first electrode of the input transistor is electrically connected with the first level end, and the second electrode of the input transistor is electrically connected with the pull-up node of the current stage;
a control electrode of the pull-up node control transistor is electrically connected with the pull-down node, a first electrode of the pull-up node control transistor is electrically connected with the pull-up node of the current stage, and a second electrode of the pull-up node control transistor is electrically connected with the second level end;
the energy storage circuit comprises a storage capacitor, wherein the first end of the storage capacitor is the first end of the energy storage circuit, and the second end of the storage capacitor is the second end of the energy storage circuit;
the pull-down node control circuit comprises a first pull-down node control transistor and a second pull-down node control transistor;
a control electrode of the first pull-down node control transistor and a first electrode of the first pull-down node control transistor are electrically connected with a power supply voltage end, and a second electrode of the first pull-down node control transistor is electrically connected with the pull-down node;
the control electrode of the second pull-down node control transistor is electrically connected with the pull-up node at the current stage, the first electrode of the second pull-down node control transistor is electrically connected with the pull-down node, and the second electrode of the second pull-down node control transistor is electrically connected with the second level end.
7. The shift register cell of claim 5, wherein the output circuit comprises an output transistor, an output pull-down transistor, and an output reset transistor, wherein,
the control electrode of the output transistor is electrically connected with the pull-up node of the current stage, the first electrode of the output transistor is electrically connected with the output clock signal end, and the second electrode of the output transistor is electrically connected with the gate drive signal output end;
a control electrode of the output pull-down transistor is electrically connected with the pull-down node, a first electrode of the output pull-down transistor is electrically connected with the gate drive signal output end, and a second electrode of the output pull-down transistor is electrically connected with the second level end;
the control electrode of the output reset transistor is electrically connected with the reset end, the first electrode of the output reset transistor is electrically connected with the grid drive signal output end, and the second electrode of the output reset transistor is electrically connected with the second level end.
8. A driving method of a shift register unit, applied to the shift register unit according to any one of claims 1 to 7, the driving method comprising:
and the output noise amplifying circuit controls to switch on or switch off the connection between the grid driving signal output end and the output clock signal end under the control of the potential of the pull-up node of the next adjacent stage.
9. The method of driving a shift register cell according to claim 8, wherein said shift register cell further comprises a pull-up noise-discharging terminal and a pull-up node noise-discharging circuit; the driving method of the shift register unit further includes:
the pull-up node noise amplifying circuit is controlled to be connected or disconnected between the pull-up node and the noise amplifying voltage end under the control of a pull-up noise amplifying control signal provided by the pull-up noise amplifying control end.
10. A gate drive circuit comprising a shift register cell according to any one of claims 1 to 7;
the shift register unit is electrically connected with the pull-up node of the current stage in the adjacent next-stage shift register unit, and the pull-up node of the current stage in the adjacent next-stage shift register unit is the adjacent next-stage pull-up node.
11. The gate drive circuit of claim 10, wherein the shift register cell further comprises a pull-up node noise-discharging circuit; the pull-up node noise amplifying circuit is electrically connected with the pull-up noise amplifying control end;
a pull-up node noise amplifying circuit included in the Nth-stage shift register unit is electrically connected with a grid driving signal output end of the (N +2) th-stage shift register unit; n is a positive integer.
12. A display device comprising the gate driver circuit according to claim 10 or 11.
13. The display device according to claim 12, wherein the display device includes two of the gate driver circuits; the display device further comprises a plurality of rows of gate lines;
the Nth-level grid driving signal output end of the first grid driving circuit is electrically connected with the 2N-1 th row of grid lines;
the Nth stage grid driving signal output end of the second grid driving circuit is electrically connected with the 2 Nth row of grid lines; n is a positive integer.
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1889190A (en) * | 2006-07-12 | 2007-01-03 | 友达光电股份有限公司 | Shift register |
| US20110075790A1 (en) * | 2009-09-25 | 2011-03-31 | Beijing Boe Optoelectronics Technology Co., Ltd. | Shift register and gate line driving device |
| CN202258264U (en) * | 2011-09-06 | 2012-05-30 | 北京京东方光电科技有限公司 | Shift register unit, gate driving device and applied liquid crystal display thereof |
| CN102651186A (en) * | 2011-04-07 | 2012-08-29 | 北京京东方光电科技有限公司 | Shift register and grid line driving device |
| CN105405387A (en) * | 2016-01-05 | 2016-03-16 | 京东方科技集团股份有限公司 | Shifting register unit, driving method thereof, gate drive circuit and display device |
| CN105869563A (en) * | 2016-05-30 | 2016-08-17 | 京东方科技集团股份有限公司 | GOA unit circuit and driving method thereof and GOA circuit |
| US20160300623A1 (en) * | 2015-04-10 | 2016-10-13 | Boe Technology Group Co., Ltd. | Shift register unit and driving method thereof, scan driving circuit and display device |
| CN108564980A (en) * | 2018-01-29 | 2018-09-21 | 京东方科技集团股份有限公司 | Shifting deposit unit and its driving method, gate driving circuit and display device |
-
2020
- 2020-01-20 CN CN202010064642.3A patent/CN111210752A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1889190A (en) * | 2006-07-12 | 2007-01-03 | 友达光电股份有限公司 | Shift register |
| US20110075790A1 (en) * | 2009-09-25 | 2011-03-31 | Beijing Boe Optoelectronics Technology Co., Ltd. | Shift register and gate line driving device |
| CN102651186A (en) * | 2011-04-07 | 2012-08-29 | 北京京东方光电科技有限公司 | Shift register and grid line driving device |
| CN202258264U (en) * | 2011-09-06 | 2012-05-30 | 北京京东方光电科技有限公司 | Shift register unit, gate driving device and applied liquid crystal display thereof |
| US20160300623A1 (en) * | 2015-04-10 | 2016-10-13 | Boe Technology Group Co., Ltd. | Shift register unit and driving method thereof, scan driving circuit and display device |
| CN105405387A (en) * | 2016-01-05 | 2016-03-16 | 京东方科技集团股份有限公司 | Shifting register unit, driving method thereof, gate drive circuit and display device |
| CN105869563A (en) * | 2016-05-30 | 2016-08-17 | 京东方科技集团股份有限公司 | GOA unit circuit and driving method thereof and GOA circuit |
| CN108564980A (en) * | 2018-01-29 | 2018-09-21 | 京东方科技集团股份有限公司 | Shifting deposit unit and its driving method, gate driving circuit and display device |
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