CN110111831B

CN110111831B - Shift register, grid drive circuit and display device

Info

Publication number: CN110111831B
Application number: CN201910336072.6A
Authority: CN
Inventors: 周洪波; 赖青俊; 伍黄尧; 沈柏平
Original assignee: Xiamen Tianma Microelectronics Co Ltd
Current assignee: Xiamen Tianma Microelectronics Co Ltd
Priority date: 2019-04-24
Filing date: 2019-04-24
Publication date: 2021-08-06
Anticipated expiration: 2039-04-24
Also published as: CN110111831A

Abstract

The invention discloses a shift register, a grid drive circuit and a display device, wherein the shift register comprises: the system comprises an output module, a node control module, a node charging module, a scanning control module and a reset module; the scanning control module is used for providing the signal of the forward scanning control signal end to the input node under the control of the signal of the forward scanning input signal end, or providing the signal of the reverse scanning control signal end to the input node under the control of the signal of the reverse scanning input signal end. Because the scanning control module is controlled by the input signal end, the scanning control module can enable the input node to be in a floating state during the non-scanning period, and further enable the first node to be in the floating state through the node charging module, so that the potential of the first node cannot leak electricity through the input node, and the potential of the first node is kept.

Description

Shift register, grid drive circuit and display device

Technical Field

The present invention relates to the field of display technologies, and in particular, to a shift register, a gate driving circuit and a display device.

Background

In a flat panel display panel, a gate-on signal is generally supplied to a gate of each Thin Film Transistor (TFT) of a pixel region through a gate driving circuit. The Gate driving Circuit may be formed on an Array substrate of the flat Panel display Panel through an Array process, i.e., a Gate Driver on Array (GOA) process, which not only saves cost, but also may achieve an aesthetic design of bilateral symmetry of the flat Panel display Panel (Panel), and simultaneously, may also save a Bonding area of the Gate Integrated Circuit (IC) and a wiring space of the Fan-out (Fan-out), thereby implementing a design of a narrow bezel.

As shown in fig. 1, a conventional gate driver circuit includes a plurality of cascaded shift registers: SR (1), SR (2) … SR (N), SR (N +1) … SR (N-1), SR (N) (N shift registers, N is more than or equal to 1 and less than or equal to N), wherein each shift register SR (N) is used for providing a grid opening signal for a grid line connected with a signal Output end Output _ N of the shift register SR (N) so as to open the TFT of the pixel region of the corresponding row. Except for the first stage shift register SR (1), the Input signal end Input _ n of the shift registers SR (n) of the other stages is respectively connected with the signal Output end Output _ n-1 of the shift register SR (n-1) of the previous stage. Each stage of shift register sr (n) includes a pull-up node for controlling the signal output terminal to output a gate-on signal, and when the potential of the pull-up node is further pulled up, the signal output terminal outputs the gate-on signal.

At present, in a touch display panel driven by time sharing for touch and display, i.e. a plurality of touch time periods are inserted in a time for displaying a frame of picture, and generally each touch time period needs a time interval of a certain duration, assuming that a touch time period enters after a gate-on signal is outputted from a signal output terminal of an nth-stage shift register, a potential of a pull-up node in an n + 1-stage shift register has already changed to a high level, because the time interval of the touch time period is long, during which a leakage occurs to the pull-up node in the n + 1-stage shift register through a TFT connected thereto, so that the potential of the pull-up node is reduced, and when the touch time period ends, the n + 1-stage shift register starts to operate, and because the potential of the pull-up node is attenuated, the gate-on signal outputted from the shift register is attenuated, in severe cases, the corresponding gate line cannot receive the scan signal, and the corresponding pixel cannot perform the display function, so that a dark line phenomenon that one line of pixels is not bright occurs, and the display quality is reduced.

Disclosure of Invention

In view of the above, embodiments of the present invention provide a shift register, a gate driving circuit and a display device to solve the problem of dark lines in a display image in the prior art.

The shift register provided by the embodiment of the invention comprises: the system comprises an output module, a node control module, a node charging module, a scanning control module and a reset module;

the output module is used for providing a signal of a first clock signal end to the grid signal output end under the control of a signal of a first node, or providing a signal of a first reference voltage end to the grid signal output end under the control of a signal of a second node;

the node control module is used for controlling the level of the signals of the first node and the second node to be opposite according to the signal of the first node or the signal of the second node;

the node charging module comprises a first control end and is used for providing a signal of an input node to the first node under the control of the signal of the first control end;

the scanning control module is used for providing a signal of a forward scanning control signal end to the input node under the control of a signal of a forward scanning input signal end, or providing a signal of a reverse scanning control signal end to the input node under the control of a signal of a reverse scanning input signal end;

the reset module comprises a reset control end, and is used for resetting the potential of the first node under the control of the reset control end and providing a signal of a second reference voltage end for the second node.

Correspondingly, an embodiment of the present invention further provides a gate driving circuit, including N cascaded shift registers according to any one of the shift registers described above, where N is an integer greater than 2.

Correspondingly, an embodiment of the present invention further provides a display device, including:

a display area and a non-display area;

the display area comprises a plurality of gate lines and a plurality of data lines which are insulated and intersected with the gate lines;

the non-display area includes the gate driving circuit provided in the embodiment of the present invention, and the gate signal output terminal of each shift register is electrically connected to one of the gate lines.

The invention has the following beneficial effects:

the shift register, the gate driving circuit and the display device provided by the embodiment of the invention, wherein the shift register comprises: the system comprises an output module, a node control module, a node charging module, a scanning control module and a reset module; the scanning control module is used for providing the signal of the forward scanning control signal end to the input node under the control of the signal of the forward scanning input signal end, or providing the signal of the reverse scanning control signal end to the input node under the control of the signal of the reverse scanning input signal end. Because the scanning control module is controlled by the input signal end, the scanning control module can enable the input node to be in a floating state during the non-scanning period, and further enable the first node to be in the floating state through the node charging module, so that the potential of the first node cannot leak electricity through the input node, and the potential of the first node is kept. When the shift register is recovered to the scanning period from the non-scanning period and normally works to output the scanning signal to the gate line, the output module can provide the signal of the first clock signal end to the gate signal output end under the control of the signal of the first node, so that the shift register normally outputs the scanning signal to the gate line, and therefore the problem of abnormal output signal when the shift register enters the scanning period again can be solved, and the dark line phenomenon can be improved.

Drawings

Fig. 1 is a schematic structural diagram of a conventional gate driving circuit;

FIG. 2 is a schematic structural diagram of a shift register according to an embodiment of the present invention;

FIG. 3 is a diagram illustrating a shift register according to another embodiment of the present invention;

FIG. 4 is a diagram illustrating a shift register according to another embodiment of the present invention;

FIG. 5 is a diagram illustrating a shift register according to another embodiment of the present invention;

FIG. 6 is a diagram illustrating a shift register according to another embodiment of the present invention;

FIG. 7 is a timing diagram of a shift register shown in FIG. 6;

FIG. 8 is a timing diagram of another circuit corresponding to the shift register shown in FIG. 6;

fig. 9 is a schematic structural diagram of a gate driving circuit according to an embodiment of the invention;

fig. 10 is a schematic structural diagram of a display device according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention clearer, the present invention will be described in further detail with reference to the accompanying drawings, and it is apparent that the described embodiments are only a part of the embodiments of the present invention, not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

The shapes and sizes of the various elements in the drawings are not to scale and are merely illustrative of the principles of the invention

As shown in fig. 2, a shift register according to an embodiment of the present invention includes: the system comprises an output module 03, a node control module 01, a node charging module 02, a scanning control module 04 and a reset module 05;

the output module 03 is configured to provide the signal of the first clock signal terminal CK1 to the gate signal output terminal GOUT under the control of the signal of the first node N1, or provide the signal of the first reference voltage terminal VGL to the gate signal output terminal GOUT under the control of the signal of the second node N2;

the node control module 01 is used for controlling the levels of the signals of the first node N1 and the second node N2 to be opposite according to the signal of the first node N1 or the signal of the second node N2;

the node charging module 02 includes a first control terminal SET, and the node charging module 02 is configured to provide a signal of an input node IN to the first node N1 under the control of the signal of the first control terminal SET;

the scan control module 04 is used for providing the signal of the forward scan control signal terminal U2D to the input node IN under the control of the signal of the forward scan input signal terminal INF, or providing the signal of the reverse scan control signal terminal D2U to the input node IN under the control of the signal of the reverse scan input signal terminal INB;

the reset module 05 includes a reset control terminal RST, and the reset module 05 is configured to reset the potential of the first node N1 under the control of the reset control terminal RST and provide the signal of the second reference voltage terminal VGH to the second node N2.

IN the shift register of the embodiment, the scan control module 04 is configured to provide the signal of the forward scan control signal terminal U2D to the input node IN under the control of the signal of the forward scan input signal terminal INF, or provide the signal of the reverse scan control signal terminal D2U to the input node IN under the control of the signal of the reverse scan input signal terminal INB, so that during the non-scan period, the scan control module 04 makes the input node IN a floating state under the control of the forward scan input signal terminal INF or the reverse scan input signal terminal INB, and further makes the first node N1 IN a floating state through the node charging module 02, so that the potential of the first node N1 is not leaked through the input node IN, and the potential of the first node N1 is maintained. When the shift register is restored from the non-scanning period to the scanning period and normally operates to output the scanning signal to the gate line, the output module 03 can provide the signal of the first clock signal terminal CK1 to the gate signal output terminal GOUT under the control of the signal of the first node N1, so that the shift register can normally output the scanning signal to the gate line, thereby improving the problem of abnormal output signal when the shift register enters the scanning period again and improving the dark line phenomenon.

In this embodiment, the non-scanning period of the shift register is a period during which the shift register suspends outputting the scanning signal to the gate line.

Specifically, in the display device, during the forward scanning, the forward scan input signal terminal INF of the first stage shift register is generally used for receiving the start signal, and the forward scan input signal terminals INF of the other shift registers except the first stage shift register are used for receiving the signal output from the gate signal output terminal GOUT of the previous shift register. In the reverse scan, the reverse scan input signal terminal INB of the last stage shift register is generally used for receiving the start signal, and the reverse scan input signal terminals INB of the other stages except the last stage shift register are used for receiving the signal output from the gate signal output terminal GOUT of the next stage shift register.

Optionally, in the shift register provided in the embodiment of the present invention, as shown in fig. 3, the shift register further includes a discharging module 06;

the discharging module 06 includes a discharging control terminal GAS, and the discharging module 06 is configured to provide the signal of the first reference voltage terminal VGL to the first node N1 and the second node N2, and provide the signal of the second reference voltage terminal VGH to the gate signal output terminal GOUT under the control of the discharging control terminal GAS.

In a specific implementation, the discharging module 06 provides the signal of the first reference voltage terminal VGL to the first node N1 and the second node N2 respectively under the control of the discharging control terminal GAS, so as to discharge the first node N1 and the second node N2 of the shift register, thereby achieving the internal discharging of the shift register. The discharging module 06 provides the signal of the second reference voltage terminal VGH to the gate signal output terminal GOUT under the control of the discharging control terminal GAS, and the gate signal output terminal GOUT is generally connected to a row of pixels, so that the discharging of the pixels in the corresponding row can be realized.

Optionally, in the shift register provided in the embodiment of the present invention, as shown in fig. 4, a reset control module 07 is further included;

the reset control module 07 is used for providing the signal of the second clock signal terminal CK2 to the reset control terminal RST under the control of the signal of the normal scan control signal terminal U2D, or providing the signal of the third clock signal terminal CK3 to the reset control terminal RST under the control of the signal of the reverse scan control signal terminal D2U. Therefore, the shift register can be further ensured to be timely reset after the grid signal output end GOUT outputs a grid signal.

The present invention will be described in detail with reference to specific examples. It should be noted that the present embodiment is intended to better explain the present invention, but not to limit the present invention.

In a specific implementation, a first pole of the transistor may be used as a source and a second pole may be used as a drain according to the type of the transistor and a signal of a gate thereof; or, conversely, the first pole of the transistor is used as the drain thereof, and the second pole is used as the source thereof, which are not specifically distinguished herein.

In general, transistors are classified into N-type transistors and P-type transistors. The N-type transistor is switched on under the control of a high level signal and switched off under the control of a low level signal; the P-type transistor is turned on under the control of a low level signal and turned off under the control of a high level signal.

Alternatively, in the shift register provided in the embodiment of the present invention, as shown in fig. 5 and 6,

the node control module 01 includes a first transistor T1, a second transistor T2, and a third transistor T3;

a gate of the first transistor T1 is connected to the second node N2, a first pole of the first transistor T1 is connected to the first reference voltage terminal VGL, and a second pole of the first transistor T1 is connected to the first node N1;

a gate of the second transistor T2 is connected to the input node IN, a first pole of the second transistor T2 is connected to the first reference voltage terminal VGL, and a second pole of the second transistor T2 is connected to the second node N2;

a gate of the third transistor T3 is connected to the first node N1, a first pole of the third transistor T3 is connected to the first reference voltage terminal VGL, and a second pole of the third transistor T3 is connected to the second node N2.

In the present embodiment, the second node N2 is used to control the first transistor T1 to be turned on or off, and when the first transistor T1 is turned on, a signal of the first reference voltage terminal VGL may be transmitted to the first node N1; the input node IN is used for controlling the on/off of the second transistor T2, and when the second transistor T2 is turned on, the signal of the first reference voltage terminal VGL can be transmitted to the second node N2; the first node N1 is used to control the third transistor T3 to be turned on or off, and when the third transistor T3 is turned on, a signal of the first reference voltage terminal VGL may be transmitted to the second node N2.

Optionally, in the shift register provided in the embodiment of the present invention, as shown in fig. 5 and fig. 6, the node charging module 02 includes a fourth transistor T4;

a gate of the fourth transistor T4 is connected to the first control terminal SET, a first pole of the fourth transistor T4 is connected to the input node IN, and a second pole of the fourth transistor T4 is connected to the first node N1.

IN an embodiment, the first control terminal SET is used to control the fourth transistor T4 to be turned on or off, and when the fourth transistor T4 is turned on, the signal input to the node IN may be transmitted to the first node N1.

Optionally, in the shift register provided in the embodiment of the present invention, as shown in fig. 4 and 5, the output module 03 includes a fifth transistor T5, a sixth transistor T6, a first capacitor C1, and a second capacitor C2;

a gate of the fifth transistor T5 is connected to the second node N2, a first pole of the fifth transistor T5 is connected to the first reference voltage terminal VGL, and a second pole of the fifth transistor T5 is connected to the gate signal output terminal GOUT;

a gate of the sixth transistor T6 is connected to the first node N1, a first pole of the sixth transistor T6 is connected to the first clock signal terminal CK1, and a second pole of the sixth transistor T6 is connected to the gate signal output terminal GOUT;

a first pole of the first capacitor C1 is connected to the first reference voltage terminal VGL, and a second pole is connected to the second node N2;

a first pole of the second capacitor C2 is connected to the first node N1, and a second pole is connected to the gate signal output terminal GOUT.

In the present embodiment, the second node N2 is used to control the fifth transistor T5 to be turned on or off, and when the fifth transistor T5 is turned on, the signal of the first reference voltage terminal VGL can be transmitted to the gate signal output terminal GOUT; the first node N1 is used for controlling the sixth transistor T6 to be turned on or off, and when the sixth transistor T6 is turned on, the signal of the first clock signal terminal CK1 can be transmitted to the gate signal output terminal GOUT; the first capacitor C1 and the second capacitor C2 have a coupling effect, and can be used for stabilizing the potentials of the first node N1 and the second node N2. In this embodiment, since the node control module 01 can control the potentials of the first node N1 and the second node N2 to be opposite, so that one of the sixth transistor T6 controlled by the first node N1 and the fifth transistor T5 controlled by the second node N2 is turned on and the other is turned off, and accordingly, the gate signal output terminal GOUT outputs the signal of the first reference voltage terminal VGL or the signal of the first clock signal terminal CK1, thereby ensuring that the gate signal output terminal GOUT does not simultaneously output the signal of the first reference voltage terminal VGL and the signal of the first clock signal terminal CK 1.

Alternatively, in the shift register provided in the embodiment of the present invention, as shown in fig. 5 and 6, the scan control module 04 includes a seventh transistor T7 and an eighth transistor T8;

a gate of the seventh transistor T7 is connected to the positive scan input signal terminal INF, a first pole of the seventh transistor T7 is connected to the positive scan control signal terminal U2D, and a second pole of the seventh transistor T7 is connected to the input node IN;

the gate of the eighth transistor T8 is connected to the reverse-scan input signal terminal INB, the first pole of the eighth transistor T8 is connected to the reverse-scan control signal terminal D2U, and the second pole of the eighth transistor T8 is connected to the input node IN.

IN the present embodiment, the positive scan input signal terminal INF is used to control the seventh transistor T7 to be turned on or off, and when the seventh transistor T7 is turned on, the signal of the positive scan control signal terminal U2D may be transmitted to the input node IN; the inverse scan input signal terminal INB is used to control the eighth transistor T8 to be turned on or off, and when the eighth transistor T8 is turned on, the signal of the inverse scan control signal terminal D2U may be transmitted to the input node IN. The seventh transistor T7 or the eighth transistor T8 is turned on only when there is an input signal, that is, the input node IN is IN a floating state at other times than when there is an input signal at the forward-scan input signal terminal INF or the reverse-scan input signal terminal INB, which is equivalent to blocking the leakage of the first node N1 IN the direction of the input node IN, so that the potential of the first node N1 can be maintained.

Alternatively, in the shift register provided in the embodiment of the present invention, as shown in fig. 5 and 6, the reset module 05 includes a ninth transistor T9 and a tenth transistor T10;

a gate of the ninth transistor T9 is connected to the reset control terminal RST, a first pole of the ninth transistor T9 is connected to the input node IN, and a second pole of the ninth transistor T9 is connected to the first node N1;

a gate of the tenth transistor T10 is connected to the reset control terminal RST, a first pole of the tenth transistor T10 is connected to the second reference voltage terminal VGH, and a second pole of the tenth transistor T10 is connected to the second node N2.

IN the present embodiment, the reset control terminal RST is used to control the ninth transistor T9 to be turned on or off, and when the ninth transistor T9 is turned on, the potential of the input node IN may be transmitted to the first node N1; the reset control terminal RST is used to control the tenth transistor T10 to be turned on or off, and when the tenth transistor T10 is turned on, a signal of the second reference voltage terminal VGH may be transmitted to the second node N2.

Optionally, in the shift register provided in the embodiment of the present invention, the channel width-to-length ratio of the tenth transistor T10 is greater than the channel width-to-length ratio of the second transistor T2 and the channel width-to-length ratio of the third transistor T3, respectively. This is for the purpose that the potential of the second node N2 is controlled by the tenth transistor T10 during the reset phase, thereby ensuring that the potential of the second node N2 is the potential of the second reference voltage terminal VGH.

Alternatively, in the shift register provided in the embodiment of the present invention, as shown in fig. 5 and 6, the reset control module 07 includes an eleventh transistor T11 and a twelfth transistor T12;

a gate of the eleventh transistor T11 is connected to the positive scan control signal terminal U2D, a first pole of the eleventh transistor T11 is connected to the second clock signal terminal CK2, and a second pole of the eleventh transistor T11 is connected to the reset control terminal RST;

a gate of the twelfth transistor T12 is connected to the reverse scan control signal terminal D2U, a first pole of the twelfth transistor T12 is connected to the third clock signal terminal CK3, and a second pole of the twelfth transistor T12 is connected to the reset control terminal RST.

In the present embodiment, the positive scan control signal terminal U2D is used to control the turn-on or turn-off of the eleventh transistor T11, and when the eleventh transistor T11 is turned on, the signal of the second clock signal terminal CK2 may be transmitted to the reset control terminal RST; the reverse scan control signal terminal D2U is used to control the twelfth transistor T12 to be turned on or off, and when the twelfth transistor T12 is turned on, the signal of the third clock signal terminal CK3 may be transmitted to the reset control terminal RST.

the discharging module 06 includes a thirteenth transistor T13, a fourteenth transistor T14, and a fifteenth transistor T15;

a gate of the thirteenth transistor T13 is connected to the discharge control terminal GAS, a first pole of the thirteenth transistor T13 is connected to the first reference voltage terminal VGL, and a second pole of the thirteenth transistor T13 is connected to the first node N1;

a gate of the fourteenth transistor T14 is connected to the discharge control terminal GAS, a first pole of the fourteenth transistor T14 is connected to the first reference voltage terminal VGL, and a second pole of the fourteenth transistor T14 is connected to the second node N2;

a gate of the fifteenth transistor T15 is connected to the discharge control terminal GAS, a first pole of the fifteenth transistor T15 is connected to the second reference voltage terminal VGH, and a second pole of the fifteenth transistor T15 is connected to the gate signal output terminal GOUT.

In the present embodiment, the discharge control terminal GAS is configured to simultaneously control turning on or off of the thirteenth transistor T13, the fourteenth transistor T14, and the fifteenth transistor T15, when the thirteenth transistor T13 is turned on, the signal of the first reference voltage terminal VGL may be transmitted to the first node N1, when the fourteenth transistor T14 is turned on, the signal of the first reference voltage terminal VGL may be transmitted to the second node N2, and when the fifteenth transistor T15 is turned on, the signal of the second reference voltage terminal VGH may be transmitted to the gate signal output terminal GOUT.

Optionally, in the shift register provided in the embodiment of the present invention, as shown in fig. 6, a sixteenth transistor T16 is further included;

the first node N1 is divided into an a sub-node N1a and a b sub-node N1b by a sixteenth transistor T16;

a first pole of the sixteenth transistor T16 is connected to the first node N1a, a second pole of the sixteenth transistor T16 is connected to the second node N1b, a gate of the sixteenth transistor T16 is connected to the second reference voltage terminal VGH, and a signal of the second reference voltage terminal VGH controls the sixteenth transistor T16 to be turned on.

In the present embodiment, the second reference voltage terminal VGH controls the sixteenth transistor T16 to be turned on, so that the first sub-node N1a and the second sub-node N1b are turned on.

The above is merely an example of the specific structure of each block in the shift register, and in the specific implementation, the specific structure of each block is not limited to the above structure provided in the embodiment of the present invention, and may be other structures known to those skilled in the art, and is not limited herein.

It should be noted that, in the shift register provided in the embodiment of the present invention, when all the transistors are N-type transistors, the signal of the first reference voltage terminal VGL is a low level signal, and the signal of the second reference voltage terminal VGH is a high level signal; when all the transistors are P-type transistors, the signal of the first reference voltage terminal VGL is a high level signal, and the signal of the second reference voltage terminal VGH is a low level signal.

In the shift register according to the embodiment of the invention, the signals of the first clock signal terminal CK1, the second clock signal terminal CK2, and the third clock signal terminal CK3 are all pulse signals, and the signal of the first control terminal SET may also be a pulse signal.

Next, the operation process of the shift register according to the embodiment of the present invention when performing forward scan will be described with reference to the circuit timing diagrams shown in fig. 7 and 8, taking the shift register shown in fig. 6 as an example. In the following description, 1 represents a high level, and 0 represents a low level. It should be noted that 1 and 0 are logic potentials, which are only used to better explain the specific operation of the embodiment of the present invention, and not specific voltage values.

Specifically, taking forward direction scanning as an example, when the shift register is always in the scanning period, the corresponding timing sequence is shown in fig. 7.

In the forward direction scan, D2U is 0, and the twelfth transistor T12 is turned off; GAS is 0, and the thirteenth transistor T13, the fourteenth transistor T14, and the fifteenth transistor T15 are all turned off; U2D is equal to 1, and the eleventh transistor T11 is turned on.

In the stage t1 (i.e., the input stage), INF is 1, SET is 1, CK1 is 0, CK2 is 0, and CK3 is 0.

The eighth transistor T8 is turned off by the signal of the reverse scan input signal terminal INB, the fourth transistor T4, the seventh transistor T7 and the sixteenth transistor T16 are turned on, and the high level signal of the positive scan control signal terminal U2D is transmitted to the input node IN through the seventh transistor T7, so that the potential of the input node IN is high. The high potential of the input node IN is transmitted to the first sub-node N1a through the fourth transistor T4, and then transmitted to the second sub-node N1b through the sixteenth transistor T16; therefore, the first node N1 is at a high potential, the third transistor T3 and the sixth transistor T6 are turned on under the control of the first node N1, the low level signal of the first reference voltage terminal VGL is transmitted to the second node N2 through the third transistor T3, and the second node N2 is at a low potential. The low level signal of the first clock signal terminal CK1 is transmitted to the gate signal output terminal GOUT through the sixth transistor T6, so that the voltage level of the gate signal output terminal GOUT is low. The input node IN controls the second transistor T2 to be turned on, and the low level signal of the first reference voltage terminal VGL is transmitted to the second node N2 through the second transistor T2, so as to further ensure that the potential of the second node N2 is at a low level. Under the control of the second node N2, the first transistor T1 and the fifth transistor T5 are turned off. The low level signal of the second clock signal terminal CK2 is transmitted to the reset control terminal RST through the eleventh transistor T11, the potential of the reset control terminal RST is low, and the reset control terminal RST controls the ninth transistor T9 and the tenth transistor T10 to be turned off. In this stage, the potentials of the first node N1 and the second node N2 are opposite.

At stage t2, INF is 0, SET is 0, CK1 is 0, CK2 is 0, and CK3 is 1.

The signal of the inverse scan input signal terminal INB controls the eighth transistor T8 to be turned off. The seventh transistor T7 and the fourth transistor T4 are turned off, the first sub-node N1a is in a floating state, the potential of the first sub-node N1a is still kept at a high potential, the potential of the second sub-node N1b is still at a high potential through the sixteenth transistor T16, the first sub-node N1a controls the third transistor T3 to be turned on, the low level signal of the first reference voltage terminal VGL is transmitted to the second node N2 through the third transistor T3, and the potential of the second node N2 is at a low potential. The second node N1b controls the sixth transistor T6 to be turned on, and the low level signal of the first clock signal terminal CK1 is transmitted to the gate signal output terminal GOUT through the sixth transistor T6, so that the voltage level of the gate signal output terminal GOUT is still at a low level. The input node IN controls the second transistor T2 to be turned on, and the low level signal of the first reference voltage terminal VGL is transmitted to the second node N2 through the second transistor T2, so as to further ensure that the potential of the second node N2 is at a low level. Under the control of the second node N2, the first transistor T1 and the fifth transistor T5 are turned off. The low level signal of the second clock signal terminal CK2 is transmitted to the reset control terminal RST through the eleventh transistor T11, the potential of the reset control terminal RST is low, and the reset control terminal RST controls the ninth transistor T9 and the tenth transistor T10 to be turned off. In this stage, the potentials of the first node N1 and the second node N2 are opposite.

In the stage t3 (i.e., the output stage), INF is 0, SET is 0, CK1 is 1, CK2 is 0, and CK3 is 0.

The eighth transistor T8 is turned off by a signal of the anti-scan input signal terminal INB, the seventh transistor T7 and the fourth transistor T4 are turned off, the first sub-node N1a is in a floating state, the potential of the first sub-node N1a is still kept at a high potential, the potential of the second sub-node N1b is still kept at a high potential through the sixteenth transistor T16, the first sub-node N1a controls the third transistor T3 to be turned on, a low level signal of the first reference voltage terminal VGL is transmitted to the second node N2 through the third transistor T3, and the potential of the second node N2 is at a low potential. The second node N1b controls the sixth transistor T6 to be turned on, and the high level signal of the first clock signal terminal CK1 is transmitted to the gate signal output terminal GOUT through the sixth transistor T6, so that the potential of the gate signal output terminal GOUT becomes high. Due to the bootstrap action of the second capacitor C2, the potential of the b sub-node N1b is further pulled high, thereby ensuring the stability of the output. The input node IN controls the second transistor T2 to be turned on, and the low level signal of the first reference voltage terminal VGL is transmitted to the second node N2 through the second transistor T2, so as to further ensure that the potential of the second node N2 is at a low level. Under the control of the second node N2, the first transistor T1 and the fifth transistor T5 are turned off. The low level signal of the second clock signal terminal CK2 is transmitted to the reset control terminal RST through the eleventh transistor T11, the potential of the reset control terminal RST is still low, and the reset control terminal RST controls the ninth transistor T9 and the tenth transistor T10 to be turned off. In this stage, the potentials of the first node N1 and the second node N2 are opposite.

In the t4 phase (i.e., the reset phase), INF is 0, SET is 0, CK1 is 0, CK2 is 1, and CK3 is 0.

The second clock signal terminal CK2 controls the eleventh transistor T11 to be turned on, the high level signal of the positive scan control signal terminal U2D is transmitted to the reset control terminal RST through the eleventh transistor T11, the reset control terminal RST controls the ninth transistor T9 and the tenth transistor T10 to be turned on, the high level signal of the second reference voltage terminal VGH is transmitted to the second node N2 through the tenth transistor T10, the potential of the second node N2 becomes high, the second node N2 controls the fifth transistor T5 and the first transistor T1 to be turned on, the low level signal of the first reference voltage terminal VGL is transmitted to the first sub-node N1a through the first transistor T1, the potential of the first sub-node N1a becomes low, and then is transmitted to the second sub-node N1b through the sixteenth transistor T16, and the potential of the second sub-node N1b becomes low. The first sub-node N1a controls the third transistor T3 to be turned off, and the second sub-node N1b controls the sixth transistor T6 to be turned off. The low level signal of the first reference voltage terminal VGL is transmitted to the gate signal output terminal GOUT through the fifth transistor T5, and the potential of the gate signal output terminal GOUT becomes a low level. The positive scan input signal terminal INF controls the seventh transistor T7 to be turned off, the low level signal of the first sub-node N1a is transmitted to the input node IN through the ninth transistor T9, the potential of the input node IN becomes the low level, and the first control terminal SET controls the fourth transistor T4 to be turned off. In this stage, the potentials of the first node N1 and the second node N2 are opposite.

After the period t4, until the positive scan input signal is received again, the potential of the first node N1 is kept high, the potential of the second node N2 is kept low, and the potential of the gate signal output terminal GOUT is kept low.

Specifically, when the shift register is restored from the non-scanning period to the scanning period, the corresponding timing is as shown in fig. 8.

the working principle of the stages t1, t2, t3 and t4 is the same as that of the stages t1, t2, t3 and t4 in fig. 7, and is not described herein again.

At stage t0 (i.e., the non-scanning stage). INF is 0, SET is 0, CK1 is 0, CK2 is 0, CK3 is 0, and CK4 is 0.

The seventh transistor T7 and the fourth transistor T4 are turned off, the first sub-node N1a is in a floating state, the potential of the first sub-node N1a is still kept at a high potential, the potential of the second sub-node N1b is still at a high potential through the sixteenth transistor T16, the first sub-node N1a controls the third transistor T3 to be turned on, the low level signal of the first reference voltage terminal VGL is transmitted to the second node N2 through the third transistor T3, and the potential of the second node N2 is at a low potential. The second node N1b controls the sixth transistor T6 to be turned on, and the low level signal of the first clock signal terminal CK1 is transmitted to the gate signal output terminal GOUT through the sixth transistor T6, so that the voltage level of the gate signal output terminal GOUT is still at a low level. Under the control of the second node N2, the first transistor T1 and the fifth transistor T5 are turned off. The input node IN controls the second transistor T2 to be turned off, the low level signal of the second clock signal terminal CK2 is transmitted to the reset control terminal RST through the eleventh transistor T11, the potential of the reset control terminal RST is still low, and the reset control terminal RST controls the ninth transistor T9 and the tenth transistor T10 to be turned off. In this stage, the potentials of the first node N1 and the second node N2 are opposite.

At this stage, since both the seventh transistor T7 and the eighth transistor T8 are IN the off state, the input node IN is IN the floating state, and the fourth transistor T4 is IN the off state, so that the leakage of the first node N1 IN the direction of the fourth transistor T4 is blocked, and the potential of the first node N1 can be maintained. When the shift register is restored from the non-scanning period to the scanning period and normally operates to output the scanning signal to the gate line, the output module 03 can provide the signal of the first clock signal terminal CK1 to the gate signal output terminal GOUT under the control of the signal of the first node N1, so that the shift register can normally output the scanning signal to the gate line, thereby improving the problem of abnormal output signal when the shift register enters the scanning period again and improving the dark line phenomenon.

In the implementation, the operation principle of the shift register in the backward scan is similar to that in the forward scan, and will not be described in detail here.

Based on the same inventive concept, an embodiment of the present invention further provides a gate driving circuit, including N cascaded shift registers according to any one of the above embodiments of the present invention, where N is a positive integer greater than 2. The gate driving circuit provided by the embodiment can be applied to a display panel to drive a plurality of gate lines in the display panel.

Optionally, as shown in fig. 9, the positive scan input signal terminal INF of the 1 st stage shift register is coupled to the positive scan frame trigger signal terminal STVF; the positive scan input signal terminal INF of the nth stage shift register is coupled to the gate signal output terminal GOUT of the (n-1) th stage shift register, except for the 1 st stage shift register; the positive scanning input signal end INF of the Nth stage shift register is coupled with the grid signal output end GOUT of the N-1 th stage shift register; wherein N is an integer greater than or equal to 1 and less than or equal to N-1. This can realize forward scan driving.

Alternatively, as shown in fig. 9, in the gate driving circuit, the anti-scan input signal terminal INB of the nth stage shift register is coupled to the anti-scan frame trigger signal terminal STVB; the reverse scan input signal terminal INB of the (N-1) th stage shift register is coupled to the gate signal output terminal GOUT of the nth stage shift register, except for the nth stage shift register; the inverse scan input signal terminal INB of the 1 st stage shift register is coupled to the gate signal output terminal GOUT of the 2 nd stage shift register. This enables reverse scan driving.

Further, in order to switch between the forward scan mode and the reverse scan mode, in the specific implementation, as shown in fig. 9, the forward scan input signal terminal INF of the 1 st stage shift register is coupled to the forward scan frame trigger signal terminal STVF; the positive scan input signal terminal INF of the nth stage shift register is coupled to the gate signal output terminal GOUT of the (n-1) th stage shift register, except for the 1 st stage shift register; the positive scan input signal terminal INF of the nth stage shift register is coupled to the gate signal output terminal GOUT of the N-1 th stage shift register. The inverse scan input signal terminal INB of the nth stage shift register is coupled to the inverse scan frame trigger signal terminal STVB; the reverse scan input signal terminal INB of the (N-1) th stage shift register is coupled to the gate signal output terminal GOUT of the nth stage shift register, except for the nth stage shift register; the inverse scan input signal terminal INB of the 1 st stage shift register is coupled to the gate signal output terminal GOUT of the 2 nd stage shift register. This allows switching between forward and reverse scanning.

Further, in the gate driving circuit provided in the embodiment of the present invention, as shown in fig. 9, the gate driving circuit further includes 4 clock signal lines: clk1, clk2, clk3 and clk4, 4 clock signal lines are respectively connected to each stage of the shift register.

Specifically, the specific structure of each shift register in the gate driving circuit is the same as that of the shift register of the present invention in function and structure, and repeated descriptions are omitted.

Based on the same inventive concept, the present invention further provides a display device, please refer to fig. 9 and fig. 10 in combination, including: a display area AA and a non-display area BB; the display area AA comprises a plurality of gate lines G and a plurality of data lines S which are insulated and intersected with the gate lines G; the non-display area BB includes a driving circuit gr according to any of the above embodiments of the present invention, and the gate signal output terminal GOUT of each shift register is electrically connected to one gate line G.

In particular implementations, the display device may include 2 driver circuits in implementations of the invention. Alternatively, as shown in fig. 10, one shift register in each gate driving circuit is connected to one gate line in the display panel, and the shift register of the same stage in the 2 gate driving circuits is connected to the same gate line. Alternatively, 1 driving circuit is connected to the gate lines of the odd-numbered rows in the display panel, and another 1 driving circuit is connected to the gate lines of the even-numbered rows in the display panel.

In particular implementations, a display device may include 1 driver circuit in implementations of the invention.

The display device provided in this embodiment may be an array substrate, or may be a terminal display device, such as a mobile phone, a computer, a television, or other display devices with a display function, which is not limited in this respect. The display device provided by the embodiment of the present invention has the beneficial effects of the driving circuit provided by the embodiment of the present invention, and reference may be made to the above embodiments specifically. For the specific description of the driving circuit, the detailed description of the embodiment is omitted here.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. A shift register is characterized in that a plurality of shift registers are arranged,

the method comprises the following steps: the system comprises an output module, a node control module, a node charging module, a scanning control module and a reset module;

2. The shift register of claim 1,

the device also comprises a discharging module;

the discharging module comprises a discharging control end, and is used for respectively providing the signals of the first reference voltage end to the first node and the second node and providing the signals of the second reference voltage end to the grid signal output end under the control of the discharging control end.

3. The shift register of claim 1,

the device also comprises a reset control module;

the reset control module is used for providing a signal of a second clock signal end to the reset control end under the control of a signal of the forward scanning control signal end, or providing a signal of a third clock signal end to the reset control end under the control of a signal of the reverse scanning control signal end.

4. The shift register of claim 1,

the node control module comprises a first transistor, a second transistor and a third transistor;

a gate of the first transistor is connected to the second node, a first pole of the first transistor is connected to the first reference voltage terminal, and a second pole of the first transistor is connected to the first node;

a gate of the second transistor is connected to the input node, a first pole of the second transistor is connected to the first reference voltage terminal, and a second pole of the second transistor is connected to the second node;

a gate of the third transistor is coupled to the first node, a first pole of the third transistor is coupled to the first reference voltage terminal, and a second pole of the third transistor is coupled to the second node.

5. The shift register of claim 1,

the node charging module comprises a fourth transistor;

a gate of the fourth transistor is connected to the first control terminal, a first pole of the fourth transistor is connected to the input node, and a second pole of the fourth transistor is connected to the first node.

6. The shift register of claim 1,

the output module comprises a fifth transistor, a sixth transistor, a first capacitor and a second capacitor;

a gate of the fifth transistor is connected to the second node, a first pole of the fifth transistor is connected to the first reference voltage terminal, and a second pole of the fifth transistor is connected to the gate signal output terminal;

a gate of the sixth transistor is connected to the first node, a first pole of the sixth transistor is connected to the first clock signal terminal, and a second pole of the sixth transistor is connected to the gate signal output terminal;

a first pole of the first capacitor is connected with the first reference voltage end, and a second pole of the first capacitor is connected with the second node;

and the first pole of the second capacitor is connected with the first node, and the second pole of the second capacitor is connected with the grid signal output end.

7. The shift register of claim 1,

the scanning control module comprises a seventh transistor and an eighth transistor;

a gate of the seventh transistor is connected to the positive scan input signal terminal, a first pole of the seventh transistor is connected to the positive scan control signal terminal, and a second pole of the seventh transistor is connected to the input node;

the gate of the eighth transistor is connected to the reverse-scan input signal terminal, the first pole of the eighth transistor is connected to the reverse-scan control signal terminal, and the second pole of the eighth transistor is connected to the input node.

8. The shift register of claim 4,

the reset module comprises a ninth transistor and a tenth transistor;

a gate of the ninth transistor is connected to the reset control terminal, a first pole of the ninth transistor is connected to the input node, and a second pole of the ninth transistor is connected to the first node;

a gate of the tenth transistor is connected to the reset control terminal, a first pole of the tenth transistor is connected to the second reference voltage terminal, and a second pole of the tenth transistor is connected to the second node.

9. The shift register of claim 8,

the tenth transistor has a channel width-to-length ratio larger than that of the second transistor and that of the third transistor, respectively.

10. The shift register of claim 3,

the reset control module comprises an eleventh transistor and a twelfth transistor;

a gate of the eleventh transistor is connected to the positive scan control signal terminal, a first pole of the eleventh transistor is connected to the second clock signal terminal, and a second pole of the eleventh transistor is connected to the reset control terminal;

the grid electrode of the twelfth transistor is connected with the reverse scanning control signal end, the first pole of the twelfth transistor is connected with the third clock signal end, and the second pole of the twelfth transistor is connected with the reset control end.

11. The shift register of claim 2,

the discharge module comprises a thirteenth transistor, a fourteenth transistor and a fifteenth transistor;

a gate of the thirteenth transistor is connected to the discharge control terminal, a first pole of the thirteenth transistor is connected to the first reference voltage terminal, and a second pole of the thirteenth transistor is connected to the first node;

a gate of the fourteenth transistor is connected to the discharge control terminal, a first pole of the fourteenth transistor is connected to the first reference voltage terminal, and a second pole of the fourteenth transistor is connected to the second node;

the gate of the fifteenth transistor is connected to the discharge control terminal, the first pole of the fifteenth transistor is connected to the second reference voltage terminal, and the second pole of the fifteenth transistor is connected to the gate signal output terminal.

12. The shift register of claim 1,

a sixteenth transistor;

the first node is divided into an A sub-node and a B sub-node by the sixteenth transistor;

a first pole of the sixteenth transistor is connected to the first node, a second pole of the sixteenth transistor is connected to the second node, a gate of the sixteenth transistor is connected to the second reference voltage terminal, and a signal of the second reference voltage terminal controls the sixteenth transistor to be turned on.

13. A gate driving circuit is characterized in that,

a shift register as claimed in any one of claims 1 to 12 comprising N cascades, wherein N is an integer greater than 2.

14. A display device, comprising:

a display area and a non-display area;

the non-display region includes the gate driving circuit as claimed in claim 13, the gate signal output terminal of each of the shift registers being electrically connected to one of the gate lines.