CN111200006B - Lateral double-diffusion metal oxide semiconductor field effect transistor and preparation method thereof - Google Patents

Lateral double-diffusion metal oxide semiconductor field effect transistor and preparation method thereof Download PDF

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CN111200006B
CN111200006B CN201811377880.9A CN201811377880A CN111200006B CN 111200006 B CN111200006 B CN 111200006B CN 201811377880 A CN201811377880 A CN 201811377880A CN 111200006 B CN111200006 B CN 111200006B
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metal
region
drift region
gate structure
drain region
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CN111200006A (en
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高桦
孙贵鹏
罗泽煌
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CSMC Technologies Fab2 Co Ltd
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CSMC Technologies Fab2 Co Ltd
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66681—Lateral DMOS transistors, i.e. LDMOS transistors
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    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1041—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface
    • H01L29/1045—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a non-uniform doping structure in the channel region surface the doping structure being parallel to the channel length, e.g. DMOS like

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Abstract

The present application relates to an LDMOS comprising: a semiconductor substrate having a first conductivity type; a drift region having a second conductivity type formed on a surface layer of the semiconductor substrate; the gate structure is arranged on the surface of the semiconductor substrate and covers part of the surface of the drift region; the source region and the drain region are of a second conductivity type and are respectively formed at two sides of the gate structure, the drain region is formed in the drift region at one side far away from the gate structure, and the source region is formed in the substrate and is connected with the gate structure; the metal silicide barrier layer is formed on the drift region between the grid structure and the drain region; the oxide layer is formed on the metal silicide barrier layer; and the metal field plate is formed on the oxide layer and comprises a plurality of metal sections which are arranged from the grid structure to the drain region direction at intervals. The LDMOS is formed with segmented metal field plates, the potential of each metal field plate is adjusted, and the breakdown voltage of the device can be enhanced. The application also relates to a preparation method of the LDMOS.

Description

Lateral double-diffusion metal oxide semiconductor field effect transistor and preparation method thereof
Technical Field
The invention relates to the field of semiconductors, in particular to a semiconductor device and a manufacturing method of the semiconductor device.
Background
In a Lateral Double-diffused metal oxide semiconductor field effect transistor (LDMOS for short), in order to make the LDMOS have a better voltage withstanding characteristic and a lower on-resistance, a field plate is usually formed on the surface layer of a drift region to replace a shallow trench isolation structure in the drift region to regulate and control an electric field below the drift region. Meanwhile, under high operating voltage, in order to make the surface electric field distribution of the drift region more uniform, a step field plate or an extended field plate is generally formed. However, in order to form a step field plate or an extended field plate, multiple times of photoetching are required in the process, so that the process is more complicated and the process cost is increased, and the thickness requirement of a dielectric layer from the surface of the device to an electrode leading-out layer of the device is limited, so that the structure is commonly used in discrete devices. For the BCD (Bipolar-CMOS-DMOS) process platform, the structure is rarely adopted to improve the voltage resistance and the surface electric field.
Disclosure of Invention
Therefore, a new lateral double-diffused metal oxide semiconductor field effect transistor and a method for manufacturing the lateral double-diffused metal oxide semiconductor field effect transistor are needed to be provided for solving the problem that the process of the LDMOS field plate is complex.
A lateral double diffused metal oxide semiconductor field effect transistor, comprising:
a semiconductor substrate having a first conductivity type;
the drift region is of the second conduction type and is formed on the surface layer of the semiconductor substrate;
the gate structure is arranged on the semiconductor substrate and covers part of the surface of the drift region;
the source region and the drain region are of a second conductivity type and are respectively formed on two sides of the grid structure, the drain region is formed in the drift region and is far away from the grid structure, and the source region is formed in the substrate and is connected with the grid structure;
the metal silicide barrier layer is formed on the drift region between the grid structure and the drain region;
the oxide layer is formed on the metal silicide barrier layer;
and the metal field plate is formed on the oxide layer and comprises a plurality of metal sections which are arranged from the grid structure to the drain region direction at intervals.
The transverse double-diffusion metal oxide semiconductor field effect transistor comprises a metal field plate arranged above a drift region, wherein an oxide layer and a metal silicide barrier layer are arranged below the metal field plate, and the surface electric field of the drift region can be integrally regulated and controlled by regulating the thickness of the oxide layer and the thickness of the metal silicide barrier layer. Meanwhile, the metal field plate comprises a plurality of metal sections which are arranged at intervals, the metal sections are not connected with each other, and different voltages can be connected to the metal sections, so that the potentials of the metal sections are different, different intensities of the drift region can be adjusted according to the electric field distribution condition of the drift region, the surface electric field distribution of the drift region is more uniform, and the reverse breakdown voltage of the LDMOS is greatly improved. Meanwhile, the segmented metal segment is formed, the device preparation process can be completed only by one-time photoetching, and the process is simple and the cost is low.
In one embodiment, the metal silicide blocking layer formed on the drift region between the gate structure and the drain region further extends to the gate structure;
the plurality of metal sections arranged from the grid structure to the drain region at intervals comprise metal sections arranged on the grid structure and the drift region in a spanning mode and a plurality of metal sections located on the drift region between the grid structure and the drain region.
In one embodiment, the coverage area of the metal field plate is smaller than or equal to the coverage area of the metal silicide barrier layer.
In one embodiment, the metal silicide blocking layer and the metal field plate are located on a surface of a drift region and extend from the surface of the drift region to the gate structure.
In one embodiment, the length of the metal segment spanning the gate structure and the drift region is greater than the length of the metal segment on the drift region between the gate structure and the drain region.
In one embodiment, a first conductive type body region is further formed in the semiconductor substrate, and the source region is formed in the second conductive type body region.
In one embodiment, a surface layer of the source region, a surface layer of the gate structure, and a surface layer of the drain region are all formed with metal silicide.
In one embodiment, a contact hole is led out from the upper part of the metal section spanning the gate structure and the drift region, and the contact hole is filled with a field plate material.
In one embodiment, the lengths of the metal segments arranged at intervals are gradually increased from the drain region to the gate structure, and the pitches of the metal segments arranged at intervals are gradually increased from the drain region to the gate structure.
A method for preparing a lateral double-diffused metal oxide semiconductor field effect transistor comprises the following steps:
providing a semiconductor substrate, wherein a drift region, a source region and a drain region are formed in the semiconductor substrate, a gate structure is formed on the semiconductor substrate, the semiconductor substrate has a first conductivity type, the drift region, the source region and the drain region have a second conductivity type, the gate structure covers part of the surface of the drift region, the source region and the drain region are respectively located on two sides of the gate structure, the drain region is formed in the drift region and far away from the gate structure, and the source region is formed in the substrate and connected with the gate structure;
forming a metal silicide blocking layer on the drift region between the grid structure and the drain region;
forming an oxide layer on the metal silicide barrier layer and forming a metal field plate on the oxide layer;
and etching the metal field plate, and forming a plurality of metal sections arranged at intervals in the direction from the grid structure to the drain region.
According to the preparation method of the transverse double-diffusion metal oxide semiconductor field effect tube, the metal silicide barrier layer, the oxidation layer and the metal field plate are respectively formed on the surface of the drift region, wherein the metal silicide barrier layer and the oxidation layer are dielectric layers, and the surface electric field of the drift region can be integrally regulated and controlled by regulating the thicknesses of the metal silicide barrier layer and the oxidation layer. Meanwhile, the metal field plate is divided into a plurality of metal sections which are arranged at intervals, the metal sections are not connected with each other, different voltages can be applied to the metal sections according to the electric field distribution condition of the drift region, the electric field distribution on the surface of the drift region is more uniform, and the reverse breakdown voltage of the LDMOS is further improved. Meanwhile, the segmented metal segment is formed, the device preparation process can be completed only by one-time photoetching, and the process is simple and the cost is low.
In one embodiment, the metal silicide blocking layer formed on the drift region between the gate structure and the drain region further extends to the gate structure;
the plurality of metal sections arranged from the grid structure to the drain region at intervals comprise metal sections arranged on the grid structure and the drift region in a spanning mode and a plurality of metal sections located on the drift region between the grid structure and the drain region.
Drawings
FIG. 1 is a schematic diagram of an exemplary LDMOS structure;
FIG. 2 is a flow chart of steps of a method for manufacturing an LDMOS device in accordance with an embodiment;
fig. 3a to 3g are state diagrams corresponding to the relevant steps of the LDMOS manufacturing method in an embodiment.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
As shown in fig. 1, in an embodiment, the LDMOS includes a semiconductor substrate 100, a drift region 110 is formed in the semiconductor substrate 100, a drain region 111 is formed in the drift region 110, an active region 122 is formed outside the drift region 110, a gate structure 200 is formed between the source region 122 and the drain region 111, the gate structure 200 is disposed on a surface of the semiconductor substrate 100 and covers a portion of a surface of the drift region 110, that is, the drain region 111 is formed in the drift region 110 and away from the gate structure 200, the source region 122 is formed on another side of the gate structure 200 and connected to the gate structure 200, a metal silicide blocking layer 400 is formed on a surface of the drift region between the gate structure 200 and the drain region 111, an oxide layer 500 is formed on the metal silicide blocking layer 400, a metal field plate 600 is formed on the oxide layer 500, and the metal field plate 600 includes a plurality of metal segments spaced apart from the gate structure toward the drain region. Wherein the semiconductor substrate 100 has a first conductivity type and the drift region 110, the drain region 111 and the source region 122 have a second conductivity type, the first conductivity type and the second conductivity type having opposite conductivity properties.
The region of the LDMOS mainly bearing withstand voltage is the drift region 110, the concentration and the size in the drift region 110 are main factors determining the breakdown voltage of the device, and decreasing the concentration of the drift region 110 or increasing the length of the drift region can increase the withstand voltage of the device, but this also deteriorates other characteristics of the device, such as on-resistance, on-state characteristics (on-state characteristics), and the like. In order to further increase the withstand voltage when the device has a low on-resistance, the drift region 110 of the device needs to be fully depleted, i.e., the surface electric field of the device needs to be optimized. At present, a field plate is arranged above a drift region, and the electric field distribution on the surface of the drift region is regulated and controlled through the field plate. When the field plate is not arranged, the electric field distribution on the surface of the drift region is not uniform, and the drift region of the device cannot be fully depleted. However, for a high-voltage device, the size of the drift region is relatively large, and the whole field plate is covered on the drift region, so that the device is exhausted too fast, that is, the withstand voltage of the device is low, and thus the field plate structure needs to be re-optimized. Therefore, when the voltage endurance of the device needs to be further improved, a slant field plate or a step field plate is usually formed, the oxide layer below the field plate close to the main junction is thinner, the thickness of the oxide layer is gradually increased towards the direction of the drain region, the modulation effect of the field plate on the electric field is stronger when the oxide layer is thinner, the modulation effect of the field plate on the electric field is weaker when the oxide layer is thicker, the oxide layers with different thicknesses are simultaneously arranged, the electric fields of drift regions at different positions are modulated, the electric field distribution on the surface of the drift region is more uniform, the breakdown voltage of the LDMOS is further improved, and meanwhile, the difficulty and the cost of the LDMOS preparation process are correspondingly increased.
In the present embodiment, a metal silicide blocking layer 400, an oxide layer 500 and a metal field plate 600 are sequentially formed above the drift region 110, wherein the metal field plate 600 may be made of a metal or a metal-like material with a small conductivity coefficient and a good adhesion, such as titanium, titanium silicide or tungsten silicide. The metal silicide blocking layer 400 and the oxide layer 500 are dielectric layers, and the metal field plate 600 can regulate and control the electric field of the drift region 110 to different degrees by regulating the thickness of the dielectric layers. Meanwhile, the metal field plate 600 comprises a plurality of metal sections which are arranged at intervals, the metal sections are arranged above the drift region at intervals from the grid structure 200 to the drain region 111, different voltages are applied to the metal sections at different positions according to the electric field distribution condition of the surface of the drift region 110, different electric potentials are formed at different positions of the drift region 110, and therefore the electric field inside the drift region 110 is regulated and controlled, the electric field inside the drift region 110 is distributed more uniformly, the breakdown voltage of the LDMOS is greatly improved, the segmented metal sections only need to be formed at one step in the process, and the preparation is simple. Meanwhile, the segmented metal segments are arranged, and the distribution of the electric field on the surface of the drift region 110 can be further adjusted by adjusting the number and the spacing of the segmented metal segments.
In addition, in the embodiment, when the pitch (pitch) of the device is relatively small, the surface electric field of the device can be optimized, a buried layer is not required to be arranged, the junction depth is not limited, and the application voltage range of the device is wide. In other embodiments, the device surface electric field optimization effect of the device with the voltage of 50V to 100V is relatively good, and the junction depth and the pitch (pitch) of the device can be relatively reduced.
In one embodiment, the first conductivity type is P-type and the second conductivity type is N-type. In other embodiments, the first conductivity type may also be N-type and the second conductivity type may be P-type. In one embodiment, the gate structure includes a gate oxide layer 210 and a polysilicon layer 220, and the semiconductor substrate 100 under the gate oxide layer 210 forms a channel region. In an embodiment, a first conductive type body region 120 is further formed in the semiconductor substrate 100, the first conductive type body region 120 and the semiconductor substrate 100 together form a channel region, a source region 122 is formed in the first conductive type body region 120, and a doping concentration of the first conductive type body region 120 is higher than that of the semiconductor substrate.
In an embodiment, a sidewall 300 is formed on a sidewall of the gate structure 200, that is, the sidewall of the gate oxide layer 210 and the sidewall of the polysilicon layer 220 are both formed with the sidewall 300, and the sidewall 300 includes a dielectric material, which can further isolate the gate structure 200 from the two side structures.
In an embodiment, the oxide layer 500 may be only located on the surface of the metal silicide 400, or may be integrally formed on the surface of the metal silicide 400, the surface of the gate structure 200, the surface of the source region 122, the surface of the drift region 110, and the surface of the drain region 111. In one embodiment, the LDMOS further includes a top dielectric layer 700, and the top dielectric layer 700 covers the source region 122, the gate structure 200, the drift region 110 and the drain region 111.
In an embodiment, a first metal silicide 123 is formed on a surface layer of the source region 122, a second metal silicide 112 is formed on a surface layer of the drain region 111, and a third metal silicide 221 is formed on a surface layer of the gate structure 200, wherein the third metal silicide 221 is specifically formed on a surface layer of the polysilicon 220, and at the same time, the source electrode 810 is led out from the first metal silicide 123, the gate electrode (not shown in fig. 1) is led out from the second metal silicide 221, the drain electrode 830 is led out from the third metal silicide 112, and a contact hole is led out on the metal field plate 600, and the contact hole is filled with a conductive material. The source 810, the drain 830 and the gate are connected to the metal silicide through the top dielectric layer 700, and the contact resistance of each conductive electrode in contact with each active region can be reduced by arranging the metal silicide. Because the metal silicide barrier layer 400 is arranged on the surface layer of the drift region 110, the modulation region on the surface of the drift region can be defined through the metal silicide barrier layer 400, and when metal silicide is formed on the source region, the drain region and the gate structure in the process, the metal silicide barrier layer is formed on the surface of the drift region, so that metal silicide cannot be formed on the top layer of the metal silicide group, the metal silicide barrier layer not only has the electric field modulation effect of the drift region, but also has the effect of defining the modulation region of the drift region, and metal silicide is prevented from being formed in the modulation region of the drift region.
In one embodiment, as shown in fig. 1, the metal field plate 600 is located directly above the metal silicide blocking layer 400, and the coverage area of the metal field plate 600 is smaller than or equal to the coverage area of the metal silicide blocking layer 400. In an embodiment, the metal silicide blocking layer 400 may be only located on the surface of the drift region 110, or may be located on the surface of the drift region 110 and extend to the gate structure 200, and specifically extend to the surface of the polysilicon 220, where the plurality of metal segments spaced from the gate structure 200 toward the drain region 111 include metal segments straddling over the gate structure 200 and the drift region 110 and a plurality of metal segments located on the gate structure and the drift region 110 of the drain region, that is, the metal silicide blocking layer 400, the metal field plate 600 and the oxide layer 500 sandwiched therebetween form a drift region electric field modulation structure, and the electric field modulation structure may be located only on the surface of the drift region, or may be located on the surface of the drift region and extend to a part of the top surface of the gate structure from the surface of the drift region to the surface of the drift region. In an embodiment, the length of the metal segment spanning the gate structure 200 and the drift region 110 is greater than the length of the metal segment located only above the drift region 110 between the gate structure and the drain region. When the sidewall 300 is formed on the sidewall of the gate structure 200, the metal silicide blocking layer 400 and the metal field plate 600 also cover the surface of the sidewall 300. In one embodiment, the length of the metal segment near the gate structure is longer, and the metal segment near the gate structure extends from the drift region to the gate structure.
A contact hole is led out from the metal field plate 600, the contact hole is specifically connected with the metal field plate 600 covering the drift region 110, the contact holes in different metal sections are connected with different voltages to change the potential of the metal section, and the potential of each metal section can be adjusted according to specific conditions. The material filled in the contact hole is selected from a material suitable for being used as a metal field plate, for example, a metal or metalloid material with small conductivity coefficient and good adhesion, such as titanium, titanium silicide or tungsten silicide. The metal segment near the gate structure 200 may have the same or different potential as the rest of the metal segments. Specifically, in an embodiment, the metal segment near the gate structure is grounded, the metal segment near the gate structure may also have the same potential as the gate or the source, and the potentials of the other metal segments are floating. As shown in fig. 1, a contact hole 820 is led out to cross over the metal segments on the gate structure 200 and the drift region 110, and the contact hole 820 is filled with a field plate material, for example, a metal or metalloid material with a small conductivity coefficient and a good adhesion, such as titanium, titanium silicide, or tungsten silicide. The contact hole 820 can be grounded, or connected with the source 810, or connected with the gate, and other metal segments are suspended, so that the potential distribution on the surface of the drift region can be changed, a high electric field peak value at the main junction is decomposed into a plurality of lower electric field peak values, the electric field distribution on the surface of the drift region is more uniform, and the breakdown voltage is improved. In an embodiment, different voltages can be applied to the metal segments to increase the surface potential of the drift region in a step manner. Similarly, a high electric field peak at the main junction can be decomposed into a plurality of lower electric field peaks, so that the electric field distribution on the surface of the drift region is more uniform, and the breakdown voltage is improved. In an embodiment, the lengths of the metal segments arranged at intervals are gradually increased from the drain region 111 to the gate structure 200, and the pitches of the metal segments arranged at intervals are gradually increased from the drain region 222 to the gate structure 200, so that the surface potential of the drift region 110 can be segmented uniformly, even if the electric field distribution on the surface of the drift region is uniform, and the withstand voltage of the device is improved. In one embodiment, for a 60V device, the device pitch (pitch) of the drift region is approximately 3 μm to 4 μm, and the spacing between the metal segment close to the gate structure 200 and the adjacent metal segment is in a range of 0.15 μm to 0.3 μm, i.e., the spacing between the first adjacent metal segments in the direction from the gate structure to the drain region is in a range of 0.15 μm to 0.3 μm. In one embodiment, when the metal field plate 600 further includes metal segments spanning the gate structure 200 and the drift region 110, the spacing between the metal segments spanning the gate structure 200 and the drift region 110 and the adjacent metal segments is in the range of 0.15 μm to 0.3 μm.
The application also relates to a method for preparing the lateral double-diffusion metal oxide semiconductor field effect transistor, and in one embodiment, as shown in figure 2, the method comprises the following steps.
Step S100: providing a semiconductor substrate, forming a drift region in the semiconductor substrate, forming a gate structure on the semiconductor substrate, wherein the semiconductor substrate has a first conductivity type, the drift region, a source region and a drain region have a second conductivity type, the gate structure covers part of the surface of the drift region, the source region and the drain region are respectively positioned at two sides of the gate structure, the drain region is formed in the drift region and is far away from the gate structure, and the source region is formed in the substrate and is connected with the gate structure.
In an embodiment, as shown in fig. 3a, the semiconductor substrate 100 is doped to form the drift region 110, the drift region 110 is doped to form the drain region 111, the source region 122 is formed outside the drift region, and the gate structure 200 is formed on a portion of the surface of the drift region 110 between the source region 122 and the drain region 111 and on the surface of the semiconductor substrate 100, that is, the source region 122 and the drain region 111 are respectively located on both sides of the gate structure 200, and the gate structure 200 further covers a portion of the surface of the drift region 110, the drain region 111 is spaced apart from the gate structure 200, and the source region 122 is connected to the gate structure 200.
In one embodiment, forming the gate structure specifically includes forming a gate oxide layer 210 and forming a polysilicon layer 220 on the gate oxide layer, and the semiconductor substrate 100 under the gate oxide layer 210 forms a channel region. In an embodiment, before forming the source region 122, doping the semiconductor substrate 100 to form the first conductive type body region 120, forming a channel region by the first conductive type body region 120 and the semiconductor substrate 100 together, doping the first conductive type body region 120 to form the source region 122, and reducing the on-resistance of the channel region by the doping concentration of the first conductive type body region 120 being higher than that of the semiconductor substrate.
In an embodiment, after the gate structure 200 is formed, a sidewall spacer 300 is formed on a sidewall of the gate structure 200, wherein the sidewall spacer 300 includes a dielectric material. In an embodiment, the forming of the sidewall spacer 300 specifically includes depositing a dielectric layer on the surface of the device after the gate structure 200 is formed, etching back the dielectric layer, and leaving the dielectric layer on the sidewall of the gate structure 200 to form the sidewall spacer 300.
Step S200: and forming a metal silicide barrier layer on the drift region between the gate structure and the drain region.
In one embodiment, as shown in FIG. 3b, a target area window is defined by photoresist and a metal silicide block layer 400 is deposited within the target area window. The metal silicide blocking layer 400 may be only on the surface of the drift region 110, or may be on the surface of the drift region 110 and extend to the gate structure 200, specifically to the surface of the polysilicon 220. When the sidewall 300 is formed on the sidewall of the gate structure 200, the metal silicide blocking layer 400 also covers the surface of the sidewall 300.
Step S300: an oxide layer is formed on the metal silicide barrier layer and a metal field plate is formed on the metal oxide layer.
In an embodiment, before forming the oxide layer, forming a metal silicide on a surface layer of the source region, a surface layer of the gate structure, and a surface layer of the drain region, that is, forming the oxide layer on the metal silicide blocking layer specifically includes:
step S310: a reactive metal layer is deposited on the side of the semiconductor structure having the active region formed in step S200.
In one embodiment, as shown in fig. 3c, a reactive metal layer 900, which may be cobalt metal, is deposited on the side of the semiconductor structure having the active region formed in step S200.
Step S320: and (4) performing heat treatment on the semiconductor structure formed in the step (S310) to enable the reaction metal layer to react with silicon to form metal silicide.
The metal in the reaction metal layer 900 only reacts with silicon, and since the sidewall 300 and the metal silicide blocking layer 400 are dielectric layers, the metal does not react with the metal. As shown in fig. 3d, the semiconductor structure is placed in a high temperature environment, the metal in the reaction metal layer 900 reacts with the silicon in the source region 122, the polysilicon 220 and the drain region 111 to form a metal silicide, and after the metal silicide is formed, the excess unreacted metal is removed, i.e., the metal at the sidewall 300 and the metal at the metal silicide barrier layer 400 are removed, the first metal silicide 123 is formed on the surface of the source region 122, the second metal silicide 221 is formed on the surface of the gate structure 200, and the third metal silicide 112 is formed at the drain region 111.
Step S330: an oxide layer is formed on the metal silicide barrier layer and a metal field plate is formed on the oxide layer.
The oxide layer can be only positioned on the surface of the metal silicide, or can be integrally formed on the surface of the metal silicide, the surface of the gate structure, the surface of the source region, the surface of the drift region and the surface of the drain region. In one embodiment, as shown in fig. 3e, an oxide layer 500 is deposited on the surface of the semiconductor device formed in step 320, i.e., the oxide layer 500 is formed on the upper surface of the semiconductor structure, and a metal field plate 600 is deposited on the oxide layer 500.
Step S400: and etching the metal field plate, and forming a plurality of metal sections which are arranged at intervals in the direction from the grid structure to the drain region.
As shown in fig. 3f, after defining an etching window by a photolithography process, the metal field plate 600 is etched, and segmented metal segments are formed above the metal silicide, and when the metal silicide 400 is located on the surface of the drift region and extends from the surface of the drift region to the top of the polysilicon portion, the metal segments spaced from the gate structure 200 toward the drain region 111 include metal segments straddling the gate structure 200 and the drift region 110 and metal segments on the drift region 110 between the gate structure 200 and the drain region 111. A metal segment close to the gate structure is partially located in the drift region and partially extends to a partial top surface of the gate structure, that is, the metal silicide blocking layer 400, the metal field plate 600 and the oxide layer 500 sandwiched therebetween form an electric field modulation structure of the drift region, and the electric field modulation structure may be located only on the surface of the drift region, or located on the surface of the drift region and extends to a partial top surface of the gate structure.
In an embodiment, the LDMOS manufacturing method further includes depositing a top dielectric layer 700 on the surface of the semiconductor formed in step S400, and etching the top dielectric layer to extract the source 810 from the source region 122, the gate from the gate structure, and the drain 830 from the drain region 111. In one embodiment, when the first metal silicide 123 is formed on the surface of the source region, the second metal silicide 221 is formed on the surface of the gate structure, and the third metal silicide 112 is formed on the surface of the drain region, each electrode is connected with the metal silicide in the corresponding source region, and by providing the metal silicide, the contact resistance between the conductive electrode and the active region can be reduced.
In the present embodiment, a metal silicide blocking layer 400, an oxide layer 500 and a metal field plate 600 are sequentially formed above the drift region 110, wherein the metal field plate 600 may be made of a metal or a metal-like material with a small conductivity coefficient and a good adhesion, such as titanium, titanium silicide or tungsten silicide. The metal silicide blocking layer 400 and the oxide layer 500 are dielectric layers, and the metal field plate can regulate and control the electric field of the drift region 110 to different degrees by regulating the thickness of the dielectric layers. Meanwhile, the metal field plate 600 comprises a plurality of metal sections which are arranged at intervals, the metal sections are arranged above the drift region at intervals from the grid structure 200 to the drain region 111, different voltages are applied to the metal sections at different positions according to the electric field distribution condition of the surface of the drift region 110, different electric potentials are formed at different positions of the drift region 110, and therefore the electric field inside the drift region 110 is regulated and controlled, the electric field inside the drift region 110 is distributed more uniformly, the breakdown voltage of the LDMOS is greatly improved, the segmented metal sections need to be formed at one step in the process, and the preparation is simple. Meanwhile, the segmented metal segments are arranged, and the distribution of the electric field on the surface of the drift region 110 can be further adjusted by adjusting the number and the spacing of the segmented metal segments.
And a contact hole is led out from the metal field plate and is filled with a conductive material. The contact holes are connected with different voltages to change the electric potentials of different metal sections, and the electric potentials of the metal sections can be adjusted according to specific conditions. Specifically, in an embodiment, as shown in fig. 3g, a contact hole 820 is led out to cross over the metal segments on the gate structure 200 and the drift region 110, the contact hole 820 may be grounded, or connected to the source 810, or connected to the gate, and other metal segments are suspended, so that the potential distribution on the surface of the drift region can be changed, and a high electric field peak at the main junction is decomposed into several lower electric field peaks, so that the electric field distribution on the surface of the drift region is more uniform, and the breakdown voltage is increased. In an embodiment, different voltages can be applied to the metal segments to increase the surface potential of the drift region in a step manner. Similarly, a high electric field peak at the main junction can be decomposed into a plurality of lower electric field peaks, so that the electric field distribution on the surface of the drift region is more uniform, and the breakdown voltage is improved.
The above examples only show some embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (10)

1. A lateral double diffused metal oxide semiconductor field effect transistor, comprising:
a semiconductor substrate having a first conductivity type;
the drift region is of the second conduction type and is formed on the surface layer of the semiconductor substrate;
the gate structure is arranged on the semiconductor substrate and covers part of the surface of the drift region;
the source region and the drain region are of a second conductivity type and are respectively formed on two sides of the grid structure, the drain region is formed in the drift region and is far away from the grid structure, and the source region is formed in the substrate and is connected with the grid structure;
the metal silicide barrier layer is formed on the drift region between the grid structure and the drain region;
the oxide layer is formed on the metal silicide barrier layer;
the metal field plate is formed on the oxide layer and comprises a plurality of metal sections which are arranged from the grid structure to the drain region at intervals, and different voltages are applied to the metal sections at different positions according to the electric field distribution condition of the surface of the drift region, so that different potentials are formed at different positions of the drift region;
the metal field plate is positioned right above the metal silicide barrier layer, and the coverage area of the metal field plate is smaller than or equal to that of the metal silicide barrier layer; the metal silicide barrier layer, the metal field plate and the oxide layer clamped in the middle form an electric field modulation structure of the drift region.
2. The ldmos field effect transistor of claim 1 wherein the metal silicide blocking layer formed on the drift region between the gate structure and the drain region also extends onto the gate structure;
the plurality of metal sections arranged from the grid structure to the drain region at intervals comprise metal sections arranged on the grid structure and the drift region in a spanning mode and a plurality of metal sections located on the drift region between the grid structure and the drain region.
3. The LDMOS transistor of claim 1 or 2, wherein the metal segment adjacent to the gate structure is at the same potential as the gate or the source, and the remaining metal segments are floating.
4. The ldmosfet of claim 2 wherein the length of the metal segment spanning the gate structure and the drift region is greater than the length of the metal segment in the drift region between the gate structure and the drain region.
5. The ldmos field effect transistor of claim 1 wherein a first conductivity type body region is further formed in the semiconductor substrate, the source region being formed in the first conductivity type body region.
6. The ldmos field effect transistor of claim 1 wherein a surface layer of the source region, a surface layer of the gate structure and a surface layer of the drain region are all formed with a metal silicide.
7. The ldmosfet as set forth in claim 2, wherein said contact hole is led out over said metal segment straddling said gate structure and said drift region.
8. The ldmosfet of claim 1 wherein the length of said spaced apart metal segments increases from said drain region to said gate structure and the pitch of said spaced apart metal segments increases from said drain region to said gate structure.
9. A method for preparing a lateral double-diffused metal oxide semiconductor field effect transistor is characterized by comprising the following steps:
providing a semiconductor substrate, wherein a drift region, a source region and a drain region are formed in the semiconductor substrate, a gate structure is formed on the semiconductor substrate, the semiconductor substrate has a first conductivity type, the drift region, the source region and the drain region have a second conductivity type, the gate structure covers part of the surface of the drift region, the source region and the drain region are respectively located on two sides of the gate structure, the drain region is formed in the drift region and far away from the gate structure, and the source region is formed in the substrate and connected with the gate structure;
forming a metal silicide blocking layer on the drift region between the grid structure and the drain region;
forming an oxide layer on the metal silicide barrier layer and forming a metal field plate on the oxide layer;
etching the metal field plate, forming a plurality of metal sections arranged at intervals from the grid structure to the drain region direction, and applying different voltages to the metal sections at different positions according to the electric field distribution condition of the surface of the drift region so as to form different electric potentials at different positions of the drift region;
the metal field plate is positioned right above the metal silicide barrier layer, and the coverage area of the metal field plate is smaller than or equal to that of the metal silicide barrier layer; the metal silicide barrier layer, the metal field plate and the oxide layer clamped in the middle form an electric field modulation structure of the drift region.
10. The method of claim 9, wherein the metal silicide blocking layer formed on the drift region between the gate structure and the drain region further extends onto the gate structure;
the plurality of metal sections arranged from the grid structure to the drain region at intervals comprise metal sections arranged on the grid structure and the drift region in a spanning mode and a plurality of metal sections located on the drift region between the grid structure and the drain region.
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