CN113506743A - Method for improving breakdown voltage of double-diffusion-drain device - Google Patents
Method for improving breakdown voltage of double-diffusion-drain device Download PDFInfo
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- CN113506743A CN113506743A CN202110685154.9A CN202110685154A CN113506743A CN 113506743 A CN113506743 A CN 113506743A CN 202110685154 A CN202110685154 A CN 202110685154A CN 113506743 A CN113506743 A CN 113506743A
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- 238000000034 method Methods 0.000 title claims abstract description 30
- 230000015556 catabolic process Effects 0.000 title claims abstract description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 22
- 229920005591 polysilicon Polymers 0.000 claims abstract description 12
- 229910005883 NiSi Inorganic materials 0.000 claims abstract description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 230000008569 process Effects 0.000 claims abstract description 6
- 238000005468 ion implantation Methods 0.000 claims description 6
- 230000004888 barrier function Effects 0.000 claims description 2
- 238000001259 photo etching Methods 0.000 claims 1
- 238000009792 diffusion process Methods 0.000 abstract description 7
- 238000010586 diagram Methods 0.000 description 8
- 230000000903 blocking effect Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
- H01L29/66598—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET forming drain [D] and lightly doped drain [LDD] simultaneously, e.g. using implantation through the wings a T-shaped layer, or through a specially shaped layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a method for improving the breakdown voltage of a double-diffusion drain device.A wafer is provided with a P-type substrate, and an N well is formed on the P-type substrate; forming an IO well on the N well; forming a first LDD region and a second LDD region on two sides of the IO well respectively; forming a polysilicon structure on the upper surface of the IO well; a part of the first LDD region and a part of the second LDD region are positioned below two sides of the polysilicon structure; forming a side wall on the side wall of the polycrystalline silicon structure; forming a source drain region on the first LDD region and the second LDD region outside the side wall of the polysilicon structure respectively; the source region in the source and drain region has no interval between the lateral direction and the adjacent side wall; shielding regions are arranged between the drain regions in the source and drain regions and the side walls adjacent to the drain regions in the transverse direction at intervals; forming an SAB region on the upper surface of the shielding region of the LDD region; and forming a NiSi layer on the surface of the wafer outside the SAB area. The novel asymmetric DDDMOS structure provided by the invention can improve the transverse punch-through voltage of the DDDMOS under the condition of not increasing any process cost, thereby being more widely applied to high-voltage or high-power devices.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for improving breakdown voltage of a double-diffusion drain device.
Background
The high voltage double diffused Drain device dddmos (drift Drain mosfet) is widely used in power management, input/output interface, LCD driver, and other circuits with its excellent voltage withstanding performance. The DDDMOS device forms a deep diffusion junction with small concentration and large junction depth under a highly doped source drain region by using a double diffusion technology. The traditional layout design diagram and the structural schematic diagram are shown in fig. 1a and fig. 1b, and the main structure comprises: and the shallow trench isolation region, the metal gate, the gate oxide layer, the isolation side wall, the source drain and the source drain shallow doped region are formed in a manner of being compatible with the CMOS process. With the wide application of high-voltage devices and high-power devices, the requirement on the breakdown voltage of the DDDMOS is higher and higher, so how to effectively improve the breakdown voltage of the device is a problem to be solved by the invention.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention provides a method for increasing the breakdown voltage of a double diffused drain device, which is used to solve the problem of low breakdown voltage of a high voltage double diffused drain device in the prior art.
To achieve the above and other related objects, the present invention provides a method for increasing the breakdown voltage of a double diffused drain device, comprising: providing a wafer, wherein the wafer is provided with a P-type substrate, and an N well is formed on the P-type substrate;
forming an IO (input/output) well on the N well;
step three, forming a first LDD area and a second LDD area on two sides of the IO trap respectively;
fourthly, forming a polycrystalline silicon structure on the upper surface of the IO trap; a part of the first LDD region and a part of the second LDD region are positioned below two sides of the polysilicon structure;
fifthly, forming a side wall on the side wall of the polycrystalline silicon structure;
sixthly, forming source drain regions in the first LDD region and the second LDD region outside the side wall of the polycrystalline silicon structure respectively; the source region in the source and drain region has no interval between the lateral direction and the adjacent side wall; shielding regions are arranged between the drain regions in the source and drain regions and the side walls adjacent to the drain regions in the transverse direction at intervals;
step seven, forming an SAB region on the upper surface of the shielding region of the LDD region;
and step eight, forming a NiSi layer on the surface of the wafer outside the SAB area.
Preferably, the N-well in step one is a deep N-well or a high voltage N-well.
Preferably, in the forming of the blocking region in the sixth step, the shielding region is defined on a photomask in the forming process of the source/drain region, and then the photomask of the source/drain region is used for performing photolithography and ion implantation to form the source/drain region, wherein ion implantation is not performed in the shielding region between the formed drain region and the adjacent side wall.
Preferably, the SAB region formed in step seven is SiN.
Preferably, the SAB region in step seven is a high resistance region.
Preferably, the NiSi layer in step eight is a low resistance region.
Preferably, the NiSi layer is formed in step eight using self-alignment.
As described above, the method for improving the breakdown voltage of the double diffused drain device of the present invention has the following beneficial effects: the novel asymmetric DDDMOS structure provided by the invention can improve the transverse punch-through voltage of the DDDMOS under the condition of not increasing any process cost, thereby being more widely applied to high-voltage or high-power devices.
Drawings
FIG. 1a is a schematic diagram of a double diffused drain device structure in the prior art;
FIG. 1b is a schematic diagram of a prior art double diffused drain device;
FIG. 2 is a schematic diagram of the structure layout of the double-diffused drain device in the present invention;
FIG. 3 is a schematic diagram of a double diffused drain device according to the present invention;
fig. 4 is a flow chart of a method for increasing the breakdown voltage of a double diffused drain device according to the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 2 to 4. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
The invention provides a method for improving the breakdown voltage of a double-diffusion leakage device, as shown in fig. 4, fig. 4 is a flow chart of the method for improving the breakdown voltage of the double-diffusion leakage device, and the method at least comprises the following steps:
providing a wafer, wherein the wafer is provided with a P-type substrate, and an N well is formed on the P-type substrate; as shown in fig. 3, fig. 3 is a schematic diagram of a double diffused drain device structure according to the present invention. In the first step, the P-type substrate (Psub) is disposed on the wafer, and then the N-well (DNW/HVNW) is formed on the upper surface of the P-type substrate (Psub).
Forming an IO (input/output) well on the N well; as shown in fig. 3, in the second step, the IO well (IOWell) is formed on the N well (DNW/HVNW);
step three, forming a first LDD area and a second LDD area on two sides of the IO trap respectively; as shown in fig. 3, in the third step, a first LDD region (IOLDD) and a second LDD region (IOLDD) are respectively formed on two sides of the IO well (IOWell), and the first LDD region in this embodiment is located on the left side of fig. 3; the second LDD region is located on the right side of fig. 3. The first and second LDD regions are diffusion regions.
Fourthly, forming a polycrystalline silicon structure on the upper surface of the IO trap; a part of the first LDD region and a part of the second LDD region are positioned below two sides of the polysilicon structure; as shown in fig. 3, in the fourth step, a polysilicon structure 02 is formed on the upper surface of the IO well (IOWell); a part of the first and second LDD regions is located below two sides of the polysilicon structure 02. That is, the first and second LDD regions are formed to partially overlap the polysilicon structure in the longitudinal direction, i.e., a portion of each of the first and second LDD regions is located below the polysilicon structure.
Fifthly, forming a side wall on the side wall of the polycrystalline silicon structure; as shown in fig. 3, in this step five, a sidewall 03 is formed on the sidewall of the polysilicon structure 02.
Sixthly, forming source drain regions in the first LDD region and the second LDD region outside the side wall of the polycrystalline silicon structure respectively; the source region in the source and drain region has no interval between the lateral direction and the adjacent side wall; shielding regions are arranged between the drain regions in the source and drain regions and the side walls adjacent to the drain regions in the transverse direction at intervals; as shown in fig. 3, in the sixth step, source drain regions (SD) are respectively formed in the first and second LDD regions (IOLDD) except the sidewall 03 on the sidewall of the polysilicon structure 02; wherein, the source region (S) in the source and drain regions has no space between the side walls adjacent to the source region in the transverse direction (as shown in fig. 3, there is no gap between the SD source region on the right side and the side walls on the right side in the transverse direction); shielding regions are arranged between the drain regions in the source and drain regions and the side walls adjacent to the drain regions in the transverse direction at intervals (for example, the shielding regions (SD blocks) are arranged between the SD drain regions on the right side in fig. 3 and the side walls adjacent to the SD drain regions in the transverse direction at intervals). Further, in the sixth step of this embodiment, the barrier region is formed by defining the shielding region on a mask (mask) during the formation of the source/drain region, and then performing photolithography and ion implantation using the mask of the source/drain region to form the source/drain region, wherein ion implantation is not performed in the shielding region between the formed drain region and the adjacent sidewall.
Step seven, forming an SAB region on the upper surface of the shielding region of the LDD region; as shown in fig. 3, in this step seven, an SAB region 01 is formed on the upper surface of the shield region (SD Block) of the LDD region. Further, the SAB region formed in step seven of this embodiment is SiN. In this embodiment, the SAB region is a metal silicide blocking region. Further, the SAB region in step seven of this embodiment is a high resistance region. As shown in fig. 2, fig. 2 is a layout diagram of the double diffused drain device structure in the present invention. The SAB area 01 is located between the drain area and the side wall.
And step eight, forming a NiSi layer on the surface of the wafer outside the SAB area. Further, the NiSi layer in step eight of this embodiment is a low resistance region. Further, the NiSi layer is formed by self-alignment in step eight of this embodiment.
In conclusion, the novel asymmetric DDDMOS structure provided by the invention can improve the lateral punch-through voltage of the DDDMOS without increasing any process cost, thereby being more widely applied to high-voltage or high-power devices. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (7)
1. A method for improving the breakdown voltage of a double diffused drain device is characterized by at least comprising the following steps:
providing a wafer, wherein the wafer is provided with a P-type substrate, and an N well is formed on the P-type substrate;
forming an IO (input/output) well on the N well;
step three, forming a first LDD area and a second LDD area on two sides of the IO trap respectively;
fourthly, forming a polycrystalline silicon structure on the upper surface of the IO trap; a part of the first LDD region and a part of the second LDD region are positioned below two sides of the polysilicon structure;
fifthly, forming a side wall on the side wall of the polycrystalline silicon structure;
sixthly, forming source drain regions in the first LDD region and the second LDD region outside the side wall of the polycrystalline silicon structure respectively; the source region in the source and drain region has no interval between the lateral direction and the adjacent side wall; shielding regions are arranged between the drain regions in the source and drain regions and the side walls adjacent to the drain regions in the transverse direction at intervals;
step seven, forming an SAB region on the upper surface of the shielding region of the LDD region;
and step eight, forming a NiSi layer on the surface of the wafer outside the SAB area.
2. The method of claim 1, wherein the method further comprises: the N trap in the first step is a deep N trap or a high-voltage N trap.
3. The method of claim 1, wherein the method further comprises: and step six, the barrier region is formed by defining the shielding region on a photomask in the process of forming the source and drain regions, and then photoetching and ion implantation are carried out by utilizing the photomask of the source and drain regions to form the source and drain regions, wherein ion implantation is not carried out in the shielding region between the formed drain region and the adjacent side wall.
4. The method of claim 1, wherein the method further comprises: and the SAB region formed in the seventh step is SiN.
5. The method of claim 1, wherein the method further comprises: and the SAB area in the step seven is a high-resistance area.
6. The method of claim 1, wherein the method further comprises: and the NiSi layer in the step eight is a low-resistance region.
7. The method of claim 1, wherein the method further comprises: and forming the NiSi layer by utilizing self-alignment in the step eight.
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| CN110634954A (en) * | 2018-06-22 | 2019-12-31 | 三星电子株式会社 | Semiconductor device, method of manufacturing the same, and layout design method |
| WO2020103672A1 (en) * | 2018-11-19 | 2020-05-28 | 无锡华润上华科技有限公司 | Transverse double diffusion metal-oxide semiconductor field-effect transistor and preparation method therefor |
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2021
- 2021-06-21 CN CN202110685154.9A patent/CN113506743A/en active Pending
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| US20030141559A1 (en) * | 2001-12-20 | 2003-07-31 | Stmicroelectronics S.R.I. | Metal oxide semiconductor field-effect transistor and associated methods |
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