CN111192922A - 一种具有p型漂移区和n型沟道的槽栅双极型晶体管 - Google Patents
一种具有p型漂移区和n型沟道的槽栅双极型晶体管 Download PDFInfo
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Abstract
本发明属于半导体器件技术领域,具体的说涉及一种槽栅双极型晶体管。本发明的主要方案:将常规N型漂移区N型沟道的载流子储存槽栅双极型晶体管(ND‑IGBT)的制造工艺用于P型硅片上,即将传统的N型漂移区变为P型漂移区,且放置于N型缓冲层3和N型CS层10之间。因此,本发明的PD‑IGBT具有与商业化ND‑IGBT兼容的工艺流程。在器件关断过程中,PD‑IGBT通过内部寄生晶闸管的电流正反馈作用,加速了器件对过剩载流子的抽取。同时,由于PD‑IGBT的耗尽层可以扩展进N型缓冲层内部,抽取了绝大多数存储在N型缓冲层内部的过剩少子,仅留下少数过剩少子来通过复合消除。因此,加快了PD‑IGBT的关断速度,同时降低了PD‑IGBT的关断功耗。
Description
技术领域
本发明属于半导体技术领域,具体的说涉及一种槽栅双极型晶体管(TrenchInsulated Gate Bipolar Transisitor,简称:TIGBT)。
背景技术
高压功率半导体器件是功率电子的重要组成部分,在诸如动力***中的电机驱动,消费电子中变频等领域具有广泛的应用。传统绝缘栅双极型晶体管(Insulated GateBipolar Transistor,简称:IGBT)由于其在中高压电力电子领域中展现出优越的性能而得到广泛的应用。但是,IGBT存在能耗参数(诸如开启能耗、导通能耗和关断能耗)间的折中优化。H.Takahashi等人在ISPSD`96proceedings上首次提出了一种新的槽栅型IGBT结构—CSTBT(ND-IGBT)结构。该结构通过在槽栅型IGBT的P型基区与N-漂移区之间添加一层浓度较高的N+载流子储存(CS)层,提升了器件的电导调制效应,进而优化了导通功耗与关断功耗的折中关系。此种产品已由日本三菱公司商业化生产,并成为第五代IGBT器件的典型代表。而在动态特性上,相比于比传统IGBT,CSTBT的关断时间和关断功耗并没有优化,甚至还有略微得增大。
发明内容
本发明所要解决的,就是针对上述问题,提出一种具有P型漂移区和N型沟道的新型IGBT(可称为PD-IGBT),实现在不影响器件其他特性的条件下加快IGBT的关断速度,同时降低IGBT的关断功耗。
为实现上述目的,本发明采用如下技术方案:
一种具有P型漂移区和N型沟道的槽栅双极型晶体管,其结构如图1所示;包括集电极结构、漂移区结构、发射极结构和槽栅结构;所述的集电极结构包括金属化集电极1和位于金属化集电极1上表面的P型集电极区2;所述漂移区结构包括N型缓存层3、位于N型缓存层3上表面的P型漂移区4和位于P型漂移区4上表面的N型载流子存储(CS)层10;所述N型缓存层3位于型P集电极区2的上表面;所述发射极结构包括金属化发射极5、N+发射区6、P+接触区7和P基区8,所述发射极结构位于漂移区结构的上层,P型基区8位于N型CS层10的上表面;所述N+发射区6位于P型基区8上表面的两端,且P+接触区7位于两端的N+发射区6之间,所述金属化发射极5位于P+接触区7和N+发射区6的上表面;所述槽栅结构由栅氧化层11和多晶硅栅级10组成,所述栅氧化层11位于发射极结构的两侧,并沿器件垂直方向延伸入器件中形成沟槽,所述栅氧化层11的侧面与P型基区8、N+发射区6、N型CS层10和P型漂移区4接触,所述多晶硅栅9位于沟槽中;其特征在于所述的漂移区结构由N型缓冲层3、P型漂移区4和N型CS层10组成,且位于P型集电极区2与P型基区8之间;
本发明总的技术方案,主要是将如图2所示的常规N型漂移区N型沟道的载流子储存槽栅双极型晶体管(ND-IGBT)的制造工艺用于P型硅片上,即将传统的N型漂移区变为P型漂移区,且放置于N型缓冲层3和N型CS层10之间。因此,本发明的PD-IGBT具有与商业化ND-IGBT兼容的工艺流程。
本发明的有益效果为,通过提出新结构槽栅双极型晶体管(PD-IGBT),在不改变器件其他参数的前提下,极大得降低了器件的关断时间和关断功耗,同时几乎不影响器件其他方面的特性。
附图说明
图1是本发明的PD-IGBT结构示意图;
图2是常规的ND-IGBT结构示意图;
图3是ND-IGBT与本发明提供的PD-IGBT的关断电场分布图;
图4是ND-IGBT与本发明提供的PD-IGBT的关断载流子浓度分布图;
图5是ND-IGBT与本发明提供的PD-IGBT的关断特性比较图;
图6是ND-IGBT与本发明提供的PD-IGBT的导通特性比较图;
图7是ND-IGBT与本发明提供的PD-IGBT的导通压降与关断功耗的折中关系比较图;
图8是本发明的PD-IGBT在不同温度下的开关特性图。
具体实施方式
下面结合附图,详细描述本发明的技术方案:
一种具有P型漂移区和N型沟道的槽栅双极型晶体管,其结构如图1所示;包括集电极结构、漂移区结构、发射极结构和槽栅结构;所述的集电极结构包括金属化集电极1和位于金属化集电极1上表面的P型集电极区2;所述漂移区结构包括N型缓存层3、位于N型缓存层3上表面的P型漂移区4和位于P型漂移区4上表面的N型载流子存储(CS)层10;所述N型缓存层3位于型P集电极区2的上表面;所述发射极结构包括金属化发射极5、N+发射区6、P+接触区7和P基区8,所述发射极结构位于漂移区结构的上层,P型基区8位于N型CS层10的上表面;所述N+发射区6位于P型基区8上表面的两端,且P+接触区7位于两端的N+发射区6之间,所述金属化发射极5位于P+接触区7和N+发射区6的上表面;所述槽栅结构由栅氧化层11和多晶硅栅级10组成,所述栅氧化层11位于发射极结构的两侧,并沿器件垂直方向延伸入器件中形成沟槽,所述栅氧化层11的侧面与P型基区8、N+发射区6、N型CS层10和P型漂移区4接触,所述多晶硅栅9位于沟槽中;其特征在于所述的漂移区结构由N型缓冲层3、P型漂移区4和N型CS层10组成,且位于P型集电极区2与P型基区8之间;
本发明总的技术方案,主要是将如图2所示的常规N型漂移区N型沟道的载流子储存槽栅双极型晶体管(ND-IGBT)的制造工艺用于P型硅片上,即将传统的N型漂移区变为P型漂移区,且放置于N型缓冲层3和N型CS层10之间。因此,本发明的PD-IGBT具有与商业化ND-IGBT兼容的工艺流程。
本发明工作原理:在所述IGBT的金属化集电极1上加正电压,在多晶硅栅极9上加正压,在金属化发射极5上加零电压,IGBT工作在导通状态。此时,撤去多晶硅栅极9上的正压,IGBT从导通状态逐渐转为关断状态。当IGBT在最常见的感性负载下关断时,其关断过程可分为两个阶段:电压上升期和电流下降期。在电压上升期,IGBT的集电极电流密度保持不变,集电极电压随时间上升。IGBT通过抽取器件内部的过剩载流子形成耗尽区,进而利用耗尽区内产生的电场来支撑上升的电压,如图3所示。而对于传统的ND-IGBT来说,器件内部过剩载流子的抽取只能依靠器件自身寄生的PNP晶体管(P型集电极区/N型漂移区/P型基区晶体管)的作用来完成,限制了载流子的抽取速度,从而增加的电压上升的时间。而对于本发明的PD-IGBT来说,其内部寄生了PNPN晶闸管结构(P型集电极区/N型缓冲区/P型漂移区/N型CS层区)。因此,在电压上升期,该寄生晶闸管产生电流正反馈作用,加速了器件对过剩载流子的抽取作用,进而缩短了电压上升的时间。另一方面,在电流下降期,对于ND-IGBT来说,由于电场无法穿透到N型缓冲区内,所以N型缓冲区内部的过剩少子(△P)无法通过电场快速扫除,只能通过复合作用缓慢消除。这会导致ND-IGBT关断时产生明显的电流拖尾,增大电流下降期的时间。而对于本发明的PD-IGBT来说,其电场的扩展几乎能延伸到整个N型缓冲区,如图3所示。因此,存储在PD-IGBT的N型缓冲层内部的绝大部分过剩少子(△P)可以被电场快速扫除,仅留下极少量的过剩载流子来通过复合消除,如图4所示。因此,PD-IGBT也可以缩短电流下降的时间。综上所述,相比于传统的ND-IGBT,PD-IGBT可以实现更快速的关断,实现更小的关断功耗。
对本发明提供的PD-IGBT和常规ND-IGBT结构进行仿真对比,进一步证实了本结构的优越性。图5给出了PD-IGBT和ND-IGBT的关断特性对比图。可以看出,PD-IGBT的关断只有90ns,比ND-IGBT降低了50%,证明了PD-IGBT的快速关断特性。图6给出了PD-IGBT和ND-IGBT的导通特性对比图。可以看出,PD-IGBT具有和ND-IGBT几乎一致的导通特性。同时,虽然PD-IGBT内部存在寄生晶闸管结构,但是期间依然具有饱和特性。这是由于PD-IGBT的电子注入是依靠MOS的N型沟道实现的,所以电子的注入效率仍然受到N型沟道的饱和特性限制,出现电流饱和现象。图7给出了PD-IGBT和ND-IGBT的导通压降和关断功耗的折中关系对比图。可以看出,在相同导通压降,PD-IGBT的关断功耗比传统ND-IGBT的要降低69%,证明了PD-IGBT的低功耗特性。图8给出了PD-IGBT在不同温度下的开关特性图。可以看出,PD-IGBT可以在-40℃和150℃的极端条件下正常工作,证明了器件的稳定性。
通过对IGBT关键参数:导通压降、饱和电流、关断时间和关断功耗的比较,直观地展示出了本发明结构相对与传统ND-IGBT结构在功率半导体器件应用上的性能优势。
Claims (1)
1.一种具有P型漂移区和N型沟道的槽栅双极型晶体管,包括集电极结构、漂移区结构、发射极结构和槽栅结构;
所述集电极结构包括金属化集电极(1)和位于金属化集电极(1)上表面的P型集电极区(2);
所述漂移区结构包括N型缓存层(3)、位于N型缓存层(3)上表面的P型漂移区(4)和位于P型漂移区(4)上表面的N型载流子存储层(10);所述N型缓存层(3)位于型P集电极区(2)的上表面;
所述发射极结构位于漂移区结构的上层,发射极结构包括金属化发射极(5)、N+发射区(6)、P+接触区(7)和P基区(8);P型基区(8)位于N型载流子存储层(10)的上表面;所述N+发射区(6)和P+接触区(7)位于P型基区(8)的上表面,且N+发射区(6)位于P+接触区(7)的两端,所述金属化发射极(5)位于P+接触区(7)和N+发射区(6)的上表面;
所述槽栅结构位于发射极结构的两侧,并沿器件垂直方向延伸入P型漂移区(4)中形成沟槽;槽栅结构由栅氧化层(11)和位于栅氧化层(11)中的多晶硅栅(9)组成,栅氧化层(11)的侧面与P型基区(8)、N+发射区(6)、N型载流子存储层(10)和P型漂移区(4)接触;所述金属化发射极(5)覆盖在槽栅结构上表面。
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JP2003017700A (ja) * | 2001-04-27 | 2003-01-17 | Toyota Central Res & Dev Lab Inc | バイポーラ型半導体装置 |
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CN107611176A (zh) * | 2016-07-12 | 2018-01-19 | 英飞凌科技股份有限公司 | 在漂移体积中具有p层的n沟道双极型功率半导体器件 |
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