CN111192855A - 一种阵列基板的制造方法、显示面板及显示装置 - Google Patents

一种阵列基板的制造方法、显示面板及显示装置 Download PDF

Info

Publication number
CN111192855A
CN111192855A CN201811352465.8A CN201811352465A CN111192855A CN 111192855 A CN111192855 A CN 111192855A CN 201811352465 A CN201811352465 A CN 201811352465A CN 111192855 A CN111192855 A CN 111192855A
Authority
CN
China
Prior art keywords
layer
metal layer
photoresist
etching
array substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201811352465.8A
Other languages
English (en)
Inventor
付婷婷
葛邦同
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HKC Co Ltd
Original Assignee
HKC Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by HKC Co Ltd filed Critical HKC Co Ltd
Priority to CN201811352465.8A priority Critical patent/CN111192855A/zh
Priority to PCT/CN2018/119706 priority patent/WO2020098024A1/zh
Priority to US16/315,599 priority patent/US10692900B1/en
Priority to US16/870,909 priority patent/US11139324B2/en
Publication of CN111192855A publication Critical patent/CN111192855A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41733—Source or drain electrodes for field effect devices for thin film transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/456—Ohmic electrodes on silicon
    • H01L29/458—Ohmic electrodes on silicon for thin film silicon, e.g. source or drain electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78663—Amorphous silicon transistors
    • H01L29/78669—Amorphous silicon transistors with inverted-type structure, e.g. with bottom gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78651—Silicon transistors
    • H01L29/7866—Non-monocrystalline silicon transistors
    • H01L29/78672—Polycrystalline or microcrystalline silicon transistor
    • H01L29/78678—Polycrystalline or microcrystalline silicon transistor with inverted-type structure, e.g. with bottom gate

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Inorganic Chemistry (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thin Film Transistor (AREA)
  • Liquid Crystal (AREA)

Abstract

本发明属于显示器技术领域，公开了一种阵列基板的制造方法、显示面板及显示装置。其中，该阵列基板的制造方法包括依次沉积于基板上的栅金属薄膜层、栅绝缘层、半导体层、以及金属层；在该金属层上涂覆一层光刻胶，通过曝光、显影形成未曝光区域、部分曝光区域以及完全曝光区域；通过第一次灰化处理去除部分曝光区域的光刻胶，暴露出对应所述部分曝光区域的金属层，通过湿蚀刻，形成金属层凹坑，通过第二次灰化处理将第一次灰化处理未刻蚀掉的残余的光刻胶刻蚀掉，进行干蚀刻，形成薄膜晶体管沟道区域图形。这样，通过采用第二次灰化处理，将残余的光刻胶刻蚀掉，保证光刻胶与金属层的边缘相齐平，降低了金属层与光刻胶之间的尺寸偏差。

Description

一种阵列基板的制造方法、显示面板及显示装置
技术领域
本发明属于显示器技术领域，尤其涉及一种阵列基板的制造方法、显示面板及显示装置。
背景技术
随着科学技术的发展，电子设备(例如智能手机、笔记本电脑、数码相机等)越来越普及，使得作为电子设备的重要部件的液晶显示器的需求量也大大提升，从而推动了液晶显示面板行业的快速发展。
现有的显示面板制造行业中，光刻掩膜版是在光刻工艺的关键部件，利用紫外光和光刻掩膜版对涂布有光刻胶上设计的图形进行曝光，可将光刻掩膜版上的电子器件图案转写到基板上，并经过显影、刻蚀、剥离等工艺形成电子器件。
然而，在光刻工艺过程中，由于光刻胶与沉积于基板上的金属层之间存在特征尺寸偏差(即设计值与实际值之间的偏差)，影响了后续的刻蚀工艺，进而影响了阵列面板的电性表现。
发明内容
本发明的目的在于提供一种阵列基板的制造方法，旨在解决现有光刻工艺中因光刻胶与金属层之间存在尺寸偏差而影响阵列面板电性的技术问题。
为了实现上述目的，本发明采用的技术方案是：一种阵列基板制造方法，包括：
在基板上依次形成栅电极、栅绝缘层、半导体层以及金属层；
在所述金属层上涂覆一层光刻胶；通过曝光、显影步骤形成未曝光区域、部分曝光区域以及完全曝光区域；
进行第一次灰化处理去除部分曝光区域的光刻胶，暴露出对应所述部分曝光区域的金属层；
进行湿蚀刻对部分曝光区域的所述金属层进行刻蚀，形成金属层凹坑，漏出半导体层；
进行第二次灰化处理，将所述金属层凹坑区域内经过第一次灰化处理未刻蚀掉的残余的所述光刻胶刻蚀掉；
进行干蚀刻，形成薄膜晶体管沟道区域图形。
在一个实施例中，所述第二次灰化处理采用氧气或六氟化硫气体刻蚀。
在一个实施例中，所述半导体层包括硅基薄膜层和沉积于所述硅基薄膜层上的欧姆接触层。
在一个实施例中，所述进行第二次灰化处理，将所述金属层凹坑区域对应的残余的所述光刻胶刻蚀掉的步骤之后还包括如下步骤：
进行干蚀刻，将暴露在所述金属层凹坑中的所述欧姆接触层刻蚀掉，漏出所述硅基薄膜层，以此形成薄膜晶体管沟道区域图形。
在一个实施例中，在所述金属层上设置光刻胶并形成未曝光区域、部分曝光区域以及完全曝光区域的步骤与所述进行第一次灰化处理去除部分曝光区域的光刻胶，暴露出对应所述部分曝光区域的金属层的步骤之间还包括如下步骤：
采用湿蚀刻工艺对所述完全曝光区域进行刻蚀，将所述完全曝光区域的金属层刻蚀掉；
对所述完全曝光区域的欧姆接触层采用干蚀刻工艺进行蚀刻以形成数据线、源电极及漏电极。
在一个实施例中，在进行第二次灰化处理，将所述金属层凹坑区域对应的残余的所述光刻胶刻蚀掉的步骤中还包括如下步骤：
在所述完全曝光区域内沉积一层钝化层，通过干蚀刻在所述钝化层上制作出过孔；
在所述钝化层上沉积一层导电薄膜，通过干蚀刻使所述导电薄膜形成像素电极，所述像素电极通过所述过孔与所述漏电极电性连接；
剥离剩余的光刻胶。
在一个实施例中，所述栅绝缘层及所述半导体层通过化学气相沉积法依次沉积于所述基板上，所述金属层通过物理气相沉积法沉积于所述半导体层上。
在一个实施例中，所述栅绝缘层的材料为氧化物、氮化物或者氧氮化物。
本发明的目的还在于提供一种显示面板，包括阵列基板和彩膜基板，所述阵列基板采用如上所述的阵列基板制造方法制备而成。
本发明的另一目的还在于提供一种显示装置，包括显示主机、以及用于支撑所述显示主机的底座，所述显示主机包括如上所述的显示面板。
本发明提供的阵列基板的制造方法的有益效果在于：本发明通过采用第一次灰化处理，可去除部分曝光区域的光刻胶，暴露出对应部分曝光区域的金属层；随后，通过进行湿蚀刻，从而可对部分曝光区域的金属层进行刻蚀，形成金属层凹坑，漏出半导体层；由于经过第一次灰化处理后，未能完全将金属层凹坑上方的光刻胶完全去除掉，故而需通过采用第二次灰化处理，将金属层凹坑区域内经过第一次灰化处理未刻蚀掉的的残余的光刻胶刻蚀掉，即通过在横向方向上减少第一次灰化处理未刻蚀掉光刻胶的覆盖量，保证光刻胶与金属层的边缘相齐平，降低了金属层与光刻胶之间的尺寸偏差，为后续的刻蚀工艺提供保证，以实现后续的半导体与金属层对齐。
附图说明
为了更清楚地说明本发明实施例中的技术方案，下面将对实施例或现有技术描述中所需要实用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本实施例的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本发明实施例提出的阵列基板制造方法的流程图；
图2为本发明实施例提出的在基板上沉积金属薄膜层的结构示意图；
图3为本发明实施例提出的在基板上沉积栅绝缘层、半导体层、以及金属层的结构示意图；
图4为本发明实施例提出的第一次灰化处理及湿蚀刻的结构示意图；
图5为本发明实施例提出的第二次灰化处理的结构示意图；
图6为本发明实施例提出的沉积钝化层与导电薄膜的结构示意图。
其中，图中各附图标记：
1-基板；
2-栅金属薄膜层；
3-栅绝缘层；
4-半导体层；41-硅基薄膜层；42-欧姆接触层；
5-金属层；50-金属层凹坑；
6-光刻胶；
7-钝化层；
8-导电薄膜。
具体实施方式
为了使本发明的目的、技术方案及优点更加清楚明白，以下结合附图及实施例，对本发明进行进一步详细说明。应当理解，此处所描述的具体实施例仅仅用以解释本发明，并不用于限定本发明。
需要说明的是，当元件被称为“固定于”或“设置于”另一个元件，它可以直接在另一个元件上或可能同时存在居中元件。当一个元件被称为是“连接于”另一个元件，它可以是直接连接到另一个元件或者可能同时存在居中元件。
另外，还需要说明的是，本发明实施例中的左、右、上、下等方位用语，仅是互为相对概念或是以产品的正常使用状态为参考的，而不应该认为是具有限制性的以下结合具体实施例对本发明的实现进行详细的描述。
如图1～6所示，本实施例提出了一种阵列基板的制造方法，包括如下步骤：
在基板1上依次形成栅电极、栅绝缘层3、半导体层4以及金属层5；对应图1中的步骤a与步骤b；
在所述金属层5上涂覆一层光刻胶6；通过曝光、显影步骤形成未曝光区域A、部分曝光区域B以及完全曝光区域C；对应图1中的步骤c；
进行第一次灰化处理去除部分曝光区域B的光刻胶6，暴露出对应所述部分曝光区域B的金属层5；对应图1中的步骤d；
进行湿蚀刻对部分曝光区域B的金属层6进行刻蚀，形成金属层凹坑50，漏出半导体层4；对应图1中的步骤e；
进行第二次灰化处理，将上述金属层凹坑50区域内经过第一次灰化处理未刻蚀掉的残余的光刻胶6刻蚀掉；对应图1中的步骤f；
进行干蚀刻，形成薄膜晶体管沟道区域图形；对应图1中的步骤g。
在本实施例中，请参阅图4与图5，采用半色调或灰色调掩膜版曝光，使光刻胶6形成完全曝光区域(光刻胶完全去除区域)C、部分曝光区域B(光刻胶部分去除区域)、以及未曝光区域A(光刻胶完全保留区域)，这样，通过采用第一次灰化处理，从而去除部分曝光区域B的光刻胶6，暴露出对应部分曝光区域B的金属层5；通过进行湿蚀刻，从而对部分曝光区域B的金属层5进行刻蚀，形成金属层凹坑50，漏出半导体层4；由于经过第一次灰化处理后，未能完全将金属层凹坑50上方的光刻胶6完全去除掉，故而需通过采用第二次灰化处理，将金属层凹坑50区域内经过第一次灰化处理未刻蚀掉的的残余的光刻胶6刻蚀掉，即通过在横向方向上减少第一次灰化处理未刻蚀掉光刻胶6的覆盖量，保证光刻胶6与金属层5的边缘相齐平，降低了金属层5与光刻胶6之间的尺寸偏差，为后续的刻蚀工艺提供保证。当然，在本实施例中，该制备方法不限于上述顺序，此处不作唯一限定。
在一个实施例中，如图5所示，图中的X代表的是上述所述的光刻胶6的横向方向。
在一个实施例中，上述第二次灰化处理可采用氧气或六氟化硫气体刻蚀，从而可较好的将上述光刻胶6刻蚀掉。
可选地，上述第一次灰化处理也可采用氧气或六氟化硫气体刻蚀，从而可较好的将上述光刻胶6刻蚀掉。
当然，在本实施例中，上述第一灰化处理或第二次灰化处理也可以通过其他气体来刻蚀，此处不作唯一限定。
在一个实施例中，上述半导体层4包括硅基薄膜层41和欧姆接触层42，该欧姆接触层42沉积于上述硅基薄膜41上。可选地，上述欧姆接触层42可通过化学气相沉积法沉积于硅基薄膜层41上，当然，在本实施例中，上述欧姆接触层42也可通过物理气相沉积法沉积于上述硅基薄膜层41上，此处不作唯一限定。
在一个实施例中，进行第二次灰化处理，将金属层凹坑区域对应的残余的光刻胶刻蚀掉的步骤之后还包括如下步骤：
进行干蚀刻，将暴露在所述金属层凹坑50中的所述欧姆接触层42刻蚀掉，使得部分曝光区域B漏出所述硅基薄膜层41，以此形成薄膜晶体管沟道区域图形。这样，通过在干蚀刻之前设置第二次灰化处理，从而将金属层凹坑50中的多余的光刻胶6刻蚀掉，当进行干蚀刻时，从而可将漏出的金属层凹坑50中的半导体层4完全刻蚀掉，使得半导体层4与金属层5的边缘相齐平，减少了因出现尺寸偏差而影响阵列基板的电性表现。
可选地，请参照表一，表一为灰化处理中不同气体对金属凹坑中的欧姆接触层刻蚀的影响。通过对比能够明显的看出，在同等条件下，通过灰化处理可使得金属层凹坑50中的残留量的欧姆接触层42较少；此外，在同等条件下，相对于氧气刻蚀来讲，六氟化硫气体刻蚀使得金属层凹坑50中的欧姆接触层42残留量较少，进而使得显示面板具有较好的显示特性。
可选地，请参照表二，表二为氧气刻蚀下不同时间对金属凹坑中的半导体刻蚀的影响。通过对比能够明显的看出，在同等条件下，当刻蚀的时间越长时，金属层凹坑50中的欧姆接触层42残留量逐渐减少，当通气时间达到60秒时，效果较佳，可使得欧姆接触层42残留量达到0.0769微米，几乎能够实现欧姆接触层42与金属层5的边缘相齐平，避免了因欧姆接触层42出现残留量而影响阵列基板的电学特性。
表一：灰化处理中不同气体对金属凹坑中的欧姆接触层刻蚀的影响
Figure BDA0001865214560000071
可选地，请参照表三，表三为六氟化硫气体刻蚀下不同时间对金属凹坑中的欧姆接触层刻蚀的影响。通过对比能够明显的看出，在同等条件下，当刻蚀的时间越长时，金属层凹坑50中的欧姆接触层42残留量逐渐减少，当通气时间达到20秒时，效果较佳，可使得欧姆接触层42残留量达到0.0992微米，为欧姆接触层42的边缘能够与金属层5的边缘相齐平提供了保证。
表二：氧气刻蚀下不同时间对金属凹坑中的欧姆接触层刻蚀的影响
Figure BDA0001865214560000072
表三：六氟化硫气体刻蚀下不同时间对金属凹坑中的欧姆接触层刻蚀的影响
Figure BDA0001865214560000073
可选地，通过表二与表三对比能够看出，当采用氧气刻蚀，通气时长为40秒时，此时欧姆接触层42的残留量达到0.09178微米，当采用六氟化硫气体刻蚀，通气时长为20秒时，此时欧姆接触层42的残留量达到0.0992微米，通过对比能够发现，采用六氟化硫气体刻蚀能够在较短的时间内，使得欧姆接触层42的残留量达到与氧气刻蚀在40秒的残留量，即通过采用六氟化硫气体刻蚀，可大大提高刻蚀的效率，进而节约了生产成本。
在一个实施例中，在进行第二次灰化处理，将所述金属层凹坑区域对应的残余的所述光刻胶刻蚀掉的步骤还包括如下步骤：
采用湿蚀刻工艺对完全曝光区域C进行刻蚀，将完全曝光区域C的金属层5刻蚀掉；
对完全曝光区域C的欧姆接触层42采用干蚀刻工艺进行蚀刻以形成数据线、源电极及漏电极。
这样，通过湿蚀刻及干蚀刻，从而可在基板1上形成数据线、源电极及漏电极。在本实施例中，上述源电极及漏电极材料可选用铬、铝或铜等金属中的任意一种或多种，此处不作唯一限定。
在一个实施例中，在进行第二次灰化处理，将金属层凹坑区域对应的残余的光刻胶刻蚀掉的步骤中还包括如下步骤：
在完全曝光区域C上沉积一层钝化层7，通过干蚀刻在所述钝化层7上制作出过孔；
在钝化层7上沉积一层导电薄膜8，通过干蚀刻形成像素电极，像素电极通过所述过孔与所述漏电极电性连接；
剥离剩余的光刻胶。
可选地，在本实施例中，采用等离子体增强化学气相沉积法沉积一层钝化层7，钝化层7采用氮化硅材料制备，这样，通过采用氮化硅材料制备钝化层，从而可起到防止水汽、钠离子和氧气杂质侵入到器件中，当然，在本实施例中，上述钝化层也可通过其他有机绝缘材料制备，此处不作唯一限定。
可选地，在本实施例中，通过在上述钝化层7上涂覆一层光刻胶6，采用普通掩膜版通过曝光和显影后，采用干法刻蚀工艺，在像素区域内形成钝化层凹坑(即过孔图形)，钝化层凹坑内的钝化层7被完全刻蚀掉，从而可暴露出部分漏电极。
可选地，在本实施例中，采用磁控溅射或热蒸发的方法沉积一层导电薄膜8，该导电薄膜8可采用氧化铟锡或氧化铟锌，这样，通过进行干蚀刻形成像素电极，且该像素电极可通过钝化层过孔与漏电极电性相连。最后，利用带膜剥离工艺去除剩余的光刻胶6和覆盖在剩余光刻胶6上的导电薄膜8，从而使得沉积在钝化层7过孔中的导电薄膜8保留下来。
可选地，上述栅绝缘层3与半导体层4均采用化学气相沉积沉积于上述基板1上，且上述金属层5通过气相沉积法沉积于上述半导体层4上。
可选地，在本实施例中，上述栅绝缘层3的材料可为氧化物、氮化物或者氧氮化物等材料，当然，在本实施例中，上述栅绝缘层3也可通过其他材料制备，此处不作唯一限定。
在本发明中，还提供了一种显示面板(附图未作出)，该显示面板包括阵列基板和彩膜基板，在该阵列基板采用如上所述的阵列基板制造方法制备而成，此处不作赘述。这样，通过采用上述方法制造的阵列基板，从而可保证金属层5与光刻胶层6的边缘相齐平，从而使得后续刻蚀的欧姆接触层42与金属层5的边缘相齐平，避免了因边缘不齐而引起尺寸偏差，从而影响了显示面板的电学特性。
在本发明中，还提供了一种显示装置，该显示装置包括显示主机(附图未作出)以及底座(附图未作出)，该底座可用于支撑上述显示主机，该显示主机包括如上所述的显示面板。
在本发明中，通过在采用干蚀刻之前，增加第二次灰化处理，从而可降低金属层5与光刻胶6之间的尺寸偏差，从而为后续刻蚀的欧姆接触层42与金属层5的边缘相齐平提供了保证，此外，通过使用六氟化硫气体来对光刻胶6蚀刻，可实现在较短的时间内对光刻胶6进行较好的蚀刻，提高了刻蚀的生产效率，降低了生产成本。
以上所述仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内所作的任何修改、等同替换和改进等，均应包含在本发明的保护范围之内。

Claims (10)

1.一种阵列基板的制造方法，其特征在于，包括如下步骤：
在基板上依次形成栅电极、栅绝缘层、半导体层以及金属层；
在所述金属层上涂覆一层光刻胶；通过曝光、显影步骤形成未曝光区域、部分曝光区域以及完全曝光区域；
进行第一次灰化处理去除部分曝光区域的光刻胶，暴露出对应所述部分曝光区域的金属层；
进行湿蚀刻对部分曝光区域的所述金属层进行刻蚀，形成金属层凹坑，漏出半导体层；
进行第二次灰化处理，将所述金属层凹坑区域内经过第一次灰化处理未刻蚀掉的残余的所述光刻胶刻蚀掉；
进行干蚀刻，形成薄膜晶体管沟道区域图形。
2.如权利要求1所述的一种阵列基板的制造方法，其特征在于，所述第二次灰化处理采用氧气或六氟化硫气体刻蚀。
3.如权利要求1所述的阵列基板的制造方法，其特征在于，所述半导体层包括硅基薄膜层和沉积于所述硅基薄膜层上的欧姆接触层。
4.如权利要求3所述的一种阵列基板的制造方法，其特征在于，所述进行第二次灰化处理，将所述金属层凹坑区域对应的残余的所述光刻胶刻蚀掉的步骤之后还包括如下步骤：
进行干蚀刻，将暴露在所述金属层凹坑中的所述欧姆接触层刻蚀掉，漏出所述硅基薄膜层，以此形成薄膜晶体管沟道区域图形。
5.如权利要求3所述的一种阵列基板的制造方法，其特征在于，在所述金属层上设置光刻胶并形成未曝光区域、部分曝光区域以及完全曝光区域的步骤与所述进行第一次灰化处理去除部分曝光区域的光刻胶，暴露出对应所述部分曝光区域的金属层的步骤之间还包括如下步骤：
采用湿蚀刻工艺对所述完全曝光区域进行刻蚀，将所述完全曝光区域的金属层刻蚀掉；
对所述完全曝光区域的欧姆接触层采用干蚀刻工艺进行蚀刻以形成数据线、源电极及漏电极。
6.如权利要求5所述的一种阵列基板的制造方法，其特征在于，在进行第二次灰化处理，将所述金属层凹坑区域对应的残余的所述光刻胶刻蚀掉的步骤中还包括如下步骤：
在所述完全曝光区域内沉积一层钝化层，通过干蚀刻在所述钝化层上制作出过孔；
在所述钝化层上沉积一层导电薄膜，通过干蚀刻使所述导电薄膜形成像素电极，所述像素电极通过所述过孔与所述漏电极电性连接；
剥离剩余的光刻胶。
7.如权利要求1所述的一种阵列基板的制造方法，其特征在于，所述栅绝缘层及所述半导体层通过化学气相沉积法依次沉积于所述基板上，所述金属层通过物理气相沉积法沉积于所述半导体层上。
8.如权利要求7所述的一种阵列基板的制造方法，其特征在于，所述栅绝缘层的材料为氧化物、氮化物或者氧氮化物。
9.显示面板，包括阵列基板和彩膜基板，其特征在于，所述阵列基板采用如权利要求1～8任一项所述的阵列基板制造方法制备而成。
10.显示装置，包括显示主机、以及用于支撑所述显示主机的底座，其特征在于，所述显示主机包括如权利要求9所述的显示面板。
CN201811352465.8A 2018-11-14 2018-11-14 一种阵列基板的制造方法、显示面板及显示装置 Pending CN111192855A (zh)

Priority Applications (4)

Application Number Priority Date Filing Date Title
CN201811352465.8A CN111192855A (zh) 2018-11-14 2018-11-14 一种阵列基板的制造方法、显示面板及显示装置
PCT/CN2018/119706 WO2020098024A1 (zh) 2018-11-14 2018-12-07 一种阵列基板的制造方法及显示面板
US16/315,599 US10692900B1 (en) 2018-11-14 2018-12-07 Method of manufacturing array substrate and display panel
US16/870,909 US11139324B2 (en) 2018-11-14 2020-05-09 Method of manufacturing array substrate and display panel

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201811352465.8A CN111192855A (zh) 2018-11-14 2018-11-14 一种阵列基板的制造方法、显示面板及显示装置

Publications (1)

Publication Number Publication Date
CN111192855A true CN111192855A (zh) 2020-05-22

Family

ID=70708945

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201811352465.8A Pending CN111192855A (zh) 2018-11-14 2018-11-14 一种阵列基板的制造方法、显示面板及显示装置

Country Status (3)

Country Link
US (2) US10692900B1 (zh)
CN (1) CN111192855A (zh)
WO (1) WO2020098024A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111192855A (zh) * 2018-11-14 2020-05-22 惠科股份有限公司 一种阵列基板的制造方法、显示面板及显示装置

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040126950A1 (en) * 2002-12-28 2004-07-01 Jeong-Rok Kim Transistor array substrate fabrication for an LCD
CN102629588A (zh) * 2011-12-13 2012-08-08 京东方科技集团股份有限公司 阵列基板的制造方法
CN103715267A (zh) * 2013-12-30 2014-04-09 京东方科技集团股份有限公司 薄膜晶体管、tft阵列基板及其制造方法和显示装置
CN106505033A (zh) * 2016-11-16 2017-03-15 深圳市华星光电技术有限公司 阵列基板及其制备方法、显示装置
CN106684037A (zh) * 2017-03-22 2017-05-17 深圳市华星光电技术有限公司 优化4m制程的tft阵列制备方法
CN108417583A (zh) * 2018-03-09 2018-08-17 惠科股份有限公司 一种阵列基板的制造方法和阵列基板

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100439844B1 (ko) * 2002-07-24 2004-07-12 삼성전자주식회사 반도체 소자의 금속배선 형성 후의 감광막 제거방법
CN102023433B (zh) * 2009-09-18 2012-02-29 北京京东方光电科技有限公司 Tft-lcd阵列基板及其制造方法
CN103163745B (zh) * 2011-12-15 2015-09-02 中芯国际集成电路制造(上海)有限公司 光刻胶层的去除方法、晶体管的形成方法
CN104425265B (zh) * 2013-08-20 2017-07-14 中芯国际集成电路制造(上海)有限公司 Pmos晶体管的形成方法及cmos晶体管的形成方法
CN105845624A (zh) * 2016-05-11 2016-08-10 上海华虹宏力半导体制造有限公司 通孔及导电插塞的制作方法
CN107068725B (zh) * 2017-04-26 2019-09-24 京东方科技集团股份有限公司 有源矩阵有机发光二极管背板及其制造方法
CN111192855A (zh) * 2018-11-14 2020-05-22 惠科股份有限公司 一种阵列基板的制造方法、显示面板及显示装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040126950A1 (en) * 2002-12-28 2004-07-01 Jeong-Rok Kim Transistor array substrate fabrication for an LCD
CN102629588A (zh) * 2011-12-13 2012-08-08 京东方科技集团股份有限公司 阵列基板的制造方法
CN103715267A (zh) * 2013-12-30 2014-04-09 京东方科技集团股份有限公司 薄膜晶体管、tft阵列基板及其制造方法和显示装置
CN106505033A (zh) * 2016-11-16 2017-03-15 深圳市华星光电技术有限公司 阵列基板及其制备方法、显示装置
CN106684037A (zh) * 2017-03-22 2017-05-17 深圳市华星光电技术有限公司 优化4m制程的tft阵列制备方法
CN108417583A (zh) * 2018-03-09 2018-08-17 惠科股份有限公司 一种阵列基板的制造方法和阵列基板

Also Published As

Publication number Publication date
WO2020098024A1 (zh) 2020-05-22
US20200185430A1 (en) 2020-06-11
US20200273891A1 (en) 2020-08-27
US11139324B2 (en) 2021-10-05
US10692900B1 (en) 2020-06-23

Similar Documents

Publication Publication Date Title
CN105161505B (zh) 一种阵列基板及其制作方法、显示面板
JP5512180B2 (ja) フォトレジストの縁部のバリの形成方法とアレイ基板の製造方法
US10916568B2 (en) Manufacturing method of display substrate, array substrate and display device
US8895334B2 (en) Thin film transistor array substrate and method for manufacturing the same and electronic device
CN106887379B (zh) 一种半透掩膜构图方法及阵列基板、显示装置
WO2019007228A1 (zh) 薄膜晶体管及其制备方法、阵列基板和显示装置
CN103137558B (zh) 一种tn型阵列基板及其制作方法、显示装置
US10128281B2 (en) Array substrate, fabrication method thereof and display device
CN106653774B (zh) 阵列基板及其制造方法、掩膜版、显示装置
US10663820B2 (en) Display substrate, its manufacturing method, and display device
CN109712930B (zh) 显示基板及其制作方法、显示装置
CN108538855B (zh) 一种阵列基板的制作方法
JP2011070194A (ja) Ｔｆｔ−ｌｃｄアレイ基板及びその製造方法
US9905592B2 (en) Method for manufacturing TFT, array substrate and display device
WO2019179128A1 (zh) 阵列基板的制造方法、阵列基板、显示面板和显示装置
US20160322404A1 (en) Methods for producing tft array substrate and display apparatus
CN102629588B (zh) 阵列基板的制造方法
US11569275B2 (en) Array substrate, method for preparing the same, and display device
CN104617049A (zh) 一种阵列基板及其制作方法、显示装置
CN102655116B (zh) 阵列基板的制造方法
CN111192855A (zh) 一种阵列基板的制造方法、显示面板及显示装置
CN109037151B (zh) 一种阵列基板的制备方法
CN107644880B (zh) 氧化物薄膜晶体管显示基板及其制作方法、显示装置
CN107425077B (zh) 薄膜晶体管及其制作方法、显示装置
US20230017854A1 (en) Display substrate and manufacturing method, and display device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication
RJ01 Rejection of invention patent application after publication

Application publication date: 20200522