CN111164751A - 微电子组件 - Google Patents
微电子组件 Download PDFInfo
- Publication number
- CN111164751A CN111164751A CN201780095322.0A CN201780095322A CN111164751A CN 111164751 A CN111164751 A CN 111164751A CN 201780095322 A CN201780095322 A CN 201780095322A CN 111164751 A CN111164751 A CN 111164751A
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- CN
- China
- Prior art keywords
- die
- package substrate
- interconnect
- conductive
- conductive contact
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
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Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
- H01L24/09—Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
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Abstract
本文公开了微电子组件以及相关的器件和方法。例如,在一些实施例中,微电子组件可以包括具有第一表面和相对的第二表面的封装衬底、以及固定到封装衬底的管芯,其中管芯具有第一表面和相对的第二表面,管芯在第一表面处具有第一导电触点,以及在第二表面处具有第二导电触点,并且第一导电触点是通过第一非焊料互连来耦合到在封装衬底中的导电通路。
Description
背景技术
集成电路管芯通常耦合到封装衬底,用于机械稳定性并促进与诸如电路板的其它组件的连接。除了别的之外,由传统衬底可实现的互连间距受到制造、材料和热条件约束。
附图说明
结合附图通过以下详细描述将容易理解实施例。为了促进该描述,相似的参考数字指定相似的结构元件。在附图的图中,以通过示例而非限制的方式示出实施例。
图1是根据各种实施例的示例性微电子组件的侧面剖视图。
图2是根据各种实施例被包括在图1的微电子组件中的管芯的底视图。
图3-图11是根据各种实施例的示例性微电子组件的侧面剖视图。
图12-图16是根据各种实施例在微电子组件中的多个管芯的示例性布置的顶视图。
图17A-图17F是根据各种实施例在用于制造图5的微电子组件的示例性工艺中的各个阶段的侧面剖视图。
图18A-图18B是根据各种实施例在用于制造图5的微电子组件的另一示例性工艺中的各个阶段的侧面剖视图。
图19A-图19H是根据各种实施例在用于制造图5的微电子组件的另一示例性工艺中的各个阶段的侧面剖视图。
图20-图22是根据各种实施例的示例性微电子组件的侧面剖视图。
图23A-图23B是根据各种实施例在用于制造图20的微电子组件的示例性工艺中的各个阶段的侧面剖视图。
图24A-图24E是根据各种实施例在用于制造图21的微电子组件的示例性工艺中的各个阶段的侧面剖视图。
图25A-图25F是根据各种实施例在用于制造图22的微电子组件的示例性工艺中的各个阶段的侧面剖视图。
图26A-26D是根据各种实施例在用于制造图21的微电子组件的另一示例工艺中的各个阶段的侧面剖视图。
图27是根据各种实施例的示例性微电子组件的侧面剖视图。
图28是根据本文公开的实施例中的任何实施例可以被包括在微电子组件中的晶圆和管芯的顶视图。
图29是根据本文公开的实施例中的任何实施例可以被包括在微电子组件中的集成电路(IC)器件的剖面侧视图。
图30是根据本文公开的实施例中的任何实施例可以包括微电子组件的IC器件组件的剖面侧视图。
图31是根据本文公开的实施例中的任何实施例可以包括微电子组件的示例性电子设备的方块图。
具体实施方式
本文公开了微电子组件以及相关的器件和方法。例如,在一些实施例中,微电子组件可以包括具有第一表面和相对的第二表面的封装衬底以及固定在封装衬底的管芯,其中管芯具有第一表面和相对的第二表面,管芯具有在第一表面处的第一导电触点以及在第二表面处的第二导电触点,并且第一导电触点通过第一非焊料互连来耦合到在封装衬底中的导电通路。
在多管芯集成电路(IC)封装中的两个或更多个管芯之间传送大量的信号是有挑战性的,这是由于这样的管芯的尺寸越来越小、热约束和功率输出约束,除了别的之外。相对于传统方法,本文公开的实施例中的各种实施例可以以较低的成本、利用提高的功率效率、利用更高的带宽和/或利用更大的设计灵活性,来帮助实现多个IC管芯的可靠附接。相对于传统方法,本文公开的微电子组件中的各种微电子组件可以表现出更好的功率输出和信号速度,同时减小封装的尺寸。本文所公开的微电子组件对于在计算机、平板设备、工业机器人和消费电子产品(例如,可穿戴设备)中的小型和低简档应用可能是特别有利的。
在下文的详细描述中,参考形成其一部分的附图,其中贯穿全文相似的数字指定相似的部分,并且在其中通过说明的方式示出可以实践的实施例。应当理解的是,在不背离本公开内容的保护范围的情况下,可以利用其它实施例,以及可以进行结构的或的逻辑上的改变。因此,下文的详细描述将不具有限制意义。
可以以最有助于理解所要求保护的主题的方式,将各种操作描述为多个离散动作或依次进行的操作。但是,描述的顺序不应被解释为暗示这些操作必然与顺序相关。特别是,可以不按呈现的顺序来执行这些操作。可以以与所描述的实施例不同的顺序来执行所描述的操作。在额外的实施例中,可以执行各种额外的操作,和/或可以省略所描述的操作。
为了本公开内容的目的,短语“A和/或B”意指(A)、(B)或(A和B)。为了本公开内容的目的,短语“A、B和/或C”意指(A)、(B)、(C)、(A和B)、(A和C)、(B和C)或(A、B和C)。附图不一定是按比例绘制的。虽然附图中的许多附图示出具有平壁和直角拐角的直线结构,但这仅是为了便于说明,以及使用这些技术制成的实际设备将显示圆角、表面粗糙度和其它特征。
描述使用短语“在一实施例中”或“在实施例中”,其均可以指的是相同实施例或不同实施例中的一者或多者。此外,关于本公开内容的实施例使用的术语“包括”、“包含”、“具有”等等是同义的。如本文所使用的,“封装”和“IC封装”是同义的,如“管芯”和“IC管芯”是同义的。本文中可以使用术语“顶部”和“底部”来解释附图的各种特征,但是这些术语仅仅是为了便于讨论,以及并不意味着期望的或要求的定向。如本文所使用的,除非另外说明,否则术语“绝缘”意指“电绝缘”。
当用于描述尺寸的范围时,短语“在X与Y之间”表示包括X与Y的范围。为了方便起见,短语“图17”可以用于指图17A至图17F的附图集合。短语“图18”可以用于指图18A-图18B的附图集合等等。虽然在本文中某些元件可以是以单数形式来指代的,但是这样的元件可以包括多个子元件。例如,“绝缘材料”可以包括一种或多种绝缘材料。如本文所使用的,“导电触点”可以指的是用作在不同组件之间的电界面的一部分导电材料(例如,金属);导电触点可以凹入组件的表面中、与组件的表面齐平、或者从组件的表面向外延伸,并且导电触点可以采取任何适当的形式(例如,导电焊盘或插座、或者导电线或通孔的一部分)。
图1是根据各种实施例的微电子组件100的侧面剖视图。在图1中许多元件示出为包括在微电子组件100中,但是这些元件中的一些元件可以不存在于微电子组件100中。例如,在各种实施例中,可以不包括散热器131、热界面材料129、模制材料127、管芯114-3、管芯114-4、第二级互连137和/或电路板133。进一步地,图1为了便于说明起见而示出从随后的附图中省略的一些元件,但是可以被包括在本文所公开的微电子组件100中的任何微电子组件。这样的元件的示例包括散热器131、热界面材料129、模制材料127、第二级互连137和/或电路板133。图1的微电子组件100的元件中的许多元件是包括在附图中的其它附图中的;当讨论这些附图时,将不重复对这些元件的讨论,并且这些元件中的任何元件可以采用本文公开的形式中的任何形式。在一些实施例中,本文所公开的微电子组件100中的单独的微电子组件可以用作在其中包括具有不同功能的多个管芯114的***级封装(SiP)。在这样的实施例中,微电子组件100可以称为SiP。
微电子组件100可以包括通过管芯到封装衬底(DTPS)互连150-1耦合到管芯114-1的封装衬底102。尤其,封装衬底102的顶表面可以包括一组导电触点146,并且管芯114-1的底表面可以包括一组导电触点122;在管芯114-1的底表面处的导电触点122可以通过DTPS互连150-1电力地以及机械地耦合到在封装衬底102的顶表面处的导电触点146。在图1的实施例中,封装衬底102的顶表面包括在其中至少部分地安置管芯114-1的凹槽108;管芯114-1所耦合到的导电触点146位于凹槽108的底部处。在其它实施例中,管芯114-1可以不安置在凹槽中(例如,如下文参考图9-图11所讨论的)。例如,本文所公开的导电触点中的任何导电触点(例如,导电触点122、124、146、140和/或135)可以包括键合焊盘、接线柱(post)或者任何其它适当的导电触点。
封装衬底102可以包括绝缘材料(例如,如在本领域中已知的在多层中形成的电介质材料)和穿过电介质材料的一个或多个导电通路(例如,包括导电迹线和/或导电通孔,如所示出的)。在一些实施例中,封装衬底102的绝缘材料可以是电介质材料,诸如有机电介质材料、阻燃4级材料(FR-4)、双马来酰亚胺三嗪(BT)树脂、聚酰亚胺材料、玻璃增强环氧基体材料或低k和超低k电介质(例如,碳掺杂电介质、氟掺杂电介质、多孔电介质和有机聚合物电介质)。尤其,当使用标准印刷电路板(PCB)工艺来形成封装衬底102时,封装衬底102可以包括FR-4,并且可以由通过FR-4的堆积(build-up)层分离的图案化的铜片来形成在封装衬底102中的导电通路。在封装衬底102中的导电通路可以适当地以衬材料(诸如粘合衬和/或阻隔衬)为边界。
在一些实施例中,在封装衬底102中的导电通路中的一个或多个导电通路可以在封装衬底102的顶表面处的导电触点146与在封装衬底102的底表面处的导电触点140之间延伸。在一些实施例中,在封装衬底102中的导电通路中的一个或多个导电通路可以在凹槽108的底部处的导电触点146与在封装衬底102的底表面处的导电触点140之间延伸。在一些实施例中,在封装衬底102中的导电通路中的一个或多个导电通路可以在封装衬底102的顶表面处的不同导电触点146之间(例如,在凹槽108的底部处的导电触点146与在封装衬底102的顶表面处的不同导电触点146之间)延伸。在一些实施例中,在封装衬底102中的导电通路中的一个或多个导电通路可以在封装衬底102的底表面处的不同导电触点140之间延伸。
本文所公开的管芯114可以包括绝缘材料(例如,如在本领域中已知的在多层中形成的电介质材料)和穿过绝缘材料形成的多个导电通路。在一些实施例中,管芯114的绝缘材料可以包括电介质材料,诸如二氧化硅、氮化硅、氮氧化物、聚酰亚胺材料、玻璃增强环氧基体材料、或者低k或超低k电介质(例如,碳掺杂电介质、氟掺杂电介质、多孔电介质、有机聚合物电介质、光可成像电介质和/或基于苯并环丁烯的聚合物)。在一些实施例中,管芯114的绝缘材料可以包括半导体材料,诸如硅、锗或III-V材料(例如,氮化镓)以及一种或多种额外的材料。例如,绝缘材料可以包括氧化硅或氮化硅。在管芯114中的导电通路可以包括导电迹线和/或导电通孔,并且可以以任何适当的方式连接在管芯114中的导电触点中的任何导电触点(例如,连接在管芯114的相同表面或不同表面上的多个导电触点)。下文参考图29讨论可以被包括在本文所公开的管芯114中的示例性结构。在管芯114中的导电通路可以适当地以衬材料(诸如粘合衬和/或阻隔衬)为边界。
在一些实施例中,管芯114-1可以包括导电通路,以对功率、接地和/或去往/来自在微电子组件100中包括的其它管芯114中的一些管芯的信号进行布线。例如,管芯114-1可以包括穿过衬底通孔(TSV,包括通过阻隔氧化物来与周围的硅或其它半导体材料隔离的导电材料通孔,诸如金属通孔),或者可以包括通过其可以在封装衬底102与在管芯114-1的“顶部”的一个或多个管芯114之间发送的功率、接地和/或信号的其它导电通路(例如,在图1的实施例中,管芯114-2和/或管芯114-3)。在一些实施例中,管芯114-1可以包括导电通路,以在管芯114-1的“顶部”的管芯114中的不同管芯(例如,在图1的实施例中,管芯114-2和管芯114-3)之间对功率、接地和/或信号进行布线。在一些实施例中,管芯114-1可以是在管芯114-1与在微电子组件100中包括的其它管芯114之间传送的信号的源和/或目的地。
在一些实施例中,管芯114-1可以不将电源和/或接地布线至管芯114-2;反而,管芯114-2可以直接地耦合到在封装衬底102中的电源和/或接地线。通过允许管芯114-2直接地耦合到在封装衬底102中的电源和/或接地线,不需要通过管芯114-1来对这样的电源和/或接地线进行布线,允许管芯114-1被制作得更小或者包括更多的有源电路或信号通路。
在一些实施例中,管芯114-1可以仅包括导电通路,以及可以不包含有源电路或无源电路。在其它实施例中,管芯114-1可以包括有源电路或无源电路(例如,晶体管、二极管、电阻器、电感器和电容器,除了别的之外)。在一些实施例中,管芯114-1可以包括一个或多个包含晶体管的器件层(例如,如下文参考图29所讨论的)。当管芯114-1包括有源电路时,可以将电源和/或接地信号进行布线穿过封装衬底102,以及穿过在管芯114-1的底表面上的导电触点122到达管芯114-1。
虽然图1示出在102和/或管芯114中的一个或多个管芯的封装中的特定的数量和布置的导电通路,但这些仅是说明性的,以及可以使用任何适当的数量和布置。例如,本文所公开的导电通路(例如,导电迹线和/或导电通孔)可以由任何适当的导电材料(诸如铜、银、镍、金、铝或其它金属或合金)形成。
在一些实施例中,封装衬底102可以是较低密度介质,以及管芯114-1可以是较高密度介质。如本文所使用的,术语“较低密度”和“较高密度”是相对术语,其表明在较低密度介质中的导电通路(例如,包括导电线和导电通孔)比在高密度介质中的导电通路更大和/或具有更大的间距。在一些实施例中,可以使用具有改进的光刻的改良的半加成工艺或半加成堆积工艺(具有通过改进的激光或光刻工艺形成的小的垂直互连特征)来制造较高密度的介质,同时较低密度介质可以是使用标准PCB工艺来制造的PCB(例如,使用蚀刻化学去除不需要的铜的区域的标准减成工艺,以及具有通过标准激光工艺形成的粗糙的垂直互连特征)。
图1的微电子组件100还可以包括管芯114-2。管芯114-2可以通过DTPS互连150-2来电力地以及机械地耦合到封装衬底102,并且可以通过管芯到管芯(DTD)互连130-1电力地以及机械地耦合到管芯114-1。尤其,封装衬底102的顶表面可以包括一组导电触点146,并且管芯114-2的底表面可以包括一组导电触点122;在管芯114-1的底表面处的导电触点122可以通过DTPS互连150-2电力地以及机械地耦合到在封装衬底102的顶表面处的导电触点146。进一步地,管芯114-1的顶表面可以包括一组导电触点124,并且管芯114-2的底表面可以包括一组导电触点124;在管芯114-2的底表面处的导电触点124可以通过DTD互连130-1电力地以及机械地耦合到在管芯114-1的顶表面处的导电触点124中的一些导电触点。图2是图1的微电子组件100的管芯114-2的底视图,示出“较粗的”导电触点122和“较细的”导电触点124。因此,微电子组件100的管芯114-2可以是单面的管芯(从某种意义上说,管芯114-2仅在单个表面处具有导电触点122/124),以及可以是混合间距管芯(从某种意义上说,管芯114-2包含具有不同间距的多组导电触点122/124)。虽然图2示出导电触点122和导电触点124如均是以矩形阵列来布置的,但是情况不一定如此,以及可以以任何适当的图案(例如,三角形、六边形、矩形、在导电触点122与124之间的不同布置等)来布置导电触点122和124。在同一表面处具有DTPS互连150和DTD互连130的管芯114可以称为混合间距管芯114;更普遍地,在同一表面处具有不同间距的互连130的管芯114可以称为混合间距管芯114。
管芯114-2可以在管芯114-1之上延伸重叠距离191。在一些实施例中,重叠距离191可以在0.5毫米与5毫米之间(例如,在0.75毫米与2毫米之间,或者大约1毫米)。
图1的微电子组件100还可以包括管芯114-3。管芯114-3可以通过DTD互连130-2电力地以及机械地耦合到管芯114-1。尤其,管芯114-3的底表面可以包括一组导电触点124,导电触点124通过DTD互连130-2来电力地以及机械地耦合到在管芯114-1的顶表面处的导电触点124中的一些导电触点。在图1的实施例中,管芯114-3可以是单面、单间距管芯;在其它实施例中,管芯114-3可以是双面(或“多级”或“全向”)管芯,并且可以在管芯114-3的顶表面处安置额外的组件。
如上文所讨论的,在图1的实施例中,管芯114-1可以在微电子组件100的局部区域中提供高密度互连布线。在一些实施例中,管芯114-1的存在可以支持不能完全直接地连接到封装衬底102的细间距半导体管芯(例如,管芯114-2和114-3)的直接芯片安装。尤其,如上所述,管芯114-1可以支持在封装衬底102中无法实现的迹线宽度和间隔。可穿戴和移动电子设备以及物联网(loT)应用的扩散,在推动电子***的尺寸的减小,但是PCB制造工艺的局限性以及在使用过程中热膨胀的机械后果意味着具有细互连间距的芯片不能直接地安装到PCB。本文所公开的微电子组件100的各种实施例可能能够在不牺牲性能或可制造性的情况下,支持具有高密度互连的芯片和具有低密度互连的芯片。
图1的微电子组件100还可以包括管芯114-4。管芯114-4可以通过DTPS互连150-3电力地以及机械地耦合到封装衬底102。尤其,管芯114-4的底表面可以包括一组导电触点122,导电触点122通过DTPS互连150-3来电力地以及机械地耦合到在封装衬底102的顶表面处的导电触点146中的一些导电触点。在图1的实施例中,管芯114-4可以是单面、单间距管芯;在其它实施例中,管芯114-4可以是双面管芯,并且可以在管芯114-4的顶表面处安置额外的组件。诸如表面安装的电阻、电容和/或电感的其它无源组件可以安置在封装衬底102的顶表面或底表面上,或者嵌入在封装衬底102中。
图1的微电子组件100还可以包括电路板133。封装衬底102可以通过在封装衬底102的底表面处的第二级互连137耦合到电路板133。尤其,封装衬底102可以包括在其底表面处的导电触点140,以及电路板133可以包括在其顶表面处的导电触点135;第二级互连137可以电力地以及机械地耦合导电触点135和导电触点140。图1中所示的第二级互连137是焊料球(例如,用于球栅阵列布置),但是可以使用任何适当的第二级互连137(例如,在引脚栅阵列布置中的引脚或焊盘栅阵列布置中的焊盘)。电路板133例如可以是母板,并且可以具有附接到其的其它组件(未示出)。电路板133可以包括导电通路和其它导电触点(未示出),用于通过电路板133来对功率、接地和信号进行布线,如本领域中公知的。在一些实施例中,第二级互连137可以不将封装衬底102耦合至电路板133,但是可以反而将封装衬底102耦合至另一IC封装、***器或任何其它适当的组件。
图1的微电子组件100还可以包括模制材料127。模制材料127可以围绕在封装衬底102上的管芯114中的一个或多个管芯进行延伸。在一些实施例中,模制材料127可以在封装衬底102上的管芯114中的一个或多个管芯上方进行延伸。在一些实施例中,模制材料127可以在管芯114中的一个或多个管芯与封装衬底102之间在相关联的DTPS互连150周围延伸;在这样的实施例中,模制材料127可以用作底部填充材料。在一些实施例中,模制材料127可以在相关联的DTD互连130周围的管芯114中的不同管芯之间延伸;在这样的实施例中,模制材料127可以用作底部填充材料。模制材料127可以包括多种不同的模制材料(例如,底部填充材料和不同的包覆成型材料)。模制材料127可以是绝缘材料,诸如适当的环氧树脂材料。在一些实施例中,模制材料127可以包括作为环氧树脂助熔剂的底部填充材料,当形成DTPS互连150-1和150-2时,其帮助将管芯114-1/114-2焊接到封装衬底102,然后聚合并封装DTPS互连150-1和150-2。可以选择模制材料127以具有热膨胀系数(CTE),热膨胀系数可以减轻或最小化在由在微电子组件100中的不均匀的热膨胀引起的管芯114与封装衬底102之间的应力。在一些实施例中,模制材料127的CTE可以具有介于封装衬底102的CTE(例如,封装衬底102的电介质材料的CTE)与管芯114的CTE之间的值。
图1的微电子组件100还可以包括热界面材料(TIM)129。TIM 129可以包括在聚合物或其它粘合剂中的导热材料(例如,金属颗粒)。TIM 129可以是热界面材料糊剂或导热环氧树脂(如在本领域中已知的,其在施加时可以是流体,并且在固化时可以硬化)。TIM 129可以为由管芯114产生的热量提供易于流向散热器131的路径,在散热器131中热量可以扩散和/或消散。图1的微电子组件100的一些实施例可以包括跨越模制材料127和管芯114的溅射背面金属化(未示出);可以将TIM 129(例如,焊料TIM)安置在该背面金属化上。
图1的微电子组件100还可以包括散热器131。散热器131可以用于将热量从管芯114移开(例如,使得热量可以更容易地由散热器或其它热管理装置消散)。散热器131可以包括任何适当的导热材料(例如,金属、适当的陶瓷等),并且可以包括任何适当的特征(例如,散热片(fin))。在一些实施例中,散热器131可以是集成的散热器。
本文所公开的DTPS互连150可以采用任何适当的形式。在一些实施例中,一组DTPS互连150可以包括焊料(例如,经受热回流以形成DTPS互连150的焊料凸点或焊球)。包括焊料的DTPS互连150可以包括任何适当的焊料材料,诸如铅/锡、锡/铋、共晶锡/银、三元锡/银/铜、共晶锡/铜、锡/镍/铜、锡/铋/铜、锡/铟/铜、锡/锌/铟/铋或者其它合金。在一些实施例中,一组DTPS互连150可以包括各向异性导电材料,诸如各向异性导电膜或各向异性导电胶。各向异性导电材料可以包括分散在非导电材料中的导电材料。在一些实施例中,各向异性导电材料可以包括嵌入在粘合剂或热固性胶膜(例如,热固性联苯型环氧树脂或基于丙烯酸的材料)中的微观导电颗粒。在一些实施例中,导电颗粒可以包括聚合物和/或一种或多种金属(例如,镍或金)。例如,导电颗粒可以包括依次涂覆有聚合物的镍涂覆的金或银涂覆的铜。在另一示例中,导电颗粒可以包括镍。当各向异性导电材料未压缩时,可能没有从材料的一侧到另一侧的导电通路。但是,当各向异性导电材料受到充分压缩时(例如,通过在各向异性导电材料的任一侧的导电触点),靠近压缩的区域的导电材料可以彼此接触,以便在压缩的区域中形成从膜的一侧到另一侧的导电通路。
本文所公开的DTD互连130可以采用任何适当的形式。与在微电子组件中的DTPS互连150相比,DTD互连130可以具有更细的间距。在一些实施例中,在一组DTD互连130的任一侧的管芯114可以是未封装的管芯,和/或DTD互连130可以包括通过焊料附接到导电触点124的小导电凸点或柱(例如,铜凸点或柱)。DTD互连130可能具有太细的间距而不能直接地耦合到封装衬底102(例如,太细而不能用作DTPS互连150)。在一些实施例中,一组DTD互连130可以包括焊料。包括焊料的DTD互连130可以包括任何适当的焊料材料(诸如上文讨论的材料中的任何材料)。在一些实施例中,一组DTD互连130可以包括各向异性导电材料(诸如上文讨论的材料中的任何材料)。在一些实施例中,DTD互连130可以用作为数据传输通道,而DTPS互连150可以用于电源线和地线,除了别的之外。
在一些实施例中,在微电子组件100中的DTD互连130中的一些或全部DTD互连可以是金属到金属互连(例如,铜对铜互连或电镀互连)。在这样的实施例中,可以在不使用介于中间的焊料或各向异性导电材料的情况下,(例如,在升高的压力和/或温度之下)将DTD互连130的任一侧的导电触点124键合在一起。在一些实施例中,可以在金属到金属互连中使用薄焊料帽以适应平面性,并且该焊料可以在加工过程中变成金属间化合物。在利用混合键合的一些金属到金属互连中,在键合在一起的金属之间(例如,在提供相关联的导电触点124的铜焊盘或铜接线柱之间)可能存在电介质材料(例如,氧化硅、氮化硅、碳化硅或有机层)。在一些实施例中,DTD互连130的一侧可以包括金属柱(例如,铜柱),以及DTD互连的另一侧可以包括凹陷在电介质中的金属触点(例如,铜触点)。在一些实施例中,金属到金属互连(例如,铜对铜互连)可以包括贵金属(例如,金)或其氧化物是导电的金属(例如,银)。在一些实施例中,金属到金属互连可以包括可以具有降低的熔点的金属纳米结构(例如,纳米棒)。金属到金属互连可能能够比其它类型的互连更可靠地传导更大的电流;例如,当电流流动时,一些焊料互连可能形成脆性的金属间化合物,并且可能会限制通过这样的互连提供的最大电流以减轻机械故障。
在一些实施例中,在微电子组件100中的DTD互连130中的一些或全部DTD互连可以是焊料互连,其包括具有与在DTPS互连150中的一些或全部DTPS互连中包括的焊料相比更高的熔点的焊料。例如,当在形成DTPS互连150之前形成在微电子组件100中的DTD互连130时(例如,如下文参考图17A-图17F所讨论的),基于焊料的DTD互连130可以使用较高温焊料(例如,具有高于200摄氏度的熔点),而DTPS互连150可以使用较低温焊料(例如,具有低于200摄氏度的熔点)。在一些实施例中,较高温焊料可以包括锡;锡和金;或锡、银和铜(例如,96.5%的锡、3%的银和0.5%的铜)。在一些实施例中,较低温焊料可以包括锡和铋(例如,共晶锡铋)或锡、银和铋。在一些实施例中,较低温焊料可以包括铟,铟和锡或镓。
在本文所公开的微电子组件100中,DTPS互连150中的一些或全部DTPS互连可以具有比DTD互连130中的一些或全部DTD互连要大的间距。DTD互连130可以具有比DTPS互连150要小的间距,这是由于与在一组DTPS互连150的任一侧的管芯114与封装衬底102之间的材料的相似性相比,在一组DTD互连130的任一侧的不同管芯114中的材料的更大的相似性。尤其,在管芯114和封装衬底102的材料成分中的差异可能导致由于在操作期间产生的热(以及在各种制造操作期间施加的热量)而造成的管芯114和封装衬底102的差别的膨胀和收缩。为了减轻由这种差别的膨胀和收缩引起的损坏(例如,开裂、焊料桥接等),可以形成比DTD互连130更大和更远的DTPS互连150,DTPS互连150可能经受更少的热应力,这是由于在DTD互连的任一侧的一对管芯114的更大的材料相似性。在一些实施例中,本文所公开的DTPS互连150可以具有在80微米与300微米之间的间距,而本文所公开的DTD互连130可以具有在7微米与100微米之间的间距。
微电子组件100的元件可以具有任何适当的尺寸。附图中的仅一子集是利用表示尺寸的参考数字来标记的,但这仅仅是为了图示清楚,并且本文所公开的微电子组件100中的任何微电子组件可以包含具有本文讨论的尺寸的组件。例如,在一些实施例中,封装衬底102的厚度164可以在0.1毫米与1.4毫米之间(例如,在0.1毫米与0.35毫米之间、在0.25毫米与0.8毫米之间、或者大约1毫米)。在一些实施例中,凹槽108可以具有在10微米与200微米之间(例如,在10微米与30微米之间、在30微米与100微米之间、在60微米与80微米之间、或者大约75微米)的深度175。在一些实施例中,深度175可以等于在封装衬底102中的一定数量的电介质材料层。例如,深度175可以大约等于在封装衬底102中的一层与五层的电介质材料(例如,两层或三层的电介质材料)之间。在一些实施例中,深度175可以等于在封装衬底102的顶表面的阻焊材料(未示出)的厚度。
在一些实施例中,在管芯114-1的底表面与封装衬底102的近顶表面(在凹槽108的底部)之间的距离179可以小于在管芯114-2的底表面与封装衬底102的近顶表面之间的距离177。在一些实施例中,距离179可以与距离177大约相同。在一些实施例中,在管芯114-2的底表面与封装衬底102的近顶表面之间的距离177可以大于在管芯114-2的底表面与管芯114-1的近顶表面之间的距离193。在其它实施例中,距离177可以小于或等于距离193。
在一些实施例中,管芯114-1的顶表面可以延伸得高于封装衬底102的顶表面,如在图1中所示。在其它实施例中,管芯114-1的顶表面可以与封装衬底102的顶表面大体上共面,或者可以凹进到封装衬底102的顶表面下方。图3示出在前的实施例的示例。虽然附图中的各个附图示出在封装衬底102中具有单个凹槽108的微电子组件100,但是102的厚度可以包括多个凹槽108(例如,具有相同或不同的尺寸,并且各凹槽具有安置在其中的管芯114),或者没有凹槽108。下文将参考图7-8来讨论在前的实施例的示例,以及下文将参考图9-11来讨论在后的实施例的示例。在一些实施例中,代替或除了在封装衬底102的顶表面处的凹槽108之外,凹槽108可以位于封装衬底102的底表面处(例如,接近导电触点140)。
在图1的实施例中,将单个管芯114-2示出为“横跨”封装衬底102和管芯114-1。在本文所公开的微电子组件100的一些实施例中,多个管芯114可以横跨封装衬底102和另一管芯114。例如,图4示出如下实施例:在其中两个管芯114-2均具有安置在底表面处的导电触点122和导电触点124;管芯114-2的导电触点122是经由DTPS互连150-2耦合到在封装衬底102的顶表面处的导电触点146,并且管芯114-2的导电触点124是经由DTD互连130耦合到在管芯114的顶表面处的导电触点124。在一些实施例中,可以穿过封装衬底102将功率和/或接地信号直接地提供给图4的微电子组件100的管芯114,以及管芯114-1可以对在管芯114-2之间的信号进行布线,除了别的之外。
在一些实施例中,管芯114-1可以被布置为在多个其它管芯114之间的桥接,并且还可以具有在其上安置的额外的管芯114。例如,图5示出如下实施例:在其中两个管芯114-2均具有安置在底表面处的导电触点122和导电触点124;管芯114-2的导电触点122是经由DTPS互连150-2耦合到在封装衬底102的顶表面处的导电触点146,并且管芯114-2的导电触点124是经由DTD互连130耦合到在管芯114的顶表面处的导电触点124(例如,如上文参考图4所讨论的)。此外,管芯114-3(或多个管芯114-3,未示出)是通过在这些管芯114的邻近表面上的导电触点124和介于中间的DTD互连130-2(例如,如上文参考图1所讨论的)来耦合至管芯114-1的。
如上所述,在微电子组件100中的任何适当数量的管芯114可以是双面管芯114。例如,图6示出与图1共享多个元件的微电子组件100,但是包括双面管芯114-6。管芯114-6包括在其底表面处的导电触点122和124;在管芯114-6的底表面处的导电触点122是经由DTPS互连150-2耦合到在封装在衬底102的顶表面处的导电触点146,并且在管芯114-6的底表面处的导电触点124是经由DTD互连130-1耦合到在管芯114-1的顶表面处的导电触点124。管芯114-6还包括在其顶表面处的导电触点124;这些导电触点124是通过DTD互连130-3耦合到在管芯114-7的底表面处的导电触点124的。
如上所述,封装衬底102可以包括一个或多个凹槽108,在凹槽108中至少部分地安置了管芯114。例如,图7示出包括封装衬底102的微电子组件100,其中封装衬底102具有两个凹槽:凹槽108-1和凹槽108-2。在图7的实施例中,凹槽108-1嵌套在凹槽108-2中,但是在其它实施例中,多个凹槽108不需要嵌套。在图7中,管芯114-1至少部分地安置在凹槽108-1中,并且管芯114-6和114-3至少部分地安置在凹槽108-2中。在图7的实施例中,如同图6的实施例,管芯114-6包括在其底表面处的导电触点122和124;并且在管芯114-6的底表面处的导电触点122是经由DTPS互连150-2耦合到在封装衬底102的顶表面处的导电触点146,并且在管芯114-6的底表面处的导电触点124是经由DTD互连130-1耦合到在管芯114-1的顶表面处的导电触点124。管芯114-6还包括在其顶表面处的导电触点124;这些导电触点124是通过DTD互连130-3耦合到在管芯114-7的底表面处的导电触点124。进一步地,图7的微电子组件100包括横跨封装衬底102和管芯114-6的管芯114-8。尤其,管芯114-8包括在其底表面处的导电触点122和124;在管芯114-8的底表面处的导电触点122是经由DTPS互连150-3耦合到在封装衬底102的顶表面处的导电触点146,并且在管芯114-8的底表面处的导电触点124是经由DTD互连130-4耦合到在管芯114-6的顶表面处的导电触点124。
在本文所公开的微电子组件100中的各种微电子组件中,单个管芯114可以从“下方”(例如,如上文参考图4和图5所讨论的)或从“上方”桥接到其它管芯114。例如,图8示出类似于图7的微电子组件100的微电子组件100,但是包括两个双面管芯114-9和114-10以及额外的管芯114-11。管芯114-9包括在其底表面处的导电触点122和124;在管芯114-9的底表面处的导电触点122是经由DTPS互连150-3耦合到在封装衬底102的顶表面处的导电触点146,并且在管芯114-9的底表面处的导电触点124是经由DTD互连130-4耦合到在管芯114-6的顶表面处的导电触点124。管芯114-6包括在其顶表面处的导电触点124;这些导电触点124是通过DTD互连130-3耦合到在管芯114-10的底表面处的导电触点124。进一步地,管芯114-11包括在其底表面处的导电触点124;这些导电触点124中的一些导电触点是通过DTD互连130-6来耦合到在管芯114-9的顶表面处的导电触点124,并且这些导电触点124中的一些导电触点是通过DTD互连130-5来耦合到在管芯114-10的顶表面处的导电触点124。因此,管芯114-11可以桥接管芯114-9和114-10。
如上所述,在一些实施例中,封装衬底102可以不包括任何凹槽108。例如,图9示出具有以上文参考图1所讨论的方式相互地互连的管芯114和封装衬底102的实施例,但是在其中管芯114-1未安置在封装衬底102中的凹槽中。反而,将管芯114安置在封装衬底102的顶表面的平面部分上方。本文所公开的包括凹槽108的实施例中的任何适当实施例可以具有不包括凹槽108的对应实施例。例如,图10示出具有以上文参考图4所讨论的方式相互地互连的管芯114和封装衬底102的微电子组件100,但是在其中管芯114-1未安置在封装衬底102中的凹槽中。
在附图中的任何附图中示出的管芯114的布置中的任何布置可以是在微电子组件100中的重复图案的一部分。例如,图11示出微电子组件100的一部分,在其中重复类似图10的布置,具有多个管芯114-1和多个管芯114-2。管芯114-1可以桥接邻近的管芯114-2。一般而言,本文所公开的微电子组件100可以包括管芯114的任何适当的布置。图12-图16是根据各种实施例在各种微电子组件100中的多个管芯114的示例布置的顶视图。从图12-图16中省略了封装衬底102;在这些布置中的管芯114中的一些或所有管芯可以至少部分地安置在封装衬底102中的凹槽108中,或者可以不安置在封装衬底102的凹槽中。在图12-图16的布置中,不同的管芯114可以包括任何适当的电路。例如,在一些实施例中,管芯114A可以是有源管芯或无源管芯,并且管芯114B可以包括输入/输出电路、高带宽存储器和/或增强型动态随机存取存储器(EDRAM)。
图12示出在其中在多个不同管芯114B下方安置管芯114A的布置。管芯114A可以以本文参照管芯114-1所公开的方式中的任何方式连接到封装衬底102(未示出),而管芯114B可以横跨封装衬底102和管芯114A(例如,以本文参照管芯114-2所公开的方式中的任何方式)。图12还示出安置在管芯114A上的管芯114C(例如,以本文参照管芯114-3所公开的方式)。在图12中,管芯114B与管芯114A的边缘和/或拐角“重叠”,而管芯114C完全在管芯114A上方。将管芯114B至少部分地放置在管芯114A的拐角之上,可以减少在管芯114A中的布线拥塞,并且可以提高对管芯114A的利用(例如,在管芯114A与管芯114B之间所需的输入/输出的数量不足够大以要求管芯114A的完整边缘的情况下)。在一些实施例中,管芯114A可以安置在封装衬底102中的凹槽108中。在一些实施例中,管芯114A可以安置在封装衬底102中的凹槽108中,并且管芯114B可以安置在封装衬底102中的一个或多个凹槽108中。在一些实施例中,管芯114A或114B中的任何一者均未安置在凹槽108中。
图13示出在其中在多个不同管芯114B下方安置管芯114A的布置。管芯114A可以以本文参照管芯114-1所公开的方式中的任何方式连接到封装衬底102(未示出),而管芯114B可以横跨封装衬底102和管芯114A(例如,以本文参照管芯114-2所公开的方式中的任何方式)。图13还示出安置在管芯114A上的管芯114C(例如,以本文参照管芯114-3所公开的方式)。在图13中,管芯114B与管芯114A的边缘“重叠”,而管芯114C完全在管芯114A上方。在一些实施例中,管芯114A可以安置在封装衬底102中的凹槽108中。在一些实施例中,管芯114A可以安置在封装衬底102中的凹槽108中,并且管芯114B可以安置在封装衬底102中的一个或多个凹槽108中。在一些实施例中,管芯114A或114B中的任何一者均未安置在凹槽108中。在图13的实施例中,可以将管芯114B和114C布置在矩形阵列的一部分中。在一些实施例中,两个管芯114A可以代替在图13中所示的单个管芯114A,以及一个或多个管芯114C可以“桥接”两个管芯114A(例如,以下文参照图15所讨论的方式)。
图14示出在其中在多个不同管芯114B下方安置管芯114A的布置。管芯114A可以以本文参照管芯114-1所公开的方式中的任何方式连接到封装衬底102(未示出),而管芯114B可以横跨封装衬底102和管芯114A(例如,以本文参照管芯114-2所公开的方式中的任何方式)。在图14中,管芯114B与管芯114A的边缘和/或拐角“重叠”。在一些实施例中,管芯114A可以安置在封装衬底102中的凹槽108中。在一些实施例中,管芯114A可以安置在封装衬底102中的凹槽108中,并且管芯114B可以安置在封装衬底102中的一个或多个凹槽108中。在一些实施例中,管芯114A或114B中的任何一者均未安置在凹槽108中。在图14的实施例中,可以将管芯114B布置在矩形阵列的一部分中。
图15示出在其中在多个不同管芯114B下方安置多个管芯114A使得各管芯114A桥接两个或更多个水平地或垂直地邻近的管芯114B的布置。管芯114A可以以本文参照管芯114-1所公开的方式中的任何方式连接到封装衬底102(未示出),而管芯114B可以横跨封装衬底102和管芯114A(例如,以本文参照管芯114-2所公开的方式中的任何方式)。在图12中,管芯114B与邻近管芯114A的边缘“重叠”。在一些实施例中,管芯114A可以安置在封装衬底102中的一个或多个凹槽108中。在一些实施例中,管芯114A可以安置在封装衬底102中的一个或多个凹槽108中,并且管芯114B可以安置在封装衬底102中的一个或多个凹槽108中。在一些实施例中,管芯114A或114B中的任何一者均未安置在凹槽108中。在图15的实施例中,可以将管芯114A和管芯114B布置在矩形阵列的一部分中。
图16示出在其中在多个不同管芯114B下方安置多个管芯114A使得各管芯114A桥接四个对角地邻近的管芯114B的布置。管芯114A可以以本文参照管芯114-1所公开的方式中的任何方式连接到封装衬底102(未示出),而管芯114B可以横跨封装衬底102和管芯114A(例如,以本文参照管芯114-2所公开的方式中的任何方式)。在图12中,管芯114B与邻近的管芯114A的拐角“重叠”。在一些实施例中,管芯114A可以安置在封装衬底102中的一个或多个凹槽108中。在一些实施例中,管芯114A可以安置在封装衬底102中的一个或多个凹槽108中,并且管芯114B可以安置在封装衬底102中的一个或多个凹槽108中。在一些实施例中,管芯114A或114B中的任何一者均未安置在凹槽108中。在图16中,可以将管芯114A和管芯114B布置在矩形阵列中。
可以使用任何适当的技术来制造本文所公开的微电子组件。例如,图17A-图17F是根据各种实施例用于制造图5的微电子组件100的示例性工艺中的各个阶段的侧面剖视图。虽然以特定顺序示出下文参考图17A-图17F所讨论的操作(以及用于表示制造工艺的附图中的其它附图),但是可以以任何适当的顺序来执行这些操作。此外,虽然在图17A-图17F中示出特定的组件(以及用于表示制造工艺的附图中的其它附图),但是下文参考图17A-图17F所讨论的操作可以用于形成任何适当的组件。在一些实施例中,根据图17A-图17F的工艺来制造的微电子组件100(例如,图1-图11的微电子组件100中的任何微电子组件)可以具有是焊料互连的DTPS互连150-1、以及是非焊料互连的DTD互连130-1和130-2(例如,金属到金属互连或各向异性导电材料互连)。在图17A-图17F的实施例中,可以首先将管芯114组装成“复合管芯”,然后可以将复合管芯耦合至封装衬底102。该方法可以考虑到在DTD互连130的形成中的更严格的公差,并且可以是针对相对小的管芯114而言特别期望的。
图17A示出包括载体202的组件300,在载体202上安置了管芯114-2和114-3。管芯114-2和114-3在管芯202上“倒置”,在某种意义上,管芯114的导电触点122和124背对着载体202,并且管芯114-3的导电触点124背对着载体202。可以使用任何适当的技术(诸如可移除的粘合剂),将管芯114-2和114-3固定到载体上。载体202可以包括用于在随后的制造操作期间提供机械稳定性的任何适当的材料。
图17B示出在将管芯114-1耦合到管芯114-2和114-3之后的组件302。尤其,可以在组件302中“倒置”布置管芯114-1,使得管芯114-1的导电触点124可以(经由DTD互连130-1)耦合到管芯114-2的导电触点124,并且(经由DTD互连130-2)耦合到管芯114-3的导电触点124。可以使用任何适当的技术(诸如金属到金属附接技术、焊接技术或者各向异性导电材料技术)来形成组件302的DTD互连130。
图17C示出包括封装衬底203的组件304。封装衬底203可以在结构上类似于图5的封装衬底102,但是可以不包括封装衬底102的凹槽108。在一些实施例中,可以使用标准的PCB制造工艺来制造封装衬底203,因此,如上所述,封装衬底203可以采用PCB的形式。在一些实施例中,封装衬底203可以是通过在电介质材料上进行层压或旋压以及通过激光钻孔和电镀创建导电通孔和线,来在面板载体(未示出)上形成的一组再分布层。可以使用在本领域中已知的用于制造封装衬底203的任何方法,以及为了简洁起见,在本文中将不进一步详细讨论这样的方法。
图17D示出在封装衬底203(图17C)中形成凹槽108以形成封装衬底102之后的组件306。凹槽108可以具有底表面,在该底表面处暴露导电触点146。可以使用任何适当的技术来形成凹槽108。例如,在一些实施例中,可以将凹槽108向下激光钻孔到在封装衬底203中的平面金属挡块(stop)(未示出);一旦到达金属挡块,则可以去除金属挡块以暴露在凹槽108底部处的导电触点146。在一些实施例中,可以通过机械钻孔形成凹槽108。
图17E示出在“翻转”组件302(图17B)并使管芯114-1和管芯114-2与封装衬底102(图17D)对准以便使在管芯114-1和114-2上的导电触点122与它们在封装衬底102的顶表面处的各自的导电触点146对齐之后的组件308。
图17F示出在管芯114-1/114-2与组件308的封装衬底102(图17E)之间形成DTPS互连150然后去除载体之后的组件310。DTPS互连150可以采用本文所公开的形式中的任何形式(例如,焊料互连、或各向异性导电材料互连),并且可以使用任何适当的技术来形成DTPS互连150(例如,大规模回流工艺或热压键合工艺)。组件310可以采取图5的微电子组件100的形式。可以适当地执行进一步的操作(例如,提供模制材料127、提供TIM 129、提供散热器131、将额外的管芯114附接到封装衬底102等等)。
图18A-图18B是根据各种实施例在用于制造图5的微电子组件100的另一示例性工艺中的各个阶段的侧面剖视图。在一些实施例中,根据图18A-图18B的工艺来制造的微电子组件100(例如,图1-图11的微电子组件100中的任何微电子组件)可以具有是焊料互连的DTPS互连150-1、以及也是焊料互连的DTD互连130-1和130-2。在图18A-图18B的实施例中,管芯114-1可以耦合到封装衬底102,然后可以附接剩余的管芯114。该方法可以适应封装衬底102的公差和翘曲,并且可以是针对相对较大的管芯114而言特别期望的。图17A-图17F的工艺可以有利地与非焊料DTD互连130更兼容,而图18A-图18B的工艺可以有利地涉及对管芯114的更简单的处理。
图18A示出在将管芯114-1耦合到封装衬底102之后的组件312。尤其,管芯114-1可以定位在凹槽108中,并且在管芯114-1的底表面处的导电触点122可以通过DTPS互连150-1来耦合到在封装衬底102的顶表面处的导电触点146。DTPS互连150-1可以采用本文所公开的实施例中的任何实施例的形式,诸如焊料互连或各向异性导电材料互连。可以根据上文参考图17C-17D所讨论的技术中的任何技术来形成封装衬底102。
图18B示出在将管芯114-2和114-3耦合至组件312(图18A)之后的组件314。尤其,管芯114-1的导电触点124可以(经由DTD互连130-1)耦合到管芯114-2的导电触点124,并且(经由DTD互连130-2)耦合到管芯114-3的导电触点124。进一步地,管芯114-2的导电触点122可以经由DTPS互连150-2耦合到在封装衬底102的顶表面处的导电触点146。可以使用诸如焊接技术或各向异性导电材料技术的任何适当的技术,来形成组件314的DTD互连130-1和130-2以及DTPS互连150-2。例如,DTPS互连150-2和DTD互连130-1/130-2可以是焊料互连。组件314可以采用图5的微电子组件100的形式。可以适当地执行进一步的操作(例如,提供模制材料127、提供TIM 129、提供散热器131、将额外的管芯114附接到封装衬底102等等)。
图19A-19H是根据各种实施例在用于制造图5的微电子组件100的另一示例性工艺中的各个阶段的侧面剖视图。在一些实施例中,根据图19A-19H的工艺来制造的微电子组件100(例如,图1-图11的微电子组件100中的任何微电子组件)可以具有是非焊料互连(例如,各向异性导电材料互连)的DTPS互连150-1、以及是焊料互连的DTD互连130-1和130-2。
图19A示出在载体202上包括封装衬底部分113的组件315。封装衬底部分113可以是封装衬底102的“顶部”部分,如下文进一步讨论的,并且可以包括在封装衬底部分113的背对着载体202的表面处的导电触点146。载体202可以采用本文所公开的形式中的任何形式。可以使用任何适当的技术(诸如再分布层技术)在载体202上形成封装衬底部分113。
图19B示出在组件315(图19A)的封装衬底部分113中形成腔体111之后的组件316。例如,可以使用上文参照图17D的凹槽108所讨论的技术中的任何技术来形成腔体111。如下文进一步详细讨论的,腔体111可以对应于凹槽108。
图19C示出在将管芯114-1定位在组件316(图19B)的腔体111中之后的组件318。可以将管芯114-1定位在腔体111中,以便导电触点122面向载体202,并且导电触点124背对着载体202。在一些实施例中,可以使用取放机器来将管芯114-1放置在载体202上的腔体111中。
图19D示出在将管芯114-2和管芯114-3耦合到组件318(图19C)并且在管芯114周围提供模制材料127之后的组件320。尤其,管芯114-1的导电触点124可以(经由DTD互连130-1)耦合到管芯114-2的导电触点124,并且(经由DTD互连130-2)耦合到管芯114-3的导电触点124。进一步地,管芯114-2的导电触点122可以经由DTPS互连150-2来耦合到在封装衬底102的顶表面处的导电触点146。可以使用诸如焊接技术或各向异性导电材料技术的任何适当的技术,来形成组件314的DTD互连130-1和130-2以及DTPS互连150-2。例如,DTPS互连150-2和DTD互连130-1/130-2可以是焊料互连。模制材料127可以采用本文所公开的形式中的任何形式,并且可以为进一步的制造操作提供机械支撑。
图19E示出在将另一载体204附接到组件320(图19D)的顶表面之后的组件321。载体204可以采用本文所公开的载体202的实施例中的实施例中的任何实施例的形式。
图19F示出在从组件321(图19E)中移除载体202并且翻转结果以便暴露封装衬底部分113和管芯114-1的导电触点122之后的组件322。
图19G示出在组件322(图19F)的封装衬底部分113上形成额外的封装衬底部分115以形成封装衬底102之后的组件324。可以使用任何适当的技术来形成封装衬底部分113,这些技术包括上文参考图19A所讨论的技术中的任何技术、无凸点堆积层技术、基于载体的面板级无芯封装衬底制造技术、或者嵌入式面板级键合技术。在一些实施例中,形成封装衬底部分115可以包括:作为形成封装衬底102的接近导电触点146的一部分,利用金属或其它导电材料来对管芯114-1的导电触点122进行电镀;因此,在管芯114-1与封装衬底102之间的DTPS互连150-1可以是电镀互连。
图19H示出在从组件324(图19G)中移除载体204并且翻转结果之后的组件325。组件325可以采用图5的微电子组件100的形式。可以适当地执行进一步的操作(例如,提供TIM129、提供散热器131、将额外的管芯114附接到封装衬底102等等)。
在上文参考图1-图11所讨论的微电子组件100中,管芯114-1直接地耦合到至少一个管芯114-2,而没有封装衬底102的任何介于中间的部分。在本文所公开的微电子组件100的其它实施例中,可以在嵌入式管芯114-1与管芯114-2之间安置封装衬底102的一部分。图20-图22是根据各种实施例包括这样的特征的示例性微电子组件100的侧面剖视图。尤其,图20-图22示出类似于在图1中所示出的布置的管芯114-1、114-2、114-3和114-4的布置,但是其进一步包括在管芯114-1的顶表面与封装衬底102的顶表面之间的封装衬底部分148。管芯114-2、114-3和114-4可以全部耦合到该封装衬底部分148。例如,管芯114-1可以包括在其底表面处的导电触点122(其经由DTPS互连150-1耦合到封装衬底102的导电触点146),并且管芯114-1可以包括在其顶表面处的导电触点122(其经由DTPS互连150-4耦合到封装衬底102的导电触点146(在封装衬底部分148中))。
在一些实施例中,封装衬底部分148可以包括具有较高导电通路密度的一个或多个区域149(例如,在其中管芯114-2的覆盖区与管芯114-1的覆盖区重叠并且封装衬底部分148包括在管芯114-2与管芯114-1之间的导电通路的区域,或者在其中管芯114-3的覆盖区与管芯114-1的覆盖区重叠并且封装衬底部分148包括在管芯114-3与管芯114-1之间的导电通路的区域)。因此,管芯114-2可以是包括较大间距导电触点122A和较小间距导电触点122B的混合间距管芯;较大间距导电触点122A可以(通过DTPS互连150-2中的一些DTPS互连)耦合到在封装衬底102的顶表面上的导电触点146(它们本身通过大部分封装衬底102耦合到导电通路),并且较小间距导电触点122B可以(通过DTPS互连150-2中的一些DTPS互连)耦合到在封装衬底102的顶表面上的导电触点146(它们本身耦合到穿过封装衬底部分148的导电通路并耦合到管芯114-1)。类似地,与管芯114-4的底表面处的导电触点122(其可以经由DTPS互连150-3耦合到穿过封装衬底102的密度较小的导电通路)的间距相比,在管芯114-3的底表面处的导电触点122(其可以经由DTPS互连150-5耦合到穿过封装衬底部分148到管芯114-1的密集的导电通路)的间距可以更小。封装衬底102还可以包括与管芯114-1邻近的部分151、以及在管芯114-1下方的部分153。
图20示出在其中通过导线和通孔来提供在封装衬底102中的导电通路的实施例,如在本领域中已知的。在其它实施例中,封装衬底102可以包括导电柱(例如,铜柱)和其它结构。例如,图21示出类似于图20的微电子组件100,但是在其中封装衬底部分151包括安置在管芯114-1周围的多个导电柱134。导电柱134可以大体上由模制材料132围绕,该模制材料132可以采用本文所公开的模制材料127中的任何模制材料的形式。导电柱134可以是在封装衬底部分148与封装衬底部分153之间的导电通路的一部分。在本文所公开的实施例中的任何适当的实施例中,可以使用非导电柱(例如,由永久抗蚀剂或电介质形成的柱)来代替导电柱134,或除了导电柱134之外,还可以使用非导电柱。
导电柱134可以由诸如金属的任何适当的导电材料来形成。在一些实施例中,导电柱134可以包括铜。导电柱134可以具有任何适当的尺寸。例如,在一些实施例中,单个导电柱134可以具有在1:1与4:1之间(例如,在1:1与3:1之间)的高宽比(高度:直径)。在一些实施例中,单个导电柱134可以具有在10微米与300微米之间的直径。在一些实施例中,单个导电柱134可以具有在50微米与400微米之间的直径。
在封装衬底102包括多个导电柱134的一些实施例中,封装衬底部分151还可以包括放置环。例如,图22示出类似于图21的微电子组件100的实施例,但是其还包括放置环136。放置环136可以由任何适当的材料(例如,具有一层有机材料、不锈钢或非导电材料(诸如玻璃、蓝宝石、聚酰亚胺或具有二氧化硅的环氧树脂)的电镀铜特征)来形成,并且可以进行成形以便紧贴在管芯114-1周围。在一些实施例中,放置环136可以具有倾斜或笔直的壁以帮助将管芯114-1引导到位。因此,放置环136的形状可以补足管芯114-1的覆盖区的形状,并且放置环136可以帮助在制造期间对准管芯114-1,如下文进一步讨论的。
包括嵌入式管芯114的微电子组件100可以包括对管芯114的任何适当的布置。例如,可以利用嵌入在封装衬底中的管芯114A,利用嵌入在封装衬底102中的管芯114A和114B,或者利用嵌入在封装衬底102中的管芯114A、114B和114C来实现在图12-图16中所示的布置中的任何布置。此外,根据图20-图22的实施例中的任何实施例,可以利用嵌入在封装衬底102中的管芯114-1(和可选地,管芯114中的更多个管芯)来实现在图1-图11中所示的布置中的任何布置。
可以使用任何适当的技术来制造具有嵌入式管芯114-1(例如,具有在管芯114-1与管芯114-2之间的封装衬底部分148)的微电子组件100。例如,图23A-图23B是根据各种实施例在用于制造图20的微电子组件100的示例性工艺中的各个阶段的侧面剖视图。在一些实施例中,根据图23A-图23B的工艺来制造的微电子组件100可以具有是焊料互连的DTPS互连150-1、以及是非焊料互连(例如,电镀互连)的DTPS互连150-4。
图23A示出在组件312(图18A)上形成封装衬底部分148之后的组件326。可以使用任何适当的技术(诸如上文参照图19G的封装衬底部分115的形成所讨论的技术中的任何技术)来形成封装衬底部分148。在一些实施例中,形成封装衬底部分148可以包括:作为形成封装衬底102的接近导电触点146的一部分,利用金属或其它导电材料来对管芯114-1的导电触点122进行电镀;因此,在管芯114-1与封装衬底部分148之间的DTPS互连150-4可以是电镀互连。
图23B示出在将管芯114-2、114-3和114-4附接到组件326(图23A)之后的组件328。可以使用诸如焊接技术或各向异性导电材料技术的任何适当的技术来形成在管芯114-2、114-3和114-4与封装衬底102之间的DTPS互连150。
图24A-24E是根据各种实施例在用于制造图21的微电子组件100的示例性工艺中的各个阶段的侧面剖视图。在一些实施例中,根据图24A-24E的工艺来制造的微电子组件100可以具有是焊料互连的DTPS互连150-1、以及是非焊料互连(例如,电镀互连)的DTPS互连150-4。
图24A示出包括封装衬底部分153的组件330。可以使用诸如PCB技术或再分布层技术的任何适当技术来制造封装衬底部分153。
图24B示出在组件330(图24A)的封装衬底部分153的顶表面上形成导电柱134之后的组件332。导电柱134可以安置在不存在导电柱134的去填充(de-population)区域155周围。导电柱134可以采用本文所公开的实施例中的任何实施例的形式,并且可以是使用任何适当的技术(例如,电镀)来形成的。例如,导电柱134可以包括铜。
图24C示出在将管芯114-1放置在组件332(图24B)的去填充区域155中并将管芯114-1耦合到封装衬底部分153之后的组件334。尤其,在管芯114-1的底表面处的导电触点122可以经由DTPS互连150-1耦合到在封装衬底部分153的顶表面处的导电触点146。DTPS互连150-1可以采用本文公开的形式中的任何形式,诸如焊料互连或各向异性导电材料互连。
图24D示出在管芯114-1周围提供模制材料132和组件334(图24C)的导电柱134以完成封装衬底部分151之后的组件336。在一些实施例中,模制材料132可以是首先沉积在导电柱134和管芯114-1的顶部上和之上,然后抛光回去以暴露在管芯114-1的顶表面和导电柱134的顶表面处的导电触点122。
图24E示出在组件336(图24D)上形成封装衬底部分148之后的组件338。可以使用任何适当的技术(诸如上文参照图19G的封装衬底部分115的形成所讨论的技术中的任何技术)来形成封装衬底部分148。在一些实施例中,形成封装衬底部分148可以包括:作为形成封装衬底102的接近导电触点146的一部分,利用金属或其它导电材料来对管芯114-1的导电触点122进行电镀;因此,在管芯114-1与封装衬底部分148之间的DTPS互连150-4可以是电镀互连。然后,可以根据上文参照图23B所讨论的技术中的任何技术将管芯114-2、114-3和114-4附接到封装衬底部分148的顶表面,以形成图21的微电子组件100。
图25A-图25F是根据各种实施例在用于制造图22的微电子组件100的示例性工艺中的各个阶段的侧面剖视图。在一些实施例中,根据图25A-图25F的工艺来制造的微电子组件100可以具有是非焊料互连(例如,电镀互连)的DTPS互连150-1、以及是非焊料互连(例如,电镀互连)的DTPS互连150-4。
图25A示出在载体202上形成多个导电柱134和放置环136之后的组件340。导电柱134可以采用本文所公开的形式中的任何形式,并且可以是使用任何适当的技术(例如,上文参照图24B所讨论的技术)来形成的。放置环136可以采用本文所公开的形式中的任何形式,并且可以是使用任何适当的技术(例如,本文所公开的任何技术)来形成的。放置环136可以围绕在其中不存在导电柱134的去填充区域155。
图25B示出在将管芯114-1定位在组件340(图25A)的放置环136内的去填充区域155中之后的组件342。如上所述,放置环136可以补足管芯114-1的覆盖区,允许管芯114-1被适当地定位。
图25C示出在组件342(图25B)的导电柱134和放置环136周围提供模制材料132以完成封装衬底部分151之后的组件344。在一些实施例中,可以首先在导电柱134和管芯114-1的顶部上和之上沉积模制材料132,然后抛光回去以在管芯114-1的表面和导电柱134的表面处暴露导电触点122。
图25D示出在组件344(图25C)上形成封装衬底部分153之后的组件346。可以使用任何适当的技术(诸如上文参照图19G的封装衬底部分115的形成所讨论的技术中的任何技术)来形成封装衬底部分153。在一些实施例中,形成封装衬底部分153可以包括:作为形成封装衬底102的接近导电触点146的一部分,利用金属或其它导电材料来对管芯114-1的导电触点122进行电镀;因此,在管芯114-1与封装衬底部分148之间的DTPS互连150-1可以是电镀互连。
图25E示出在将另一载体204附接到组件346(图25D)的顶表面之后的组件347。载体204可以采取本文所公开的载体202的实施例中的任何实施例的形式。
图25F示出在从组件347(图25E)中移除载体202并且翻转结果使得暴露封装衬底部分151和管芯114-1的其它导电触点122之后的组件348。然后,可以根据上文参照图24E所讨论的技术中的任何技术,在组件348上形成封装衬底部分148,以及管芯114-2、114-3和114-4可以附接到封装衬底部分148的顶表面(例如,根据上文参照图23B所讨论的技术中的任何技术)以形成图21的微电子组件100。
在本文所公开的实施例中的任何实施例中,可以通过组装两个单独地制造的子部分来形成封装衬底102的一部分。例如,图26A-26D是根据各种实施例在用于制造图21的微电子组件100的另一示例性工艺中的各个阶段的侧面剖视图。图26A-26D的工艺包括从两个子部分组装封装衬底部分153,但是任何封装衬底102(或者其一部分)可以是从多个子部分形成的。
图26A示出在形成封装衬底子部分153A并在其上形成导电柱134之后的组件350。导电柱134可以采用本文所公开的实施例中的任何实施例的形式,并且封装衬底子部分153A可以表示封装衬底部分153的上半部,如下文所进一步讨论的。
图26B示出在将管芯114-1附接到组件350(图26A)、在导电柱134和管芯114-1周围提供模制材料132以完成封装衬底部分151、并在封装衬底部分151上形成封装衬底部分148之后的组件352。这些操作可以采用上文论述的形式中的任何形式。
图26C示出在使组件352(图26B)与封装衬底子部分153B对准之后的组件354。尤其,可以使封装衬底子部分153A接近封装衬底子部分153B。
图26D示出在将组件354(图26C)的封装衬底子部分153A和封装衬底子部分153B耦合在一起以形成封装衬底部分153之后的组件356。管芯114-2、114-3和管芯114-4可以附接到封装衬底部分148的顶表面(例如,根据上文参照图23B所讨论的技术中的任何技术,诸如焊料或各向异性导电材料技术)以形成图21的微电子组件100。
即使当管芯114-1未嵌入在封装衬底102中时(例如,即使当不存在封装衬底部分148时),本文所公开的微电子组件100也可以包括在封装衬底102中的导电柱134。例如,图27示出示例性微电子组件100,在其中封装衬底102包括不具有封装衬底部分148的导电柱134。在图27的微电子组件100中,在管芯114-2的底表面处的导电触点122经由DTPS互连150-2耦合到导电柱134,并且在管芯114-2的底表面处的导电触点124是经由DTD互连130-2耦合到在管芯114-1的顶表面处的导电触点122。本文所公开的其它微电子组件100中的任何微电子组件可以适当地包括导电柱134。
本文所公开的微电子组件100可以用于任何适当的应用。例如,在一些实施例中,微电子组件100可以用于为现场可编程门阵列(FPGA)收发机和III-V放大器提供超高密度和高带宽互连。例如,管芯114-1可以包括FPGA收发机电路或III-V放大器,并且管芯114-2可以包括FPGA逻辑。与通过介于中间的设备(例如,单独的硅桥)对这样的通信进行布线相比,在管芯114-1与管芯114-2之间的通信可能经历更少的延迟。在一些实施例中,在管芯114-1与管芯114-2之间的DTD互连130-1的间距可以小于100微米(例如,在25微米与55微米之间),并且在管芯114-2与封装衬底102之间的DTPS互连150-2的间距可以大于80微米(例如,在100与150微米之间)。这样的应用特别适用于军事电子、5G无线通信、无线千兆联盟通信和/或毫米波通信。
更普遍地,本文所公开的微电子组件100可以允许将不同种类的功能电路的“块”分配到管芯114中的不同的管芯中,而不是按照一些传统方法将所有电路都包括在单个大管芯中。在一些这样的传统方法中,单个大管芯将包括所有这些不同的电路以实现在电路之间的高带宽、低损耗通信,并且可以选择性地禁用这些电路中的一些或全部电路以调整大管芯的能力。但是,因为微电子组件100的DTD互连130可以允许在管芯114中的不同管芯之间的高带宽低损耗的通信,所以可以将不同的电路分配到不同的管芯114中,降低制造的总成本、提高产量、并通过允许容易地交换不同的管芯114(例如,使用不同的制造技术来形成的管芯114)以实现不同的功能来增加设计灵活性。此外,与如果将两个管芯的电路组合成远离散热器131的单个管芯相比,堆叠在另一管芯114的顶部上的管芯114可以更靠近散热器131,改善热性能。
在另一示例中,在微电子组件100中包括有源电路的管芯114-1可以用于在其它管芯114之间(例如,在各种实施例中,在管芯114-2与114-3之间、或者在多个不同的管芯114-2之间)提供“有源”桥。在一些这样的实施例中,可以通过封装衬底102向管芯114-1和其它管芯114的“底部”提供功率输出,而不在管芯140-1上方要求封装衬底102的通过其来对功率进行布线的额外的层。
在另一示例中,在微电子组件100中的管芯114-1可以是处理设备(例如,中央处理单元、图形处理单元、FPGA、调制解调器、应用处理器等等),以及管芯114-2可以包括高带宽存储器、收发机电路和/或输入/输出电路(例如,双数据速率传输电路、***组件互连快速电路等等)。在一些实施例中,管芯114-1可以包括一组导电触点124以与高带宽存储器管芯114-2接合,包括另一组导电触点124以与输入/输出电路管芯114-2接合等等。可以为即将到来的应用选择特定的高带宽存储管芯114-2、输入/输出电路管芯114-2等等。
在另一示例中,在微电子组件100中的管芯114-1可以是高速缓冲存储器(例如,第三级高速缓冲存储器),并且一个或多个管芯114-2可以是共享管芯114-1的高速缓冲存储器的处理设备(例如,中央处理单元、图形处理单元、FPGA、调制解调器、应用处理器等等)。
本文所公开的微电子组件100可以被包括在任何适当的电子组件中。图28-图31示出可以包括本文所公开的微电子组件100中的任何微电子组件的装置、或者可以被包括在本文所公开的微电子组件100中的任何微电子组件中的装置的各种示例。
图28是可以被包括在本文所公开的微电子组件100中的任何微电子组件中的晶圆1500和管芯1502(例如,作为管芯114中的任何适当的管芯)的顶视图。晶圆1500可以由半导体材料组成,并且可以包括一个或多个管芯1502,管芯1502具有形成在晶圆1500的表面上的IC结构。管芯1502中的各管芯可以是包括任何适当的IC的半导体产品的重复单元。在对半导体产品的制造完成之后,晶圆1500可以经历分离工艺,在其中管芯1502彼此分离以提供半导体产品的离散“芯片”。管芯1502可以是本文所公开的管芯114中的任何管芯。管芯1502可以包括一个或多个晶体管(例如,下文讨论的图29的晶体管1640中的一些晶体管)、支撑电路以将电信号布线到晶体管、无源组件(例如,信号迹线、电阻、电容或电感)和/或任何其它IC组件。在一些实施例中,晶圆1500或管芯1502可以包括存储器件(例如,随机存取存储器(RAM)器件、诸如静态RAM(SRAM)器件、磁性RAM(MRAM)器件、电阻性RAM(RRAM)器件、导电桥接RAM(CBRAM)器件等)、逻辑器件(例如,AND、OR、NAND或NOR门)或者任何其它适当的电路元件。这些器件中的多个器件可以组合在单个管芯1502上。例如,由多个存储器件形成的存储阵列可以形成在与处理设备(例如,图31的处理设备1802)或者其它逻辑的相同的管芯1502上,其中其它逻辑被配置为将信息存储在存储设备中或者执行存储在存储阵列中的指令。可以使用管芯到晶圆组装技术来制造本文所公开的微电子组件100中的各种微电子组件,在该管芯到晶圆组装技术中一些管芯114附接到包括管芯114中的其它管芯的晶圆1500,并且随后将晶圆1500单个化。
图29是可以被包括在本文所公开的微电子组件100中的任何微电子组件(例如,在管芯114中的任何管芯中)中的IC器件1600的剖面侧视图。IC器件1600中的一个或多个IC器件可以被包括在一个或多个管芯1502(图28)中。IC器件1600可以形成在管芯衬底1602(例如,图28的晶圆1500)上,并且可以被包括在管芯(例如,图28的管芯1502)中。管芯衬底1602可以是由包括例如n型或p型材料***(或两者的组合)的半导体材料***组成的半导体衬底。例如,管芯衬底1602可以包括使用块状硅或绝缘体上硅(SOI)子结构来形成的晶体衬底。在一些实施例中,可以使用代用材料形成管芯衬底1602,这些材料可以与硅结合或者可以不与硅结合,这些材料包括但不限于锗、锑化铟、碲化铅、砷化铟、磷化铟、砷化镓或锑化镓。也可以使用分类为II-VI、III-V或IV族的进一步的材料来形成管芯衬底1602。虽然这里描述了从其可以形成管芯衬底1602的材料的一些示例,但是可以使用可以用作针对IC器件1600的基础的任何材料。管芯衬底1602可以是单个管芯(例如,图28的管芯1502)或晶圆(例如,图28的晶圆1500)的一部分。
IC器件1600可以包括安置在管芯衬底1602上的一个或多个器件层1604。器件层1604可以包括在管芯衬底1602上形成的一个或多个晶体管1640(例如,金属氧化物半导体场效应晶体管(MOSFET))的特征。例如,器件层1604可以包括一个或多个源极和/或漏极(S/D)区域1620、用于控制在S/D区1620之间的晶体管1640中的电流流动的栅极1622、以及用于对去往/来自S/D区1620的电信号进行布线的一个或多个S/D触点1624。晶体管1640可以包括为了清楚描述起见而未描绘的额外的特征,诸如器件隔离区域、栅极触点等等。晶体管1640并不限于在图29中所描绘的类型和配置,并且可以包括多种其它的类型和配置(诸如例如,平面晶体管、非平面晶体管或两者的组合)。非平面晶体管可以包括诸如双栅极晶体管或三栅极晶体管的FinFET晶体管、以及诸如纳米带和纳米线晶体管的环绕或全环绕栅极晶体管。
各晶体管1640可以包括由至少两层、栅极电介质和栅电极形成的栅极1622。栅极电介质可以包括一层或层堆叠。一层或多层可以包括氧化硅、二氧化硅、碳化硅和/或高k电介质材料。高k电介质材料可以包括诸如铪、硅、氧、钛、钽、镧、铝、锆、钡、锶、钇、铅、钪、铌和锌的元素。可以在栅极电介质中使用的高k材料的示例包括但不限于氧化铪、氧化铪硅、氧化镧、氧化镧铝、氧化锆、氧化锆硅、氧化钽、氧化钛、氧化钡锶钛、氧化钡钛、氧化锶钛、氧化钇、氧化铝、氧化铅钪钽和铌酸锌铅。在一些实施例中,当使用高k材料时,可以对栅极电介质执行退火工艺以改善其质量。
栅电极可以形成在栅极电介质上,并且可以取决于晶体管1640是p型金属氧化物半导体(PMOS)还是n型金属氧化物半导体(NMOS)晶体管来包括至少一种p型功函数金属或n型功函数金属。在一些实施方式中,栅电极可以由两个或更多个金属层的堆叠组成,其中一个或更多个金属层是功函数金属层,并且至少一个金属层是填充金属层。可以出于其它目的来包括进一步的金属层(诸如阻隔层)。对于PMOS晶体管,可以用于栅电极的金属包括但不限于:钌、钯、铂、钴、镍、导电金属氧化物(例如,氧化钌)、以及下文参考NMOS晶体管讨论的金属中的任何金属(例如,用于功函数调谐)。对于NMOS晶体管,可以用于栅电极的金属包括但不限于:铪、锆、钛、钽、铝、这些金属的合金、这些金属的碳化物(例如,碳化铪、碳化锆、碳化钛、碳化钽和碳化铝)、以及上文参考PMOS晶体管讨论的金属中的任何金属(例如,用于功函数调谐)。
在一些实施例中,当看作晶体管1640的沿着源极-沟道-漏极方向的横截面时,栅电极可以由U形结构组成,该U形结构包括大体上平行于管芯衬底1602的表面的底部和大体上垂直于管芯衬底1602的顶表面的两个侧壁部分。在其它实施例中,形成栅电极的金属层中的至少一个金属层可以简单地是大体上平行于管芯衬底1602的顶表面的平面层,并且不包括大体上垂直于管芯衬底1602的顶表面的侧壁部分。在其它实施例中,栅电极可以由U形结构和平面非U形结构的组合组成。例如,栅电极可以由在一个或多个平面的非U形层顶上形成的一个或多个U形金属层组成。
在一些实施例中,可以在栅极堆叠的相对侧形成一对侧壁间隔体以托住(bracket)栅极堆叠。侧壁间隔体可以由诸如氮化硅、氧化硅、碳化硅、掺杂碳的氮化硅和氮氧化硅的材料形成。用于形成侧壁间隔体的工艺在本领域中是众所周知的,并且通常包括沉积和蚀刻工艺步骤。在一些实施例中,可以使用多个间隔体对;例如,可以在栅极堆叠的相对侧形成两对、三对或四对侧壁间隔体。
可以在邻近各晶体管1640的栅极1622的管芯衬底1602内形成S/D区1620。可以例如使用注入/扩散工艺或蚀刻/沉积工艺来形成S/D区1620。在之前的工艺中,可以将诸如硼、铝、锑、磷或砷的掺杂剂离子注入到管芯衬底1602中以形成S/D区1620。激活了掺杂剂并使它们进一步扩散到管芯衬底1602的退火工艺,可以遵循离子注入工艺。在后面的工艺中,可以首先蚀刻管芯衬底1602,以在S/D区域1620的位置处形成凹槽。然后,可以执行外延沉积工艺,以利用用于制造S/D区1620的材料来填充凹槽。在一些实现方式中,可以使用诸如硅锗或碳化硅的硅合金来制造S/D区1620。在一些实施例中,外延地沉积的硅合金可以是利用诸如硼、砷或磷的掺杂剂在原位进行掺杂的。在一些实施例中,可以使用诸如锗或III-V族材料或合金的一种或多种替代的半导体材料来形成S/D区1620。在进一步的实施例中,可以使用一层或多层的金属和/或金属合金来形成S/D区1620。
可以通过安置在器件层1604上的一个或多个互连层(在图29中示为互连层1606-1610),将诸如功率和/或输入/输出(I/O)信号的电信号布线为去往和/或来自器件层1604的器件(例如,晶体管1640)。例如,器件层1604的导电特征(例如,栅极1622和S/D触点1624)可以与互连层1606-1610的互连结构1628电耦合。一个或多个互连层1606-1610可以形成IC器件1600的金属化堆叠(还称为“ILD堆叠”)1619。
可以在互连层1606-1610内布置互连结构1628,以根据多种多样的设计来对电信号进行布线;尤其,布置并不限于在图29中所描绘的互连结构1628的特定配置。虽然在图29中描绘了特定数量的互连层1606-1610,但是本公开内容的实施例包括具有比所描绘的更多或更少的互连层的IC器件。
在一些实施例中,互连结构1628可以包括利用诸如金属的导电材料来填充的线1628a和/或通孔1628b。线1628a可以被布置为:在与在其上形成器件层1604的管芯衬底1602的表面大体上平行的平面的方向上对电信号进行布线。例如,从图29的视角,线1628a可以在进入和离开页面的方向上来对电信号进行布线。通孔1628b可以被布置为在与在其上形成器件层1604的管芯衬底1602的表面大体上垂直的平面的方向上对电信号进行布线。在一些实施例中,通孔1628b可以将不同的互连层1606-1610的线1628a电耦合在一起。
互连层1606-1610可以包括安置在互连结构1628之间的电介质材料1626,如在图29中所示。在一些实施例中,在互连层1606-1610的不同层中的互连结构1628之间安置的电介质材料1626可以具有不同的成分;在其它实施例中,在不同的互连层1606-1610之间的电介质材料1626的成分可以相同。
可以直接地在器件层1604上形成第一互连层1606(称为金属1或“Ml”)。在一些实施例中,第一互连层1606可以包括线1628a和/或通孔1628b,如所示出的。第一互连层1606的线1628a可以与器件层1604的触点(例如,S/D触点1624)耦合。
可以直接地在第一互连层1606上形成第二互连层1608(称为金属2或“M2”)。在一些实施例中,第二互连层1608可以包括通孔1628b,以将第二互连层1608的线1628a与第一互连层1606的线1628a进行耦合。虽然为了清楚起见,在结构上利用在各互连层内(例如,在第二互连层1608内)的线路来描绘线1628a和通孔1628b,但在一些实施例中,线1628a和通孔1628b可以是在结构上和/或材料上连续的(例如,在双镶嵌工艺期间同时地填充的)。
可以根据结合第二互连层1608或第一互连层1606所描述的类似技术和配置,在第二互连层1608上连续地形成第三互连层1610(称为金属3或“M3”)(以及额外的互连层,如预期的)。在一些实施例中,在IC器件1600中的金属化堆叠1619中“更高”的互连层(即,距离器件层1604更远)可以更厚。
IC器件1600可以包括阻焊材料1634(例如,聚酰亚胺或类似材料)和在互连层1606-1610上形成的一个或多个导电触点1636。在图29中,将导电触点1636示出为采用焊盘的形式。导电触点1636可以与互连结构1628电耦合并且被配置为将晶体管1640的电信号布线到其它外部设备。例如,可以在一个或多个导电触点1636上形成焊料键合,以将包括IC器件1600的芯片与另一组件(例如,电路板)进行机械耦合和/或电耦合。IC器件1600可以包括额外的或替代的结构,以对来自互连层1606-1610的电信号进行布线;例如,导电触点1636可以包括将电信号布线到外部组件的其它类似特征(例如,接线柱)。视情况而定,导电触点1636可以用作导电触点122或124。
在IC器件1600是双面管芯(例如,类似管芯114-1)的一些实施例中,IC器件1600可以在器件层1604的相对侧包括另一金属化堆叠(未示出)。该金属化堆叠可以包括如上文参考互连层1606-1610所讨论的多个互连层,以在器件层1604与在IC器件1600中从导电触点1636相对侧的额外的导电触点(未示出)之间提供导电通路(例如,包括导电线和通孔)。视情况而定,这些额外的导电触点可以用作导电触点122或124。
在IC器件1600是双面管芯(例如,类似于管芯114-1)的其它实施例中,IC器件1600可以包括穿过管芯衬底1602的一个或多个TSV;这些TSV可以与器件层1604接触,并且可以在器件层1604与在IC器件1600中从导电触点1636相对侧的额外的导电触点(未示出)之间提供导电通路。视情况而定,这些额外的导电触点可以用作导电触点122或124。
图30是可以包括本文所公开的微电子组件100中的任何微电子组件的IC器件组件1700的剖面侧视图。在一些实施例中,IC器件组件1700可以是微电子组件100。IC器件组件1700包括安置在电路板1702(其可以是例如母板)上的多个组件。IC器件组件1700包括安置在电路板1702的第一面1740和电路板1702的相对的第二面1742上的组件;通常,组件可以安置在面1740和1742中的一者或两者上。下文参考IC器件组件1700讨论的IC封装中的任何IC封装可以采用本文所公开的微电子组件100的实施例中的任何适当实施例的形式。
在一些实施例中,电路板1702可以是包括多个金属层的PCB,该多个金属层通过电介质材料层彼此分开并且通过导电通孔来互连。可以以期望的电路图案形成金属层中的任何一个或多个金属层,以在耦合到电路板1702的组件之间对电信号进行布线(可选地与其它金属层结合)。在其它实施例中,电路板1702可以是非PCB衬底。在一些实施例中,电路板1702可以是例如电路板133。
在图30中所示的IC器件组件1700包括:通过耦合组件1716耦合到电路板1702的第一面1740的***器上封装(package-on-interposer)结构1736。耦合组件1716可以将***器上封装结构1736电力地以及机械地耦合到电路板1702,并且可以包括焊球(如在图30中所示)、插座的凸部和凹部、粘合剂、底部填充材料和/或任何其它适当的电气和/或机械耦合结构。
***器上封装结构1736可以包括通过耦合组件1718耦合到***器1704的IC封装1720。耦合组件1718可以采用针对应用的任何适当的形式,诸如上文参照耦合组件1716所讨论的形式。虽然在图30中示出单个IC封装1720,但是多个IC封装可以耦合至***器1704;事实上,额外的***器可以耦合到***器1704。***器1704可以提供用于桥接电路板1702和IC封装1720的介于中间的衬底。IC封装1720可以是或者包括例如管芯(图28的管芯1502)、IC器件(例如,图29的IC器件1600)或者任何其它适当的组件。通常,***器1704可以将连接伸展到更宽的间距,或者将连接重新布线到不同的连接。例如,***器1704可以将IC封装1720(例如,管芯)耦合到耦合组件1716的一组球栅阵列(BGA)导电触点,用于耦合到电路板1702。在图30所示的实施例中,IC封装1720和电路板1702附接到***器1704的相对侧;在其它实施例中,IC封装1720和电路板1702可以附接到***器1704的同一侧。在一些实施例中,可以通过***器1704互连三个或更多个组件。
在一些实施例中,***器1704可以形成为PCB,包括通过电介质材料层彼此分离并且通过导电通孔互连的多个金属层。在一些实施例中,可以由环氧树脂、玻璃纤维增强的环氧树脂、具有无机填料的环氧树脂、陶瓷材料或者诸如聚酰亚胺的聚合物材料,来形成***器1704。在一些实施例中,可以由替代的刚性材料或柔性材料来形成***器1704,其中这些刚性材料或柔性材料可以包括上文所描述的用于在半导体衬底中使用的相同材料,诸如硅、锗以及其它III-V族和IV族材料。***器1704可以包括金属互连1708和通孔1710(包括但不限于TSV 1706)。***器1704还可以包括嵌入式器件1714,包括无源器件和有源器件两者。这样的器件可以包括但不限于:电容器、去耦电容器、电阻器、电感器、保险丝、二极管、变压器、传感器、静电放电(ESD)器件和存储器件。也可以在***器1704上形成诸如射频设备、功率放大器、功率管理器件、天线、阵列、传感器和微机电***(MEMS)器件的更复杂的设备。***器上封装结构1736可以采用在本领域中已知的***器上封装结构中的任何***器上封装结构的形式。
IC器件组件1700可以包括通过耦合组件1722耦合到电路板1702的第一面1740的IC封装1724。耦合组件1722可以采用上文参考耦合组件1716所讨论的实施例中的任何实施例的形式,以及IC封装1724可以采用上文参考IC封装1720所讨论的实施例中的任何实施例的形式。
在图30中所示的IC器件组件1700包括通过耦合组件1728耦合到电路板1702的第二面1742的层叠封装(package-on-package)结构1734。层叠封装结构1734可以包括通过耦合组件耦合在一起的IC封装1726和IC封装1732,使得IC封装1726安置在电路板1702与IC封装1732之间。耦合组件1728和1730可以采用上文所讨论的耦合组件1716的实施例中的任何实施例的形式,以及IC封装1726和1732可以采用上文所讨论的IC封装1720的实施例中的任何实施例的形式。层叠封装结构1734可以是根据在本领域中已知的层叠封装结构中的任何层叠封装结构来配置的。
图31是可以包括本文所公开的微电子组件100中的一个或多个微电子组件的示例性电子设备1800的方块图。例如,电子设备1800的组件中的任何适当的组件可以包括本文所公开的IC器件组件1700、IC器件1600或管芯1502中的一者或多者,并且可以布置在本文所公开的微电子组件100中的任何微电子组件中。在图31中示出如在电子设备1800中包括的许多组件,但是可以省略或重复这些组件中的任何一个或多组件,如可适用于应用的。在一些实施例中,在电子设备1800中包括的组件中的一些或全部组件可以附接到一个或多个母板。在一些实施例中,将这些组件中的一些或全部组件制造到单个片上***(SoC)管芯上。
此外,在各种实施例中,电子设备1800可以不包括在图31中所示的组件中的一个或多个组件,但是电子设备1800可以包括用于耦合到一个或多个组件的接口电路。例如,电子设备1800可以不包括显示设备1806,但是可以包括显示设备1806可以耦合到的显示设备接口电路(例如,连接器和驱动电路)。在另一组示例中,电子设备1800可以不包括音频输入设备1824或音频输出设备1808,但是可以包括音频输入设备1824或音频输出设备1808可以耦合到的音频输入或输出设备接口电路(例如,连接器和支持电路)。
电子设备1800可以包括处理设备1802(例如,一个或多个处理设备)。如本文所使用的,术语“处理设备”或“处理器”可以指的是处理来自寄存器和/或存储器的电子数据以将该电子数据转换成可以存储在寄存器和/或存储器中的其它电子数据的任何设备或设备的一部分。处理设备1802可以包括一个或多个数字信号处理器(DSP)、专用集成电路(ASIC)、中央处理单元(CPU)、图形处理单元(GPU)、密码处理器(在硬件内执行密码算法的专用处理器)、服务器处理器或者任何其它适当的处理设备。电子设备1800可以包括存储器1804,该存储器1804本身可以包括一个或多个存储器件,诸如易失性存储器(例如,动态随机存取存储器(DRAM))、非易失性存储器(例如,只读存储器(ROM))、闪存、固态存储器和/或硬盘驱动器。在一些实施例中,存储器1804可以包括与处理设备1802共享管芯的存储器。该存储器可以用作高速缓冲存储器,并且可以包括嵌入式动态随机存取存储器(eDRAM)或自旋转移矩磁随机存取存储器(STT-MRAM)。
在一些实施例中,电子设备1800可以包括通信芯片1812(例如,一个或多个通信芯片)。例如,通信芯片1812可以被配置用于管理用于对去往和来自电子设备1800的数据的传输的无线通信。术语“无线”及其派生词可以用于描述可以通过使用经过非固体介质的调制的电磁辐射来传送数据的电路、设备、***、方法、技术、通信通道等等。术语并不意味着关联的设备不包含任何电线,尽管在一些实施例中它们可能不是这样。
]通信芯片1812可以实现多种无线标准或协议中的任何一者,包括但不限于:包括Wi-Fi(IEEE 802.11系列)的电气和电子工程师协会(IEEE)标准、IEEE 802.16标准(例如IEEE 802.16-2005修正案)、长期演进(LTE)项目连同任何修改、更新和/或修订(例如,改进的LTE项目、超移动宽带(UMB)项目(还称为“3GPP2”)等等)。兼容IEEE 802.16的宽带无线接入(BWA)网络通常称为WiMAX网络,代表全球微波接入互操作的缩写词,其是针对通过IEEE802.16标准的一致性和互操作性测试的产品的认证标志。通信芯片1812可以根据全球移动通信***(GSM)、通用分组无线服务(GPRS)、通用移动电信***(UMTS)、高速分组接入(HSPA)、演进型HSPA(E-HSPA)或LTE网络进行操作。通信芯片1812可以根据GSM演进增强数据(EDGE)、GSM EDGE无线接入网(GERAN)、通用陆地无线接入网(UTRAN)或演进的UTRAN(E-UTRAN)进行操作。通信芯片1812可以根据码分多址(CDMA)、时分多址(TDMA)、数字增强型无绳电信(DECT)、演进数据优化(EV-DO)及其派生物、以及被指定为3G、4G、5G及更高版本的任何其它无线协议进行操作。在其它实施例中,通信芯片1812可以根据其它无线协议进行操作。电子设备1800可以包括天线1822,以促进无线通信和/或接收其它无线通信(诸如AM或FM无线电传输)。
在一些实施例中,通信芯片1812可以管理诸如电、光或者任何其它适当的通信协议(例如,以太网)的有线通信。如上所述,通信芯片1812可以包括多个通信芯片。例如,第一通信芯片1812可以专用于诸如Wi-Fi或蓝牙的较短程无线通信,以及第二通信芯片1812可以专用于诸如全球定位***(GPS)、EDGE、GPRS、CDMA、WiMAX、LTE、EV-DO或其它的较远程无线通信。在一些实施例中,第一通信芯片1812可以专用于无线通信,以及第二通信芯片1812可以专用于有线通信。
电子设备1800可以包括电池/功率电路1814。电池/功率电路1814可以包括一个或多个能量存储设备(例如,电池或电容器)和/或用于将电子设备1800的组件耦合到与电子设备1800分离的能量源(例如,AC线路功率)的电路。
电子设备1800可以包括显示设备1806(或者如上所述的对应的接口电路)。显示设备1806可以包括任何视觉指示器,诸如平视(heads-up)显示器、计算机监视器、投影仪、触摸屏显示器、液晶显示器(LCD)、发光二极管显示器或平板显示器。
电子设备1800可以包括音频输出设备1808(或者如上所述的对应的接口电路)。音频输出设备1808可以包括产生可听指示器的任何设备(诸如扬声器、耳机或耳塞)。
电子设备1800可以包括音频输入设备1824(或者如上所述的对应的接口电路)。音频输入设备1824可以包括产生代表声音的信号的任何设备,诸如麦克风、麦克风阵列或数字式仪器(例如,具有乐器数字接口(MIDI)输出的仪器)。
电子设备1800可以包括GPS设备1818(或者如上所述的对应的接口电路)。GPS设备1818可以与基于卫星的***相通信,并且可以接收电子设备1800的位置,如在本领域中已知的。
电子设备1800可以包括其它输出设备1810(或者如上所述的对应的接口电路)。其它输出设备1810的示例可以包括音频编解码器、视频编解码器、打印机、用于向其它设备提供信息的有线或无线发送机、或者额外的存储设备。
电子设备1800可以包括其它输入设备1820(或者如上所述的对应的接口电路)。其它输入设备1820的示例可以包括加速度计、陀螺仪、指南针、图像捕获设备、键盘、诸如鼠标的光标控制设备、触控笔、触摸板、条形码读取器、快速响应(QR)码读取器、任何传感器或者射频识别(RFID)读取器。
电子设备1800可以具有任何期望的形状因子,诸如手持式或移动电子设备(例如,蜂窝电话、智能电话、移动互联网设备、音乐播放器、平板计算机、膝上型计算机、上网本计算机、超极本计算机、个人数字助理(PDA)、超移动个人计算机等等)、台式电子设备、服务器或其它网络计算组件、打印机、扫描仪、监视器、机顶盒、娱乐控制单元、车辆控制单元、数码照相机、数字视频记录器或者可穿戴电子设备。在一些实施例中,电子设备1800可以是处理数据的任何其它电子设备。
以下段落提供了本文公开的实施例的各种示例。
示例1是一种制造微电子组件的方法,包括:形成封装衬底的一部分;在所述封装衬底的所述部分上形成多个导电柱,其中所述导电柱是围绕在其中不存在导电柱的区域来布置的,并且所述区域包括导电触点;以及在管芯与所述封装衬底的所述部分之间形成互连,其中所述管芯具有第一表面和相对的第二表面,所述管芯包括在其第一表面处的第一导电触点和在其第二表面处的第二导电触点,并且所述互连将所述封装衬底的所述部分的所述导电触点与所述管芯的所述第一导电触点耦合。
示例2可以包括示例1的主题,并且还可以包括:在形成所述互连之后,在所述导电柱和所述管芯周围提供模制材料。
示例3可以包括示例1-2中的任何一项的主题,并且还可以指定单个导电柱具有在1:1与4:1之间的高宽比。
示例4可以包括示例1-3中的任何一项的主题,并且还可以指定单个导电柱具有在10微米与100微米之间的直径。
示例5可以包括示例1-4中的任何一项的主题,并且还可以指定单个导电柱具有在50微米与250微米之间的直径。
示例6可以包括示例1-5中的任何一项的主题,并且还可以指定所述封装衬底的所述部分是第一部分,所述互连是第一互连,并且所述方法还包括:形成所述封装衬底的接近所述管芯的所述第二表面的第二部分,其中形成所述封装衬底的所述第二部分包括:在所述管芯与所述封装衬底的所述第二部分之间形成所述第二互连,并且所述第二互连是在所述管芯的所述第二导电触点与所述封装衬底的所述第二部分的第二导电触点之间形成的。
示例7可以包括示例6的主题,并且还可以指定所述第二互连是金属到金属互连。
示例8可以包括示例6的主题,并且还可以指定所述第二互连是电镀互连。
示例9可以包括示例6-8中的任何一项的主题,并且还可以指定所述管芯是第一管芯,并且所述方法还包括:在所述封装衬底的所述第二部分与第二管芯之间形成第三互连。
示例10可以包括示例6-9中的任何一项的主题,并且还可以指定所述封装衬底的所述第二部分包括在所述第二管芯与所述第一管芯的所述第二导电触点之间的导电通路。
示例11可以包括示例1-10中的任何一项的主题,并且还可以指定所述互连包括焊料。
示例12可以包括示例1-11中的任何一项的主题,并且还可以指定所述互连包括各向异性导电材料。
示例13可以包括示例1-12中的任何一项的主题,并且还可以包括:在形成所述互连之前,在所述封装衬底的围绕所述区域的所述部分上形成放置环,其中形成所述互连包括:将所述管芯是至少部分地放置在所述放置环中。
示例14可以包括示例1-13中的任何一项的主题,并且还可以指定所述管芯是第一管芯,并且所述方法还包括:在所述封装衬底的所述部分与第二管芯之间形成第二互连。
示例15可以包括示例14的主题,并且还可以包括:在所述第二管芯与所述第一管芯之间形成第三互连,其中所述第三互连耦合所述第二管芯和所述第一管芯的所述第二导电触点。
示例16可以包括示例1-15中的任何一项的主题,并且还可以指定所述封装衬底的所述部分是第一部分,并且所述方法还包括:将所述封装衬底的所述第一部分耦合到所述封装衬底的第二部分。
示例17是一种制造微电子组件的方法,包括:在载体上形成多个导电柱,其中所述导电柱是围绕在其中没有导电柱的区域来布置的;将管芯放置在所述区域中,其中所述管芯具有第一表面和相对的第二表面,所述第一表面是在所述载体与所述第二表面之间的,并且所述管芯包括在其第一表面处的第一导电触点和在其第二表面处的第二导电触点;以及在将所述管芯放置在所述区域中之后,形成封装衬底的接近所述第二表面的一部分;其中形成所述封装衬底的所述部分包括在所述管芯与所述封装衬底的所述部分之间形成互连,并且所述互连将所述封装衬底的所述部分的导电触点与所述管芯的所述第二导电触点耦合。
示例18可以包括示例17的主题,并且还可以包括:在将所述管芯放置在所述区域中之后,在所述导电柱和所述管芯周围提供模制材料。
示例19可以包括示例17-18中的任何一项的主题,并且还可以指定单个导电柱具有在1:1与4:1之间的高宽比。
示例20可以包括示例17-19中的任何一项的主题,并且还可以指定单个导电柱具有在30微米与300微米之间的直径。
示例21可以包括示例17-20中的任何一项的主题,并且还可以指定单个导电柱具有在50微米与400微米之间的直径。
示例22可以包括示例17-21中的任何一项的主题,并且还可以包括在所述载体上围绕所述区域形成放置环;其中所述管芯是至少部分地放置在所述放置环中。
示例23可以包括示例17-22中的任何一项的主题,并且还可以指定所述封装衬底的所述部分是第一部分,所述互连是第一互连,并且所述方法还包括:去除所述载体;以及形成所述封装衬底的接近所述管芯的所述第一表面的第二部分,其中形成所述封装衬底的所述第二部分包括在所述管芯与所述封装衬底的所述第二部分之间形成第二互连,并且所述第二互连是在所述管芯的所述第一导电触点与所述封装衬底的所述第二部分的第二导电触点之间形成的。
示例24可以包括示例23的主题,并且还可以指定所述第二互连是金属到金属互连。
示例25可以包括示例23的主题,并且还可以指定所述第二互连是电镀互连。
示例26可以包括示例23-25中的任何一项的主题,并且还可以指定所述管芯是第一管芯,并且所述方法还包括:在所述封装衬底的所述第二部分与第二管芯之间形成第三互连。
示例27可以包括示例26的主题,并且还可以指定所述第三互连包括焊料。
示例28可以包括示例17-27中的任何一项的主题,并且还可以指定所述管芯是第一管芯,并且所述方法还包括:在所述封装衬底的所述部分与第二管芯之间形成第二互连。
示例29可以包括示例28的主题,并且还可以包括:在所述第二管芯与所述第一管芯之间形成第三互连,其中所述第三互连耦合所述第二管芯和所述第一管芯的所述第二导电触点。
示例30可以包括示例17-29中的任何一项的主题,并且还可以指定所述第二互连是金属到金属互连。
示例31可以包括示例17-29中的任何一项的主题,并且还可以指定所述互连是电镀互连。
示例32可以包括示例17-31中的任何一项的主题,并且还可以指定所述封装衬底的所述部分是第一部分,以及所述方法还包括:将所述封装衬底的所述第一部分耦合到所述封装衬底的第二部分。
示例33是一种制造微电子组件的方法,包括:形成封装衬底的一部分,其中所述封装衬底具有凹槽,所述凹槽具有在所述凹槽的底部的导电触点;在管芯与所述封装衬底的所述部分之间形成第一互连,其中所述管芯具有第一表面和相对的第二表面,所述管芯包括在其第一表面处的第一导电触点和在其第二表面处的第二导电触点,所述管芯的所述第一表面在所述封装衬底的所述部分与所述管芯的所述第二表面之间,并且所述第一互连是在所述管芯的所述第一导电触点与所述封装衬底的所述导电触点之间形成的;以及形成所述封装衬底的接近所述管芯的所述第二表面的第二部分,其中形成所述封装衬底的所述第二部分包括在所述管芯与所述封装衬底的所述第二部分之间形成第二互连,并且所述第二互连是在所述管芯的所述第二导电触点与所述封装衬底的所述第二部分的导电触点之间形成的。
示例34可以包括示例33的主题,并且还可以指定所述第一互连包括焊料。
示例35可以包括示例33-34中的任何一项的主题,并且还可以指定所述第一互连包括各向异性导电材料。
示例36可以包括示例33-35中的任何一项的主题,并且还可以指定所述第二互连不包括焊料。
示例37可以包括示例33-36中的任何一项的主题,并且还可以指定所述第二互连是金属到金属互连。
示例38可以包括示例33-36中的任何一项的主题,并且还可以指定所述第二互连是电镀互连。
示例39可以包括示例33-38中的任何一项的主题,并且还可以指定所述管芯是第一管芯,并且所述方法还包括:在第二管芯与所述封装衬底的所述第二部分之间形成第三互连。
示例40可以包括示例39的主题,并且还可以指定所述封装衬底的所述第二部分包括在所述第二管芯与所述第一管芯的所述第二导电触点之间的至少一个导电通路。
示例41可以包括示例39-40中的任何一项的主题,并且还可以指定所述第三互连包括焊料。
Claims (25)
1.一种制造微电子组件的方法,包括:
形成封装衬底的一部分;
在所述封装衬底的所述部分上形成多个导电柱,其中,所述导电柱是围绕在其中不存在导电柱的区域来布置的,并且所述区域包括导电触点;以及
在管芯与所述封装衬底的所述部分之间形成互连,其中,所述管芯具有第一表面和相对的第二表面,所述管芯包括在其第一表面处的第一导电触点和在其第二表面处的第二导电触点,并且所述互连将所述封装衬底的所述部分的所述导电触点与所述管芯的所述第一导电触点耦合。
2.根据权利要求1所述的方法,还包括:
在形成所述互连之后,在所述导电柱和所述管芯周围提供模制材料。
3.根据权利要求1所述的方法,其中,所述互连包括焊料。
4.根据权利要求1所述的方法,其中,所述互连包括各向异性导电材料。
5.根据权利要求1所述的方法,还包括:
在形成所述互连之前,在所述封装衬底的围绕所述区域的所述部分上形成放置环;
其中,形成所述互连包括:将所述管芯至少部分地放置在所述放置环中。
6.根据权利要求1-5中的任何一项所述的方法,其中,所述管芯是第一管芯,并且所述方法还包括:
在所述封装衬底的所述部分与第二管芯之间形成第二互连。
7.根据权利要求6所述的方法,还包括:
在所述第二管芯与所述第一管芯之间形成第三互连,其中,所述第三互连耦合所述第二管芯和所述第一管芯的所述第二导电触点。
8.根据权利要求1-5中的任何一项所述的方法,其中,所述封装衬底的所述部分是第一部分,并且所述方法还包括:
将所述封装衬底的所述第一部分耦合到所述封装衬底的第二部分。
9.一种制造微电子组件的方法,包括:
在载体上形成多个导电柱,其中,所述导电柱是围绕在其中没有导电柱的区域来布置的;
将管芯放置在所述区域中,其中,所述管芯具有第一表面和相对的第二表面,所述第一表面在所述载体与所述第二表面之间,并且所述管芯包括在其第一表面处的第一导电触点和在其第二表面处的第二导电触点;以及
在将所述管芯放置在所述区域中之后,形成封装衬底的接近所述第二表面的一部分;
其中,形成所述封装衬底的所述部分包括在所述管芯与所述封装衬底的所述部分之间形成互连,并且所述互连将所述封装衬底的所述部分的导电触点与所述管芯的所述第二导电触点耦合。
10.根据权利要求9所述的方法,还包括:
在将所述管芯放置在所述区域中之后,在所述导电柱和所述管芯周围提供模制材料。
11.根据权利要求9所述的方法,其中,单个导电柱具有在1:1与4:1之间的高宽比。
12.根据权利要求9所述的方法,其中,单个导电柱具有在30微米与300微米之间的直径。
13.根据权利要求9所述的方法,其中,单个导电柱具有在50微米与400微米之间的直径。
14.根据权利要求9-13中的任何一项所述的方法,其中,所述封装衬底的所述部分是第一部分,所述互连是第一互连,并且所述方法还包括:
去除所述载体;以及
形成所述封装衬底的接近所述管芯的所述第一表面的第二部分,其中,形成所述封装衬底的所述第二部分包括:在所述管芯与所述封装衬底的所述第二部分之间形成第二互连,以及所述第二互连是在所述管芯的所述第一导电触点与所述封装衬底的所述第二部分的第二导电触点之间形成的。
15.根据权利要求14所述的方法,其中,所述第二互连是金属到金属互连。
16.根据权利要求14所述的方法,其中,所述第二互连是电镀互连。
17.根据权利要求14所述的方法,其中,所述管芯是第一管芯,并且所述方法还包括:
在所述封装衬底的所述第二部分与第二管芯之间形成第三互连。
18.根据权利要求17所述的方法,其中,所述第三互连包括焊料。
19.一种制造微电子组件的方法,包括:
形成封装衬底的一部分,其中,所述封装衬底具有凹槽,所述凹槽具有在所述凹槽的底部的导电触点;
在管芯与所述封装衬底的所述部分之间形成第一互连,其中,所述管芯具有第一表面和相对的第二表面,所述管芯包括在其第一表面处的第一导电触点和在其第二表面处的第二导电触点,所述管芯的所述第一表面在所述封装衬底的所述部分与所述管芯的所述第二表面之间,并且所述第一互连是在所述管芯的所述第一导电触点与所述封装衬底的所述导电触点之间形成的;以及
形成所述封装衬底的接近所述管芯的所述第二表面的第二部分,其中,形成所述封装衬底的所述第二部分包括在所述管芯与所述封装衬底的所述第二部分之间形成第二互连,并且所述第二互连是在所述管芯的所述第二导电触点与所述封装衬底的所述第二部分的导电触点之间形成的。
20.根据权利要求19所述的方法,其中,所述第一互连包括焊料。
21.根据权利要求19所述的方法,其中,所述第一互连包括各向异性导电材料。
22.根据权利要求19所述的方法,其中,所述第二互连是金属到金属互连。
23.根据权利要求19所述的方法,其中,所述第二互连是电镀互连。
24.根据权利要求19-23中的任何一项所述的方法,其中,所述管芯是第一管芯,并且所述方法还包括:
在第二管芯与所述封装衬底的所述第二部分之间形成第三互连。
25.根据权利要求24所述的方法,其中,所述封装衬底的所述第二部分包括在所述第二管芯与所述第一管芯的所述第二导电触点之间的至少一个导电通路。
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US20220223561A1 (en) | 2022-07-14 |
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