CN111145816B - Circuit structure for programming - Google Patents

Circuit structure for programming Download PDF

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Publication number
CN111145816B
CN111145816B CN201911411387.9A CN201911411387A CN111145816B CN 111145816 B CN111145816 B CN 111145816B CN 201911411387 A CN201911411387 A CN 201911411387A CN 111145816 B CN111145816 B CN 111145816B
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unit
programming
read
data
nmos tube
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CN111145816A (en
Inventor
李天文
刘鸿瑾
张绍林
史立轺
贺冬云
张海
张智京
李瑞梅
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Beijing Sunwise Space Technology Ltd
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Beijing Sunwise Space Technology Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/22—Safety or protection circuits preventing unauthorised or accidental access to memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits

Abstract

The application belongs to the technical field of integrated circuit design, and relates to a circuit structure for programming, which comprises: a storage unit configured to hold data; an isolation unit configured to isolate the storage unit and switch an on-off state according to a control signal; a bit line control unit configured to select an order of bit line outputs according to a control signal; and a read/write control unit configured to read/write data of the memory cell according to a level signal of the bit line control unit. The circuit structure can realize multiple modes of a programming structure through the isolation unit according to the switching of the control signals, so that data can be read and written for many times, permanent storage of the data can also be realized, the data is not lost when power failure occurs, a user can read the data by opening the word line, and meanwhile, the user can select whether the data is permanently written in, so that the use flexibility of the user is improved, and the manufacturing cost is reduced by adopting a commercial process.

Description

Circuit structure for programming
Technical Field
The present application relates to the field of integrated circuit design, and, for example, to a circuit structure for programming.
Background
Static Random-Access Memory (SRAM), which is a type of Random Access Memory, can read and write stored data, however, when power supply is stopped, the data stored in the SRAM disappears. A Read-Only Memory (ROM) is a solid-state semiconductor Memory which can Only Read out data stored in advance, cannot modify and update data, has Only one-time programming opportunity, and cannot change the content of data once the data is programmed. Therefore, how to modify and update the stored data can be realized, the data can be permanently written according to the requirements of users, and the problem that the data is not lost when the power is down is urgently needed to be solved.
Disclosure of Invention
The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview nor is intended to identify key/critical elements or to delineate the scope of such embodiments but rather as a prelude to the more detailed description that is presented later.
The embodiment of the disclosure provides a circuit structure for programming, so as to solve the technical problems that a storage structure mode in the prior art is single, data can not be read and written, and data can not be permanently stored.
In some embodiments, the circuit structure for programming includes:
a storage unit configured to hold data;
an isolation unit configured to isolate the storage unit and switch an on-off state according to a control signal;
a bit line control unit configured to select an order of bit line outputs according to a control signal;
and a read/write control unit configured to read/write data of the memory cell according to a level signal of the bit line control unit.
The circuit structure for programming provided by the embodiment of the disclosure can achieve the following technical effects: the isolation unit can realize multiple modes of a programming structure according to the switching of the control signals, so that data can be read and written for many times, permanent storage of the data can be realized, the data is not lost when power failure occurs, a user can read the data by opening the word line, and meanwhile, the user can select whether the data is permanently written, so that the use flexibility of the user is improved, and the manufacturing cost is reduced by adopting a commercial process.
The foregoing general description and the following description are exemplary and explanatory only and are not restrictive of the application.
Drawings
One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the accompanying drawings and not in limitation thereof, in which elements having the same reference numeral designations are shown as like elements and not in limitation thereof, and wherein:
FIG. 1 is a schematic diagram of a circuit structure for programming according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of another circuit structure for programming provided by the embodiments of the present disclosure;
fig. 3 is a schematic circuit diagram for programming according to an embodiment of the present disclosure.
Detailed Description
So that the manner in which the features and elements of the disclosed embodiments can be understood in detail, a more particular description of the disclosed embodiments, briefly summarized above, may be had by reference to the embodiments, some of which are illustrated in the appended drawings. In the following description of the technology, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may be practiced without these details. In other instances, well-known structures and devices may be shown in simplified form in order to simplify the drawing.
The terms "first," "second," and the like in the description and in the claims, and the above-described drawings of embodiments of the present disclosure, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It should be understood that the data so used may be interchanged under appropriate circumstances such that embodiments of the present disclosure described herein may be made. Furthermore, the terms "comprising" and "having," as well as any variations thereof, are intended to cover non-exclusive inclusions.
The term "plurality" means two or more unless otherwise specified.
In the embodiment of the present disclosure, the character "/" indicates that the preceding and following objects are in an or relationship. For example, A/B represents: a or B.
The term "and/or" is an associative relationship that describes objects, meaning that three relationships may exist. For example, a and/or B, represents: a or B, or A and B.
As shown in fig. 1, an embodiment of the present disclosure provides a circuit structure for programming, including:
a storage unit 1 configured to hold data;
an isolation unit 2 configured to isolate the storage unit 1, switching an on-off state according to a control signal;
a bit line control unit 3 configured to select an order of bit line outputs according to a control signal;
and a read/write control unit 4 configured to read/write data of the memory cell according to the level signal of the bit line control unit 3.
By adopting the circuit structure for programming provided by the embodiment of the disclosure, various modes of the programming structure can be realized through the isolation unit according to the switching of the control signal, so that the repeated reading and writing of data can be realized, the permanent storage of the data can also be realized, and a user can also read the data.
Optionally, the memory cell includes a pair of cross-coupled inverters coupled to the storage node.
Optionally, the isolation unit is configured to isolate the memory cell into a cross-coupled cell and a programmed cell.
Optionally, the isolation unit isolates the storage node from the cross-coupling unit while isolating the storage node from the programming unit.
Optionally, an isolation unit isolating the storage nodes n1, n2 from the cross-coupled cells, while isolating the storage nodes n1, n2 from the drains of the programmed cells;
optionally, the isolation unit comprises a first isolation unit and a second isolation unit;
a first isolation unit configured to isolate the storage node from the cross-coupling unit; and/or the presence of a gas in the gas,
a second isolation unit configured to isolate the storage node from the program unit.
Optionally, the first isolation unit and the second isolation unit are configured to: when the first isolation unit and the second isolation unit are conducted, data are stored through the programming unit and/or the cross coupling unit.
Optionally, the first isolation unit and the second isolation unit are configured to: and reading the stored data from the programming unit when the first isolation unit and the second isolation unit are cut off.
Optionally, the first isolation unit includes a third PMOS transistor MP3 and a fourth PMOS transistor MP 4;
the source electrode of the third PMOS tube is connected with the drain electrode of the first PMOS tube of the cross coupling unit and the grid electrode of the second PMOS tube of the cross coupling unit;
the drain electrode of the third PMOS tube is connected with the source electrode of a fifth NMOS tube of the read-write control unit, the grid electrode of a second NMOS tube of the programming unit and the drain electrode of a third NMOS tube of the second isolation unit;
the grid electrode of the third PMOS tube is connected with the grid electrode of the fourth PMOS tube and is connected with the control signal;
the source electrode of the fourth PMOS tube is connected with the drain electrode of the second PMOS tube of the cross coupling unit and the grid electrode of the first PMOS tube of the cross coupling unit;
the drain electrode of the fourth PMOS tube is connected with the source electrode of the sixth NMOS tube of the read-write control unit, the grid electrode of the first NMOS tube of the programming unit and the drain electrode of the fourth NMOS tube of the second isolation unit.
Optionally, the second isolation unit comprises: a third NMOS transistor MN3 and a fourth NMOS transistor MN 4;
the source electrode of the third NMOS tube is connected with the drain electrode of the first NMOS tube of the programming unit;
the drain electrode of the third NMOS tube is connected with the drain electrode of the third PMOS tube of the first isolation unit, the source electrode of the fifth NMOS tube of the read-write control unit and the grid electrode of the second NMOS tube of the programming unit;
the grid electrode of the third NMOS tube is connected with the grid electrode of the fourth NMOS tube and is connected with a control signal;
the source electrode of the fourth NMOS tube is connected with the drain electrode of the second NMOS tube of the programming unit;
the drain electrode of the fourth NMOS tube is connected with the drain electrode of the fourth PMOS tube of the first isolation unit, the source electrode of the sixth NMOS tube of the read-write control unit and the grid electrode of the first NMOS tube of the programming unit.
Optionally, the cross-coupling unit may be a PMOS pair transistor or an NMOS pair transistor, a source of the PMOS pair transistor is connected to the power supply, and a drain of the PMOS pair transistor is connected to the first isolation unit; if the NMOS pair transistor is adopted, the source electrode of the NMOS pair transistor is connected with the ground, and the drain electrode of the NMOS pair transistor is connected with the second isolation unit.
Alternatively, the read/write control unit realizes the read/write function of the memory cell by controlling the gate of the read/write MOS and the level of the bit line BL0/NBL 0.
Optionally, the read-write control unit includes: and the grid electrode of the NMOS (N-Metal-Oxide-Semiconductor) transistor is connected with the bit line, and the data of the memory unit is read and written by controlling the level of the grid electrode of the read/write NMOS transistor and the bit line.
Optionally, the programming unit, in order to program the programming unit, an MOS Transistor (Metal-Oxide-Semiconductor Field Effect Transistor) of the programming unit has a thinner gate than other units, and may be a pmos (positive Channel Metal Oxide Semiconductor) pair Transistor or an NMOS pair Transistor, if the MOS Transistor is an NMOS pair Transistor, a source thereof is connected to ground, a drain thereof is connected to the second isolation unit, and a gate thereof is connected to a source of the read/write Transistor; the source electrodes of the PMOS pair transistors are connected with a power supply, the drain electrodes are connected with the first isolation unit indirectly, and the grid electrodes are connected with the source electrodes of the read-write transistors.
Optionally, when the cross-coupling unit is a PMOS pair transistor, the programming unit is an NMOS pair transistor; or the like, or, alternatively,
when the cross-coupling unit is an NMOS pair transistor, the programming unit is a PMOS pair transistor.
Optionally, the breakdown voltages of the cross-coupling unit, the isolation unit, the read-write control unit, and the bit line control unit are all greater than the breakdown voltage of the programming unit.
Alternatively, the bit line control unit selects the order of the bit line outputs according to the operation mode of the programming structure, and outputs BL1 equal to NBL0 and NBL1 equal to BL0 when the control signal ctrn is low; the output BL1 is equal to BL0 and NBL1 is equal to NBL0 when the control signal ctrn is high.
As shown in connection with fig. 2, in some embodiments, a circuit structure for programming includes: a cross coupling unit 5, a first isolation unit 6, a second isolation unit 7, a programming unit 8, a read-write control unit 4 and a bit line control unit 3. The cross-coupling unit is used for data retention when the programming structure works in a random access mode, the first isolation unit is used for isolating the node n5 from the storage node n1 and isolating the node n6 from the storage node n2, the first isolation unit is turned on when the programming structure works in the random access mode and the programming mode, and the first isolation unit is turned off when the programming structure works in a read-only memory mode. The second isolation unit is used for isolating the node n3 from the storage node n1, and isolating the node n4 from the storage node n2, and is turned on when the programming structure works in the random access mode and the programming mode, and is turned off when the programming structure works in the read only memory mode. When the programming unit works in the random storage mode, the data retention is realized together with the cross coupling unit, when the programming unit works in the programming mode, the storage unit information is stored through the programming unit, and when the programming unit works in the read-only memory mode, the storage information is read from the programming unit. And the read-write control unit realizes the read/write function of the memory cell by controlling the grid of the read/write MOS and the level of the bit line BL0/NBL 0. The bit line control unit selects an order of bit line outputs according to an operation mode of the program structure.
The cross-coupling unit includes: a first PMOS transistor MP1 and a second PMOS transistor MP 2; the first isolation unit includes: a third PMOS transistor MP3 and a fourth PMOS transistor MP 4; the read-write control unit includes: a fifth NMOS transistor MN5 and a sixth NMOS transistor MN 6; the second isolation unit includes: a third NMOS transistor MN3, a fourth NMOS transistor MN 4; the programming unit includes: a first NMOS transistor MN1, a second NMOS transistor MN 2.
Specifically, the source of the first PMOS transistor MP1 is connected to the power supply vdd, the drain of the first PMOS transistor MP1 is connected to the source of the third PMOS transistor MP3 and the gate of the second PMOS transistor MP2, the source of the second PMOS transistor MP2 is connected to the power supply vdd, and the drain of the first PMOS transistor MP2 is connected to the source of the fourth PMOS transistor MN4 and the gate of the first PMOS transistor MP 1.
The grid electrode of the third PMOS tube MP3 is connected with the grid electrode of the fourth PMOS tube MP4 and connected with the control signal ctrp, and the drain electrode of MP3 is connected with the source electrode of the fifth NMOS tube MN5, the grid electrode of the second NMOS tube MP2 and the drain electrode of the third NMOS tube MN 3; the drain of the fourth PMOS transistor MP4 is connected to the source of the sixth NMOS transistor MN6, the gate of the first NMOS transistor MN1 and the drain of the fourth NMOS transistor MN 4.
The grid electrode of the third NMOS tube MN3 is connected with the grid electrode of the fourth NMOS tube and connected with the control signal ctrn, the source electrode of the MN3 is connected with the drain electrode of the first NMOS tube MN1, and the source electrode of the fourth NMOS tube MN4 is connected with the drain electrode of the second NMOS tube MN 2;
the drain of the fifth NMOS transistor MN5 is connected to the gate of the bit line BL0, MN5 and the drain of the sixth NMOS transistor MN6 is connected to the gate of the bit line NBL0, MN 6.
Optionally, the programming structure provided in this embodiment includes a cross-coupling unit, a first isolation unit, a second isolation unit, a programming unit, a read/write control unit, and a bit line control unit. Compared with a PROM (Programmable Read-Only Memory), the scheme can work the programming structure in a random storage mode before a user does not determine data, can write the data into the unit permanently after determining the data through programming, and works in a ROM (Read-Only Memory) mode when the programming structure is used again.
In this embodiment, when the circuit structure for programming provided in the embodiment of the present disclosure operates in the random access mode, the operating power supply voltage is the core voltage of the chip, the control signal ctrp is connected to the low level, and the control signal ctrn is connected to the high level, so that the first isolation unit and the second isolation unit are always kept on, and at this time, the external world performs read/write operations on the structure through BL1, NBL1 and the read/write control unit. When the structure works in a programming mode, a user writes data into the structure, the control signal ctrp is connected to the low level, the control signal ctrn is connected to the core voltage, the word line signal WL is connected to the low level, the programming process is that the power voltage of the structure is increased, the levels of the control signal and the word line signal are kept unchanged, and if the stored data '1' (the level of the node n1 is high, and the level of the node n2 is low), the voltage of the node n1 is gradually increased along with the increase of the power voltage, and the levels of the nodes n2, n4 and n6 are kept low. The voltage at node n3 does not rise with the voltage at node n1, but instead remains at Vctrn-Vth, where Vctrn represents the voltage of the control signal ctrn and Vth represents the threshold voltage of MN 3. When the voltage of the node n1 exceeds the breakdown voltage threshold of MN2, breakdown is formed, a low-resistance path is formed between the node n1 and the ground, programming is realized, and due to the fact that a programming unit adopts a thin-gate device and other units all adopt thick-gate devices, when the programming unit breaks down, other units cannot break down. When the programming structure works in the ROM mode, the power supply voltage is connected with the core voltage, the control signal ctrp of the first isolation unit is connected with a high level, the control signal ctrn of the second isolation unit is connected with a low level, the BL1 is connected with the NBL0, the NBL1 is connected with the BL0, a user precharges the BL0 and the NBL0 to a high level before reading data, the BL0 voltage becomes low due to the existence of a low-resistance-to-ground path in n1, the NBL0 does not exist in a low-resistance-to-ground path, and the high level is maintained, so the signal NBL1 becomes low, and the ROM data reading operation is completed.
The circuit structure for programming provided by the embodiment of the disclosure can realize three working modes, wherein one mode is a random storage unit mode and can be read and written like an SRAM unit; one is a programming mode, permanently writing data to the programming cells; the other mode is a ROM mode, which operates similarly to a ROM and is a read-only memory. The structure combines the characteristics of SRAM and ROM, can be used as a random access memory and a read only memory, and the traditional PROM structure has only one-time programming opportunity, and once the data content is programmed, the data content can not be changed. The circuit structure for programming provided by the embodiment of the disclosure can enable a user to work in a random storage mode firstly, and can modify and update stored data and lose power. The data can be programmed after being completely determined, after the programming operation is completed, the data is not lost when power is off and is permanently stored, and the data cannot be modified again when being used as a ROM mode by a user. In addition, the embodiment can adopt a commercial process, the manufacturing cost is reduced, and meanwhile, the storage unit has the characteristics of high reading/writing speed and small quiescent current.
Fig. 3 is a schematic diagram of another circuit structure for programming. Compared with the circuit structure shown in fig. 2, on the basis of the circuit structure shown in fig. 2, the thick-gate PMOS-to-transistor cross-coupling unit is replaced by the thin-gate PMOS-to-transistor programming unit, and the thin-gate NMOS-to-transistor is replaced by the NMOS cross-coupling unit and part of the connecting lines are adjusted.
When the circuit structure for programming provided by the embodiment of the disclosure works in a random storage mode, the circuit structure is consistent with a common SRAM read-write function, and can realize data read-write for many times. The programming architecture can be switched to a read only memory mode, and the user can read data by turning on the word line. And when the programming structure works in a random storage mode, the programming structure is basically consistent with the read/write speed of the common storage unit, and a user can select whether to permanently write data or not, so that the use flexibility of the user is improved.
So far, two embodiments of the present application have been described in detail with reference to the accompanying drawings. From the above description, those skilled in the art should clearly recognize the programming structure of the present solution.
Further, the above definitions of the various elements and methods are not limited to the various specific structures, shapes or arrangements of parts mentioned in the examples, which may be easily modified or substituted by those of ordinary skill in the art.
In summary, the random access memory cell and the read only memory cell are integrated in one circuit structure through a circuit design technology, a commercial process is adopted, the manufacturing cost is reduced, and meanwhile, the read/write speed of the memory cell is high, and the static current is small.
The above description and drawings sufficiently illustrate embodiments of the disclosure to enable those skilled in the art to practice them. Other embodiments may include structural and other changes. The examples merely typify possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in or substituted for those of others. The embodiments of the present disclosure are not limited to the structures that have been described above and shown in the drawings, and various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims (6)

1. A circuit structure for programming, comprising:
a storage unit configured to hold data;
an isolation unit configured to isolate the storage unit and switch an on-off state according to a control signal;
a bit line control unit configured to select an order of bit line outputs according to a control signal;
a read/write control unit configured to read/write data of the memory cell according to a level signal of the bit line control unit;
the storage cell includes a pair of cross-coupled inverters coupled to a storage node;
the isolation unit is configured to isolate the memory cell into a cross-coupled cell and a programming cell; the isolation unit includes: a first isolation unit configured to isolate a storage node from the cross-coupling unit; a second isolation unit configured to isolate the storage node from the program unit; the first isolation unit and the second isolation unit are configured to: and reading the stored data from the programming unit when the first isolation unit and the second isolation unit are cut off.
2. The circuit structure of claim 1, wherein the first isolation unit and the second isolation unit are configured to:
and when the first isolation unit and the second isolation unit are conducted, data are stored through the programming unit and/or the cross coupling unit.
3. The circuit structure according to any one of claims 1 to 2, wherein the first isolation unit comprises a third PMOS transistor MP3 and a fourth PMOS transistor MP 4;
the source electrode of the third PMOS tube is connected with the drain electrode of the first PMOS tube of the cross coupling unit and the grid electrode of the second PMOS tube of the cross coupling unit;
the drain electrode of the third PMOS tube is connected with the source electrode of a fifth NMOS tube of the read-write control unit, the grid electrode of a second NMOS tube of the programming unit and the drain electrode of a third NMOS tube of the second isolation unit;
the grid electrode of the third PMOS tube is connected with the grid electrode of the fourth PMOS tube and is connected with a control signal;
the source electrode of the fourth PMOS tube is connected with the drain electrode of the second PMOS tube of the cross coupling unit and the grid electrode of the first PMOS tube of the cross coupling unit;
and the drain electrode of the fourth PMOS tube is connected with the source electrode of a sixth NMOS tube of the read-write control unit, the grid electrode of the first NMOS tube of the programming unit and the drain electrode of the fourth NMOS tube of the second isolation unit.
4. The circuit structure according to any one of claims 1 to 2, wherein the second isolation unit comprises: a third NMOS transistor MN3 and a fourth NMOS transistor MN 4;
the source electrode of the third NMOS tube is connected with the drain electrode of the first NMOS tube of the programming unit;
the drain electrode of the third NMOS tube is connected with the drain electrode of the third PMOS tube of the first isolation unit, the source electrode of the fifth NMOS tube of the read-write control unit and the gate electrode of the second NMOS tube of the programming unit;
the grid electrode of the third NMOS tube is connected with the grid electrode of the fourth NMOS tube and is connected with a control signal;
the source electrode of the fourth NMOS tube is connected with the drain electrode of the second NMOS tube of the programming unit;
and the drain electrode of the fourth NMOS tube is connected with the drain electrode of the fourth PMOS tube of the first isolation unit, the source electrode of the sixth NMOS tube of the read-write control unit and the grid electrode of the first NMOS tube of the programming unit.
5. The circuit structure of claim 1, wherein the read-write control unit comprises:
and the grid electrode of the NMOS transistor is connected with the bit line, and the data of the storage unit is read and written by controlling the level of the grid electrode of the NMOS transistor and the level of the bit line.
6. The circuit structure of any one of claims 1 to 5, wherein the breakdown voltages of the cross-coupling unit, the isolation unit, the read/write control unit and the bit line control unit are all greater than the breakdown voltage of the programming unit.
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CN101790762A (en) * 2007-01-12 2010-07-28 Vns业务有限责任公司 The CMOS sram/rom unified bit cell
US8509004B2 (en) * 2009-11-24 2013-08-13 Samsung Electronics Co., Ltd. Nonvolatile logic circuit, integrated circuit including the nonvolatile logic circuit, and method of operating the integrated circuit
CN107004445A (en) * 2014-12-22 2017-08-01 高通股份有限公司 Volatile, nonvolatile SRAM device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6034886A (en) * 1998-08-31 2000-03-07 Stmicroelectronics, Inc. Shadow memory for a SRAM and method
CN101790762A (en) * 2007-01-12 2010-07-28 Vns业务有限责任公司 The CMOS sram/rom unified bit cell
CN101241763A (en) * 2007-02-06 2008-08-13 美格纳半导体有限会社 Semiconductor memory device
US8509004B2 (en) * 2009-11-24 2013-08-13 Samsung Electronics Co., Ltd. Nonvolatile logic circuit, integrated circuit including the nonvolatile logic circuit, and method of operating the integrated circuit
CN107004445A (en) * 2014-12-22 2017-08-01 高通股份有限公司 Volatile, nonvolatile SRAM device

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