CN111143141B - State machine setting method and system - Google Patents
State machine setting method and system Download PDFInfo
- Publication number
- CN111143141B CN111143141B CN201911345178.9A CN201911345178A CN111143141B CN 111143141 B CN111143141 B CN 111143141B CN 201911345178 A CN201911345178 A CN 201911345178A CN 111143141 B CN111143141 B CN 111143141B
- Authority
- CN
- China
- Prior art keywords
- state
- state machine
- processor
- information
- user
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
- G06F11/2242—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors in multi-processor systems, e.g. one processor becoming the test master
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/3664—Environments for testing or debugging software
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/36—Preventing errors by testing or debugging software
- G06F11/3668—Software testing
- G06F11/3672—Test management
- G06F11/3688—Test management for test execution, e.g. scheduling of test suites
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Debugging And Monitoring (AREA)
Abstract
The application discloses a state machine setting method and system. In the method, information of a state machine input by a user is acquired, wherein the information of the state machine comprises at least two states of a processor, triggering conditions of each state and real-time requirements; generating a program for realizing the state machine according to the information of the state machine; applying the program to a processor of a test environment and testing; and generating a test report according to the test result, and displaying the test report to a user, wherein the test report can reflect whether the test result meets the real-time requirement of the user. The method can realize the setting and testing of the state machine, and because the time requirement for state transition is set when the state machine is set, the transition process with the time requirement set by the user is timed when the state machine is tested, whether the currently set state machine can meet the requirement of the user on real-time performance is verified, and the hard real-time performance is ensured from the aspect of software.
Description
Technical Field
The present disclosure relates to the field of processor technologies, and in particular, to a method and system for setting a state machine.
Background
A multi-core processor refers to the integration of two or more complete compute engines (cores) in a single processor, where the processor can support multiple processors on a system bus, with all bus control signals and command signals provided by a bus controller.
Multicore processors can be categorized into symmetric processing (SMP) structures and asymmetric processing structures. Multiple mainline devices, such as processors and direct memory access (direct memory access, DMA), may be connected to the bus, either in a symmetric processing architecture or an asymmetric processing architecture. However, when there are a plurality of master devices on the bus, a bus arbitration mechanism is required, and when the plurality of master devices all request to occupy the bus to access the slave device, the plurality of master devices are arbitrated to determine the master device which can currently use the bus; in addition, the interrupt controller may interrupt the current task of the processor. Therefore, common multi-core processors sacrifice hard real-time performance for efficiency and bandwidth utilization purposes.
The multi-core processor shown in fig. 1 has only one master device in the lower bus, so that the situation that a plurality of master devices compete for the bus and a bus arbitration mechanism is required to be arranged in the bus to arbitrate requests of the plurality of master devices occupying the bus for access is avoided, and the real-time performance in the lower bus environment is improved. However, the above-described scheme only considers the hardware aspect, and there is currently no software control scheme applicable to the above-described hardware environment.
Disclosure of Invention
The application provides a state machine setting method and a state machine setting system, which are used for setting and testing a state machine of a processor in various hardware environments.
In a first aspect, an embodiment of the present application provides a state machine setting method, including:
acquiring information of a state machine input by a user, wherein the information of the state machine comprises at least two states of a processor and trigger conditions of each state, the information of the state machine further comprises real-time requirement information, the real-time requirement information comprises time requirements for transferring from a first state to a second state, and the first state and the second state belong to the at least two states;
generating a program for realizing the state machine according to the information of the state machine;
applying the program to a processor of a test environment and testing;
and generating a test report according to a test result, and displaying the test report to a user, wherein the test report comprises real-time indication information, and the real-time indication information is used for indicating whether the time for the processor to transition from the first state to the second state or whether the time for the processor to transition from the first state to the second state meets the time requirement when the trigger condition is met.
In one possible implementation, the method further includes:
obtaining a state machine tool library, the state machine tool library comprising: a plurality of states of the processor, and function information corresponding to each state;
the obtaining the information of the state machine input by the user comprises the following steps:
and acquiring information of a state selected by a user from the plurality of states.
In one possible implementation, the information of the state machine further includes output information, where the output information indicates information that needs to be output when the processor is in a target state, and the target state is any one of the at least two states.
In one possible implementation, after presenting the test report to the user, the method further includes:
receiving a confirmation writing instruction of a user;
writing the program for realizing the state machine into a processor to be configured or into a memory connected with the processor to be configured through an instruction bus; the processor to be configured is the same as or different from the processor of the test environment.
In one possible implementation, the processor to be configured is the only master device on the lower bus; and/or the processor is not installed with an operating system.
In a second aspect, embodiments of the present application provide a state machine setting system, including:
the interaction module is used for receiving information of a state machine input by a user, wherein the information of the state machine comprises at least two states of a processor and trigger conditions of each state, the information of the state machine also comprises real-time requirement information, the real-time requirement information comprises time requirements for transferring from a first state to a second state, and the first state and the second state belong to the at least two states;
the compiling module is used for generating a program for realizing the state machine according to the information of the state machine;
a test module, configured to apply the program to a processor in a test environment, perform a test, and generate a test report, where the test report includes real-time indication information, where the real-time indication information is used to indicate a time when the processor transitions from the first state to the second state when a trigger condition is met, or whether a time when the processor transitions from the first state to the second state meets the time requirement;
the interaction module is also used for displaying the test report to a user.
In one possible implementation, the system further includes:
the acquisition module is used for acquiring a state machine tool library, and the state machine tool library comprises: a plurality of states of the processor, and function information corresponding to each state;
the interaction module is specifically configured to: and displaying the multiple states and the corresponding functional information thereof to a user, and acquiring information of the state selected by the user from the multiple states.
In one possible implementation, the information of the state machine further includes output information, where the output information indicates information that needs to be output when the processor is in a target state, and the target state is any one of the at least two states.
In one possible implementation, the interaction module, after presenting the test report to a user, is further configured to: receiving a confirmation writing instruction of a user;
the system further comprises:
the programming module is used for writing the program for realizing the state machine into a processor to be configured or into a memory connected with the processor to be configured through an instruction bus; the processor to be configured is the same as or different from the processor of the test environment.
In one possible implementation, the processor to be configured is the only master device on the lower bus; and/or the processor is not installed with an operating system.
The state machine setting method and the state machine setting system can realize setting and testing of the state machine, simplify the setting complexity of the state machine, reduce the workload of designers, and can be applied to various hardware environments. Because the time requirement for state conversion can be further set when the state machine is set, the conversion process with the time requirement set by the user is timed when in test, whether the currently set state machine can meet the requirement of the user on real-time performance is verified, and the real-time performance of the processor on service processing is ensured from the aspect of software.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a multi-core processor according to an embodiment of the present disclosure;
FIG. 2 is a schematic flow chart of a state machine setting method according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of a state machine according to an embodiment of the present application
FIG. 4 is a second schematic diagram of a state machine according to an embodiment of the present disclosure;
fig. 5 is a state machine setting system provided in an embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be described in detail below. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, based on the examples herein, which are within the scope of the protection sought by those of ordinary skill in the art without undue effort, are intended to be encompassed by the present application.
The state machine setting method provided by the embodiment of the application is used for setting and testing the state machine of the processor in various hardware environments.
Referring to fig. 2, a flow chart of a state machine setting method according to an embodiment of the present application is shown, and the method may include the following steps:
step 201, information of a state machine input by a user is obtained.
Specifically, the information of the state machine input by the user may include at least two states of the processor and a trigger condition of each state. The triggering condition of the state refers to a condition that needs to be met by the processor entering the state. For example, a state machine entered by a user, including state 1 and state 2; the triggering condition of the state 1 is normal startup, which means that the processor enters the state 1 if the processor is started up normally after being electrified; the trigger condition of state 2 is that instruction a is accepted in the case of state 1, which means that the processor receives instruction a in the case of state 1, and state 2 is entered.
Further, the information of the state machine input by the user may further include real-time requirement information, wherein the real-time requirement information indicates a time requirement of the processor for transferring from the first state to the second state according to the state machine. Wherein the first state and the second state both belong to at least two states of the user input. For example, the user may set the real-time requirement for the processor to transition from state 1 to state 2 after receiving the instruction a to be 10ms, that is, to complete the transition from state 1 to state 2 within 10ms, so as to test the corresponding state transition completion time in the subsequent test process, and verify whether the requirement of the user on real-time can be met. It should be understood that when multiple state transition conditions exist in the state machine set by the user, the user may set one or more real-time requirements accordingly, may set real-time requirements for each state transition condition, or may set real-time requirements for only a portion of state transition conditions.
In addition, the information of the state machine may further include output information, where the output information indicates information that the processor needs to output when in a target state, and the target state may be any state input by a user. For example, the user may set that, when the processor is in the acquisition state, preset target information is acquired according to a preset period, and the acquired data is output to the display device.
Optionally, a state machine tool library may be obtained in advance, where the state machine tool library includes: the method comprises the steps of presetting multiple states of a processor and corresponding function information of each state. At this time, when the user sets the state machine, the user may select a desired state from the state machine tool library, and accordingly, in step 201, the information of the state selected by the user from the plurality of states in the state machine tool library may be obtained. The state machine tool library is preset, so that the process of setting the state machine by a user can be simplified. Further, the states and the functions corresponding to each state included in the state machine tool library may be preset by a user or preset by a developer of the tool library.
Step 202, generating a program for realizing the state machine according to the acquired information of the state machine.
Specifically, the program code for implementing the state machine may be generated according to the states included in the state machine set by the user and the trigger condition of each state.
As mentioned above, the state machine may be set by using a preset state machine tool library, and in one possible implementation, the state provided in the state machine tool library may also be set in advance according to the corresponding function, so that in step 202, a program for implementing the state machine set by the user may be generated according to the program provided in the state machine tool library.
Step 203, the generated program is applied to a processor of the test environment, and a test is performed.
For example, the generated program code may be written in a memory built in the test processor or in a memory connected to the test processor through a bus to enable the test processor to read and execute the program to perform the test. In the test process, whether the state machine setting can be realized, reasonable and perfect or not and whether the triggering condition is perfect and reasonable or not can be checked. Further, if the user also sets the real-time requirement, the state transition completion time is further timed to verify whether the user requirement can be met.
And 204, generating a test report according to the test result, and displaying the test report to a user.
After the test is completed, a test report can be generated according to the test result, the report can comprise whether the processor is abnormal or not when running according to a state machine set by a user, and the like, and when the user sets a real-time requirement, the test report can also comprise real-time indication information. For example, if the real-time requirement set by the user is that the real-time requirement for transferring from the state 1 to the state 2 after receiving the instruction a is 10ms; when the processor receives the instruction A, the time of transition from the state 1 to the state 2 is timed, and the state conversion is finished in 8ms when the processor is actually operated, so that the 8ms conversion time can be used as real-time indication information; alternatively, the actual conversion time (8 ms) may be compared with the real-time requirement (10 ms), so as to determine that the real-time requirement of the user is satisfied, and then the result of satisfying the real-time requirement of the user is used as the real-time indication information.
After the test report is generated, the test report is displayed to the user, so that the user can determine whether the set state machine is available, whether the set state machine needs to be modified and whether the real-time performance meets the requirement according to the test report.
Optionally, after the test report is presented to the user, if the user is not satisfied with the test result, the information of the set state machine may be modified and the test may be repeated. The method may further comprise: and receiving an instruction of a user for modifying the state machine information. Specifically, the state included in the state machine, the triggering condition of each state, the real-time requirement of state transition, and the like can be modified. After receiving the modification instruction of the user, the system can generate a program for realizing the modified state machine according to the information of the modified state machine, reapply the modified program to a processor of the test environment for testing, generate a test report according to the test result and display the test report to the user again.
Further, after presenting the test report to the user, the method may further comprise: and receiving a confirmation writing instruction of the user. The instruction indicates that the currently set state machine is available according to the test report by the user, and the user requirement can be met, and after the instruction is received, the program for realizing the state machine is written into the processor to be configured or is written into a memory connected with the processor to be configured through an instruction bus. Specifically, the processor to be configured may be a processor in the above-mentioned test environment, or may be other processors.
The state machine setting method provided by the embodiment of the application can be applied to setting the state machine for the processors in various hardware environments, and is particularly suitable for the unique main equipment on the lower bus and/or the processors without an operating system.
As shown in fig. 1, the multi-core processing system includes an upper bus and a lower data bus. The upper processor and the DMA are connected with an upper bus and serve as main equipment in an upper bus environment, wherein the upper processor can be provided with a cache (cache) or not; various memories and other peripheral devices are connected with the upper bus and serve as slave devices in the upper bus environment. The host processing and the DMA as the master device can access various memories and peripherals through the host bus. The upper processor is also connected with an interrupt controller 1, which is used for notifying the upper processor to interrupt the current task when the emergency task occurs and preferentially processing the emergency task. Therefore, the functions of external data exchange, man-machine interaction and the like without hard real time can be realized in the upper bus. The lower data bus is connected with a lower processor which is used as the only main equipment in the lower bus environment, and the lower processor is not provided with a cache (cache) so as to avoid interrupting the current task of the lower processor. The lower processor is also connected with bus slave equipment for storing program codes required by the lower processor; the lower processor may also have an interrupt handler 2 connected thereto, but the interrupt handler 2 is only used during the debug phase, and the interrupt handler 2 is not operated during the non-debug phase. The lower data bus is also connected with various memory devices and other peripheral devices, and the lower processor can access the memory devices and the peripheral devices through the lower data bus. The upper bus and the lower data bus are also connected through a lower line FIFO and an upper line FIFO respectively, and are used for realizing data exchange between equipment on the upper bus and equipment on the lower data bus.
In the processing system shown in fig. 1, only one master device is in the lower bus, and the processor serving as the only master device is not interrupted by the interrupt controller in the normal working state, so that the real-time performance of the processor is improved in terms of hardware. The state machine setting method provided by the embodiment of the application is applied to the lower processor, so that not only can the state machine of the processor be set, but also the real-time performance can be tested, and the convenience of ensuring the hard real-time performance from software can be realized.
For a clearer understanding of the above embodiments of the present application, an example is described below with reference to fig. 3.
The state machine tool library has been preconfigured with the following states: 1) An idle state, which means that the processor is in the idle state and does not perform any business operations; 2) A wait instruction state, indicating that the processor is in a wait or snoop state ready to respond to an instruction to be received; 3) Working state 1, which indicates that the processor performs data acquisition according to a preset period; 4) Controlling the state of the peripheral 1, wherein the state indicates that the processor controls the external device 1 to open a switch; 5) The control peripheral 2 state represents 100 stepping pulse signals to the peripheral 2 by the processor. Further, the tool library also comprises program codes corresponding to each state. Of course, other states may be configured in the tool library, which are not illustrated here.
When the user sets the state machine, the idle state, the waiting instruction state, the working state 1, the state of the control peripheral 1 and the state of the control peripheral 2 can be selected from the state machine tool library to form the state machine of the processor, and the triggering condition of each state is correspondingly set. For example, the trigger condition 1 in the idle state is that the processor is powered on and normally started, and the trigger condition 2 is that the state of the control peripheral 1 is finished (the trigger process is called path 4); the trigger condition 1 of the waiting instruction state is that indication information for entering the waiting instruction state is received in an idle state (the trigger process is called path 1.2), and the trigger condition 2 is that the state of the control peripheral 2 is finished (the trigger process is called path 5); the trigger condition 1 of the working state 1 is that indication information for entering the working state 1 is received in an idle state (the trigger process is called path 1.1), and the trigger condition 2 is that the trigger condition for entering the working state 1 is received in a waiting instruction state (the trigger process is called path 2); the triggering condition of the state of the control peripheral 1 is that indication information for entering the state of the control peripheral 1 is received in the working state 1 (the triggering process is called path 3.1); the triggering condition of the state of the control peripheral 2 is that indication information for entering the state of the control peripheral 2 is received in the working state 1 (the triggering process is called path 3.2). The state machine diagram shown in fig. 3 can be obtained according to the information of the state machine set by the user. The system can automatically compile the program codes for realizing the state machine shown in fig. 3 according to the program codes corresponding to each state preset in the tool library, and test.
Further, the user can set corresponding real-time requirements for the path 1.1, the path 1.2, the path 2, the path 3.1, the path 3.2, the path 4, the path 5 and the like, and in the test process, the path with the real-time requirements is timed, corresponding real-time indication information is generated according to timing data, and the real-time indication information is displayed to the user through a test report, so that the user can know whether the real-time requirements can be met in the current hardware environment and software environment.
In addition, the state machine setting method provided by the embodiment of the application also supports setting a plurality of parallel state machines. For example, as shown in fig. 4, the user may also set a set of state machines 2 in parallel with the state machine 1 shown in fig. 3 on the basis of the state machine shown in fig. 3. Signal interaction between state machine 1 and state 2 is also possible. Furthermore, the user can set a corresponding real-time requirement for the signal interaction process between the state machine 1 and the state machine 2, and time the interaction process in the test process and display the test result to the user.
Through the embodiment, the setting and testing of the state machine can be realized, the setting complexity of the state machine is simplified, the workload of a designer is reduced, and the method and the system can be applied to various hardware environments. Because the time requirement for state conversion can be further set when the state machine is set, the conversion process with the time requirement set by the user is timed when in test, whether the currently set state machine can meet the requirement of the user on real-time performance is verified, and the real-time performance of the processor on service processing is ensured from the aspect of software.
Based on the same technical concept, the embodiment of the application also provides a state machine setting system, which is used for executing the state machine setting method in any implementation mode. As shown in fig. 5, the state machine setting system may include:
the interaction module 501 is configured to receive information of a state machine input by a user, where the information of the state machine includes at least two states of a processor and a trigger condition of each state, and the information of the state machine further includes real-time requirement information, where the real-time requirement information includes a time requirement for transferring from a first state to a second state, and the first state and the second state belong to the at least two states.
A compiling module 502, configured to generate a program for implementing the state machine according to the information of the state machine.
A test module 503, configured to apply the program to a processor in a test environment, perform a test, and generate a test report, where the test report includes real-time indication information, where the real-time indication information is used to indicate a time when the processor transitions from the first state to the second state when a trigger condition is met, or whether a time when the processor transitions from the first state to the second state meets the time requirement.
The interaction module 501 is further configured to present the test report to a user.
In one possible implementation, the system further includes:
an obtaining module 504, configured to obtain a state machine tool library, where the state machine tool library includes: a plurality of states of the processor, and functional information corresponding to each state.
The interaction module 501 is specifically configured to: and displaying the multiple states and the corresponding functional information thereof to a user, and acquiring information of the state selected by the user from the multiple states.
In one possible implementation, the information of the state machine further includes output information, where the output information indicates information that needs to be output when the processor is in a target state, and the target state is any one of the at least two states.
In one possible implementation, the interaction module 501, after presenting the test report to the user, is further configured to: receiving a confirmation writing instruction of a user;
the system further comprises:
a programming module 505, configured to write the program for implementing the state machine into a processor to be configured, or into a memory connected to the processor to be configured through an instruction bus; the processor to be configured is the same as or different from the processor of the test environment.
In one possible implementation, the processor to be configured is the only master device on the lower bus; and/or the processor is not installed with an operating system.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (10)
1. A state machine setting method, comprising:
acquiring information of a state machine input by a user, wherein the information of the state machine comprises at least two states of a processor and trigger conditions of each state, the information of the state machine further comprises real-time requirement information, the real-time requirement information comprises time requirements for transferring from a first state to a second state, and the first state and the second state belong to the at least two states;
generating a program for realizing the state machine according to the information of the state machine;
applying the program to a processor of a test environment and testing;
generating a test report according to a test result, and displaying the test report to a user, wherein the test report comprises real-time indication information, and the real-time indication information is used for indicating whether the time for the processor to transition from the first state to the second state or whether the time for the processor to transition from the first state to the second state meets the time requirement when a trigger condition is met;
after presenting the test report to the user, further comprising: receiving an instruction of modifying state machine information of a user, and specifically modifying states contained in a state machine, triggering conditions of each state and real-time requirements of state conversion;
after receiving the modification instruction of the user, the system generates a program for realizing the modified state machine according to the information of the modified state machine, reappears the modified program to a processor of the test environment for testing, generates a test report according to the test result and displays the test report to the user again.
2. The method as recited in claim 1, further comprising:
obtaining a state machine tool library, the state machine tool library comprising: a plurality of states of the processor, and function information corresponding to each state;
the obtaining the information of the state machine input by the user comprises the following steps:
and acquiring information of a state selected by a user from the plurality of states.
3. The method of claim 1, wherein the state machine information further comprises output information representing information that needs to be output when the processor is in a target state, the target state being any one of the at least two states.
4. The method of claim 1, further comprising, after presenting the test report to a user:
receiving a confirmation writing instruction of a user;
writing the program for realizing the state machine into a processor to be configured or into a memory connected with the processor to be configured through an instruction bus; the processor to be configured is the same as or different from the processor of the test environment.
5. The method of claim 4, wherein the processor to be configured is the only master device on the lower bus; and/or the number of the groups of groups,
the processor is not equipped with an operating system.
6. A state machine setting system, comprising:
the interaction module is used for receiving information of a state machine input by a user, wherein the information of the state machine comprises at least two states of a processor and trigger conditions of each state, the information of the state machine also comprises real-time requirement information, the real-time requirement information comprises time requirements for transferring from a first state to a second state, and the first state and the second state belong to the at least two states;
the compiling module is used for generating a program for realizing the state machine according to the information of the state machine;
a test module, configured to apply the program to a processor in a test environment, perform a test, and generate a test report, where the test report includes real-time indication information, where the real-time indication information is used to indicate a time when the processor transitions from the first state to the second state when a trigger condition is met, or whether a time when the processor transitions from the first state to the second state meets the time requirement;
the interaction module is also used for displaying the test report to a user;
the interaction module, after presenting the test report to a user, is further configured to: receiving an instruction of modifying state machine information of a user, and specifically modifying states contained in a state machine, triggering conditions of each state and real-time requirements of state conversion;
after receiving the modification instruction of the user, the system generates a program for realizing the modified state machine according to the information of the modified state machine, reappears the modified program to a processor of the test environment for testing, generates a test report according to the test result and displays the test report to the user again.
7. The system of claim 6, further comprising:
the acquisition module is used for acquiring a state machine tool library, and the state machine tool library comprises: a plurality of states of the processor, and function information corresponding to each state;
the interaction module is specifically configured to: and displaying the multiple states and the corresponding functional information thereof to a user, and acquiring information of the state selected by the user from the multiple states.
8. The system of claim 6, wherein the state machine information further comprises output information representing information that needs to be output when the processor is in a target state, the target state being any one of the at least two states.
9. The system of claim 6, wherein the interaction module, after presenting the test report to a user, is further configured to: receiving a confirmation writing instruction of a user;
the system further comprises:
the programming module is used for writing the program for realizing the state machine into a processor to be configured or into a memory connected with the processor to be configured through an instruction bus; the processor to be configured is the same as or different from the processor of the test environment.
10. The system of claim 9, wherein the processor to be configured is the only master on a lower bus; and/or the number of the groups of groups,
the processor is not equipped with an operating system.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911345178.9A CN111143141B (en) | 2019-12-24 | 2019-12-24 | State machine setting method and system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911345178.9A CN111143141B (en) | 2019-12-24 | 2019-12-24 | State machine setting method and system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN111143141A CN111143141A (en) | 2020-05-12 |
| CN111143141B true CN111143141B (en) | 2023-07-25 |
Family
ID=70519600
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911345178.9A Active CN111143141B (en) | 2019-12-24 | 2019-12-24 | State machine setting method and system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111143141B (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107315591A (en) * | 2017-06-30 | 2017-11-03 | 上海棠棣信息科技股份有限公司 | A kind of service design method and system |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7131077B1 (en) * | 2003-03-28 | 2006-10-31 | Xilinx, Inc | Using an embedded processor to implement a finite state machine |
| CN101915894B (en) * | 2010-07-22 | 2012-05-30 | 北京交大资产经营有限公司 | Method for testing real-time finite-sate machine in digital logic device |
| US20140280528A1 (en) * | 2013-03-12 | 2014-09-18 | Rockwell Automation Technologies, Inc. | State machine configurator |
| GB2508447B (en) * | 2013-03-28 | 2014-10-22 | Randomize Ltd | Method and apparatus for testing electronic systems |
| US9619595B2 (en) * | 2014-03-20 | 2017-04-11 | Infineon Technologies Ag | Generation of test stimuli |
| GB201706300D0 (en) * | 2017-04-20 | 2017-06-07 | Microsoft Technology Licensing Llc | Debugging tool |
| CN107133184B (en) * | 2017-06-06 | 2020-02-18 | 湖南中易利华信息技术有限公司 | Configurable state machine implementation method, configurable state machine and terminal equipment |
-
2019
- 2019-12-24 CN CN201911345178.9A patent/CN111143141B/en active Active
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107315591A (en) * | 2017-06-30 | 2017-11-03 | 上海棠棣信息科技股份有限公司 | A kind of service design method and system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN111143141A (en) | 2020-05-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7246052B2 (en) | Bus master and bus slave simulation using function manager and thread manager | |
| US8112263B2 (en) | Method for logic checking to check operation of circuit to be connected to bus | |
| US6539500B1 (en) | System and method for tracing | |
| US8522079B2 (en) | System and method for multi-core synchronous debugging of a multi-core platform | |
| JPH02171934A (en) | Virtual machine system | |
| JPH06250871A (en) | Cpu core, asic having the cpu core and emulation system provided with the asic | |
| US6507809B1 (en) | Method and system for simulating performance of a computer system | |
| CN101506777A (en) | Multiprocessor system and method for synchronizing a debugging process of a multiprocessor system | |
| CN116049035B (en) | Verification and debugging realization method for cache consistency | |
| JP2010225094A (en) | Integrated circuit, debugging circuit and debugging command control method | |
| JPH03109644A (en) | Microcomputer | |
| JP2003015906A (en) | Remote debugging method and device | |
| CN111143141B (en) | State machine setting method and system | |
| CN109992539B (en) | Double-host cooperative working device | |
| US7231568B2 (en) | System debugging device and system debugging method | |
| JP2009175960A (en) | Virtual multiprocessor system | |
| JP2006268753A (en) | Dma circuit and computer system | |
| US7761280B2 (en) | Data processing apparatus simulation by generating anticipated timing information for bus data transfers | |
| US20050071145A1 (en) | Simulation apparatus, simulation program, and recording medium | |
| US8090991B2 (en) | Information processing apparatus, method, and computer program product for self-diagnosis for utilizing multiple diagnostic devices, each having exclusive access to a resource | |
| CN111045980A (en) | Multi-core processor | |
| CN102495770B (en) | Method and system for computer memory error analysis | |
| US11797421B2 (en) | Semiconductor apparatus and debug system | |
| JPH1185673A (en) | Method and device for controlling shared bus | |
| JPH02730B2 (en) |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |