CN111143141A - State machine setting method and system - Google Patents
State machine setting method and system Download PDFInfo
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- CN111143141A CN111143141A CN201911345178.9A CN201911345178A CN111143141A CN 111143141 A CN111143141 A CN 111143141A CN 201911345178 A CN201911345178 A CN 201911345178A CN 111143141 A CN111143141 A CN 111143141A
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
- G06F11/2242—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors in multi-processor systems, e.g. one processor becoming the test master
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
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Abstract
The application discloses a state machine setting method and system. In the method, information of a state machine input by a user is acquired, wherein the information of the state machine comprises at least two states of a processor, a trigger condition of each state and a real-time requirement; generating a program for realizing the state machine according to the information of the state machine; applying the program to a processor of a test environment and performing a test; and generating a test report according to the test result, and displaying the test report to the user, wherein the test report can reflect whether the test result meets the real-time requirement of the user. The method can realize the setting and testing of the state machine, and the time requirement for state conversion is set when the state machine is set, so that the conversion process with the time requirement set by a user is timed during testing, whether the currently set state machine can meet the requirement of the user on real-time performance is verified, and the hard real-time performance is ensured in the aspect of software.
Description
Technical Field
The present application relates to the field of processor technologies, and in particular, to a method and a system for setting a state machine.
Background
A multi-core processor is a processor that integrates two or more complete computing engines (cores) into one processor, and the processor can support multiple processors on a system bus, and a bus controller provides all bus control signals and command signals.
The multi-core processor may be divided into a symmetric multi-processing (SMP) structure, and an asymmetric processing structure. In either a symmetric or asymmetric processing architecture, multiple bus devices, such as processors and Direct Memory Access (DMA), may be connected to the bus. However, when there are multiple masters on the bus, a bus arbitration mechanism is needed, and when the multiple masters all request to occupy the bus to access the slave, the multiple masters are arbitrated to determine the masters that can currently use the bus; in addition, the interrupt controller may also interrupt the current task of the processor. Therefore, a common multi-core processor sacrifices hard real-time performance for the purposes of efficiency and sufficient utilization of bandwidth.
In the multi-core processor shown in fig. 1, only one master device is provided in the lower bus, so that the situation that a plurality of master devices compete for the bus and a bus arbitration mechanism needs to be arranged in the bus to arbitrate the request of the plurality of master devices for occupying the bus to access is avoided, and the improvement of the real-time performance in the lower bus environment is facilitated. However, the above scheme only considers the hardware aspect, and there is no software control scheme that can be applied to the above hardware environment at present.
Disclosure of Invention
The application provides a state machine setting method and a state machine setting system, which are used for setting and testing a state machine of a processor in various hardware environments.
In a first aspect, an embodiment of the present application provides a state machine setting method, including:
acquiring information of a state machine input by a user, wherein the information of the state machine comprises at least two states of a processor and a trigger condition of each state, the information of the state machine further comprises real-time requirement information, the real-time requirement information comprises a time requirement for switching from a first state to a second state, and the first state and the second state belong to the at least two states;
generating a program for realizing the state machine according to the information of the state machine;
applying the program to a processor of a test environment and performing a test;
and generating a test report according to the test result, and displaying the test report to a user, wherein the test report comprises real-time indication information, and the real-time indication information is used for indicating the time for the processor to be switched from the first state to the second state when a trigger condition is met, or whether the time for the processor to be switched from the first state to the second state meets the time requirement.
In one possible implementation, the method further includes:
obtaining a state machine tool library, the state machine tool library comprising: multiple states of the processor and function information corresponding to each state;
the acquiring information of the state machine input by the user comprises:
and acquiring information of the state selected by the user from the plurality of states.
In a possible implementation manner, the information of the state machine further includes output information, where the output information indicates information that needs to be output when the processor is in a target state, and the target state is any one state of the at least two states.
In one possible implementation, after presenting the test report to a user, the method further includes:
receiving a writing confirmation instruction of a user;
writing the program for realizing the state machine into a processor to be configured or into a memory connected with the processor to be configured through an instruction bus; the processor to be configured may be the same as or different from the processor of the test environment.
In one possible implementation, the processor to be configured is the only master device on the lower bus; and/or the processor is not installed with an operating system.
In a second aspect, an embodiment of the present application provides a state machine setting system, including:
the interaction module is used for receiving information of a state machine input by a user, the information of the state machine comprises at least two states of a processor and a trigger condition of each state, the information of the state machine further comprises real-time requirement information, the real-time requirement information comprises a time requirement for switching from a first state to a second state, and the first state and the second state belong to the at least two states;
the compiling module is used for generating a program for realizing the state machine according to the information of the state machine;
the test module is used for applying the program to a processor of a test environment, testing the processor and generating a test report, wherein the test report comprises real-time indication information, and the real-time indication information is used for indicating the time for the processor to be switched from the first state to the second state when a trigger condition is met, or whether the time for the processor to be switched from the first state to the second state meets the time requirement or not;
the interaction module is further used for displaying the test report to a user.
In one possible implementation, the system further includes:
an acquisition module to acquire a state machine tool library, the state machine tool library comprising: multiple states of the processor and function information corresponding to each state;
the interaction module is specifically configured to: and displaying the multiple states and the corresponding function information to a user, and acquiring the information of the state selected by the user from the multiple states.
In a possible implementation manner, the information of the state machine further includes output information, where the output information indicates information that needs to be output when the processor is in a target state, and the target state is any one state of the at least two states.
In one possible implementation manner, after presenting the test report to the user, the interaction module is further configured to: receiving a writing confirmation instruction of a user;
the system further comprises:
the programming module is used for writing the program for realizing the state machine into a processor to be configured or a memory connected with the processor to be configured through an instruction bus; the processor to be configured may be the same as or different from the processor of the test environment.
In one possible implementation, the processor to be configured is the only master device on the lower bus; and/or the processor is not installed with an operating system.
The method and the system for setting the state machine can realize setting and testing of the state machine, simplify the setting complexity of the state machine and reduce the workload of designers, and can be applied to various hardware environments. The time requirement for state conversion can be further set when the state machine is set, so that the conversion process with the time requirement set by the user is timed during testing, whether the currently set state machine can meet the real-time requirement of the user is verified, and the real-time performance of the processor on service processing is ensured in the aspect of software.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic structural diagram of a multi-core processor provided in an embodiment of the present application;
fig. 2 is a flowchart illustrating a state machine setting method according to an embodiment of the present application;
FIG. 3 is a schematic diagram of a state machine according to an embodiment of the present application
Fig. 4 is a second schematic diagram of a state machine according to an embodiment of the present application;
fig. 5 is a state machine setting system according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be described in detail below. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the examples given herein without making any creative effort, shall fall within the protection scope of the present application.
The method for setting the state machine is used for setting and testing the state machine of the processor in various hardware environments.
Referring to fig. 2, a schematic flowchart of a state machine setting method provided in an embodiment of the present application is shown, where the method may include the following steps:
Specifically, the information of the state machine input by the user may include at least two states of the processor and a trigger condition of each state. The trigger condition of a state refers to a condition that needs to be satisfied when a processor enters the state. For example, a state machine of user input, including state 1 and state 2; the triggering condition of the state 1 is normal startup, which means that the processor enters the state 1 if the processor is normally started after being electrified; the trigger condition of state 2 is that instruction a is received in the case of state 1, which means that the processor receives instruction a in the case of state 1, and then state 2 is entered.
Further, the user-entered information of the state machine may further include real-time requirement information indicating a time requirement for the processor to transition from the first state to the second state according to the state machine. Wherein the first state and the second state both belong to at least two states of the user input. For example, after receiving the instruction a, the user may set the real-time requirement for the processor to transition from the state 1 to the state 2 to 10ms, that is, the processor is required to complete the transition from the state 1 to the state 2 within 10ms, so that the corresponding state transition completion time is tested in the subsequent test process, and it is verified whether the requirement of the user on the real-time property can be met. It should be understood that when there are multiple state transition situations in the state machine set by the user, correspondingly, the user may also set one or more real-time requirements, may set a real-time requirement for each state transition situation, or may set a real-time requirement for only a part of the state transition situations.
In addition, the information of the state machine may further include output information indicating information that the processor needs to output when in a target state, which may be any state input by the user. For example, the user may set that, when the processor is in the collection state, preset target information is collected according to a preset period, and the collected data is output to the display device.
Optionally, a state machine tool library may be obtained in advance, where the state machine tool library includes: the method comprises the steps of presetting a plurality of states of the processor and corresponding function information of each state. In this case, when the user sets the state machine, the user may select a desired state from the state machine tool library, and accordingly, in step 201, the user may obtain information on the state selected from the plurality of states of the state machine tool library. And a state machine tool library is preset, so that the process of setting the state machine by a user can be simplified. Further, the states included in the state machine tool library and the functions corresponding to each state may be preset by the user or preset by the developer of the tool library.
Specifically, the program code for implementing the state machine may be generated according to the states included in the state machine set by the user and the trigger condition of each state.
As mentioned above, the state machine may be set by using a preset state machine tool library, and in a possible implementation manner, a program corresponding to each state may also be preset for the state provided in the state machine tool library according to the corresponding function, so that in the step 202, a program for implementing the state machine set by the user may be generated according to the program provided in the state machine tool library.
For example, the generated program code may be written in a memory built in the test processor or a memory connected to the test processor via a bus so that the test processor can read and execute the program to perform the test. In the test process, whether the state machine setting is realizable, reasonable and perfect and whether the trigger condition is perfect and reasonable can be checked. Further, if the user also sets a real-time requirement, the state transition completion time is further timed to verify whether the user requirements can be met.
And 204, generating a test report according to the test result, and displaying the test report to a user.
After the test is completed, a test report can be generated according to the test result, where the report may include whether the processor is abnormal when operating according to a state machine set by the user, and when the user sets a real-time requirement, the test report may further include real-time indication information. For example, if the real-time requirement set by the user is that the real-time requirement for transition from state 1 to state 2 after receiving the instruction a is 10 ms; in the test, the time for transferring from the state 1 to the state 2 after the processor receives the instruction A is timed, the state conversion is completed within 8ms when the processor is actually operated, and the 8ms conversion time can be used as real-time indication information; alternatively, the actual conversion time (8ms) may be compared with the real-time requirement (10ms), and the real-time requirement of the user is determined to be satisfied, and then the result of satisfying the real-time requirement of the user is used as the real-time indication information.
After the test report is generated, the test report is displayed to a user, so that the user can determine whether the set state machine is available or not, whether the set state machine needs to be modified or not and whether the real-time performance meets the requirement or not according to the test report.
Optionally, after the test report is displayed to the user, if the user is not satisfied with the test result, the information of the set state machine may be modified, and the test may be performed again. The method may further comprise: an instruction is received from a user to modify state machine information. Specifically, the states included in the state machine, the trigger condition of each state, the real-time requirement of state transition, and the like may be modified. After receiving a modification instruction of a user, the system can generate a program for realizing the modified state machine according to the modified state machine information, apply the modified program to the processor of the test environment again, test the program, generate a test report according to the test result and display the test report to the user again.
Further, after presenting the test report to the user, the method may further include: and receiving a confirmed writing instruction of a user. And after receiving the instruction, writing a program for realizing the state machine into a processor to be configured or writing the program into a memory connected with the processor to be configured through an instruction bus. Specifically, the processor to be configured may be the processor in the test environment, or may be another processor.
The state machine setting method provided by the above embodiments of the present application may be applied to setting a state machine for a processor in various hardware environments, and the method is particularly suitable for a unique master device on a lower bus and/or a processor without an operating system installed.
As shown in fig. 1, the multi-core processing system includes an upper bus and a lower data bus. The upper processor and the DMA are connected with an upper bus and used as main equipment in an upper bus environment, wherein the upper processor can be provided with a cache (cache) or not; various memories and other peripherals are connected with the upper bus and used as slave devices in the upper bus environment. The host processing and DMA as the host device can access various memories and peripherals through a host bus. The upper processor is also connected with an interrupt controller 1, which is used for informing the upper processor to interrupt the current task when an emergency task occurs and preferentially processing the emergency task. Therefore, the functions of external data exchange, man-machine interaction and the like which do not need hard real-time can be realized in the upper bus. The lower data bus is connected with a lower processor which is used as the only main device in the lower bus environment, and the lower processor is not provided with a cache (cache) so as to avoid causing interruption to the current task of the lower processor. The lower processor is also connected with a bus slave device for storing the program code required by the lower processor; the lower processor may be connected to an interrupt handler 2, but the interrupt handler 2 is used only in the debug phase and the interrupt handler 2 does not operate in the non-debug phase. Various memory devices and other peripherals are also connected to the lower data bus, and the lower processor can access the memory devices and the peripherals through the lower data bus. The upper bus and the lower data bus are connected through a downlink FIFO and an uplink FIFO respectively, and are used for realizing data exchange between equipment on the upper bus and equipment on the lower data bus.
In the processing system shown in fig. 1, there is only one master device in the lower bus, and the processor as the only master device is not interrupted by the interrupt controller in the normal operating state, which is helpful to improve the real-time performance of the processor from the aspect of hardware. The state machine setting method provided by the embodiment of the application is applied to the lower processor, the state machine of the processor can be set, and the real-time performance can be tested, so that the hard real-time performance can be conveniently guaranteed by software.
For a more clear understanding of the above-described embodiments of the present application, reference is now made to fig. 3 for illustration.
The state machine tool library has been preconfigured with the following states: 1) an idle state, which means that the processor is in the idle state and does not execute any business operation; 2) a wait for instruction state, indicating that the processor is in a wait or snoop state, ready to respond to instructions to be received; 3) the working state 1 represents that the processor performs data acquisition according to a preset period; 4) controlling the state of the peripheral 1, and indicating that the processor controls the external device 1 to open a switch; 5) The state of the peripheral 2 is controlled, and 100 stepping pulse signals are displayed to the external device 2 by the processor. Further, the tool library also comprises program codes corresponding to each state. Of course, other states may be configured in the tool library, and this is not illustrated here.
When setting the state machine, the user can select the idle state, the waiting instruction state, the working state 1, the control peripheral 1 state and the control peripheral 2 state from the state machine tool library to form the state machine of the processor, and correspondingly set the trigger condition of each state. For example, the triggering condition 1 of the idle state is that the processor is powered on and normally started, and the triggering condition 2 is that the state of the control peripheral 1 is ended (the triggering process is called as path 4); the trigger condition 1 of the waiting instruction state is that the indication information entering the waiting instruction state is received in the idle state (the trigger process is called path 1.2), and the trigger condition 2 is that the control peripheral 2 state is ended (the trigger process is called path 5); the trigger condition 1 of the working state 1 is that the indication information entering the working state 1 is received in an idle state (the trigger process is called as path 1.1), and the trigger condition 2 is that the trigger condition entering the working state 1 is received in a waiting instruction state (the trigger process is called as path 2); the triggering condition of the state of the control peripheral 1 is that indication information entering the state of the control peripheral 1 is received in the working state 1 (the triggering process is called as path 3.1); the triggering condition for the state of the controlling peripheral 2 is the receipt of an indication of the entering of the state of the controlling peripheral 2 in the operating state 1 (the triggering process is referred to as path 3.2). The state machine diagram as shown in fig. 3 can be obtained according to the information of the state machine set by the user. The system can automatically compile the program code for realizing the state machine shown in fig. 3 according to the program code corresponding to each state preset in the tool library, and perform testing.
Further, the user may set corresponding real-time requirements for the path 1.1, the path 1.2, the path 2, the path 3.1, the path 3.2, the path 4, the path 5, and the like, and in the test process, the path with the real-time requirements is timed, corresponding real-time indication information is generated according to the timing data, and the real-time indication information is displayed to the user through the test report, so that the user can know whether the real-time requirements can be met in the current hardware environment or software environment.
In addition, the state machine setting method provided by the embodiment of the application also supports setting of a plurality of parallel state machines. For example, as shown in fig. 4, on the basis of the state machine shown in fig. 3, the user can also set a set of state machines 2 in parallel with the state machine 1 shown in fig. 3. Signal interaction between state machine 1 and state machine 2 is also possible. Further, the user can set corresponding real-time requirements for the signal interaction process between the state machine 1 and the state machine 2, and the interaction process is timed in the test process, and the test result is displayed to the user.
Through the embodiment, the state machine can be set and tested, the setting complexity of the state machine is simplified, the workload of designers is reduced, and the method and the system can be applied to various hardware environments. The time requirement for state conversion can be further set when the state machine is set, so that the conversion process with the time requirement set by the user is timed during testing, whether the currently set state machine can meet the real-time requirement of the user is verified, and the real-time performance of the processor on service processing is ensured in the aspect of software.
Based on the same technical concept, the embodiment of the present application further provides a state machine setting system, which is configured to execute the state machine setting method according to any one of the above implementation manners. As shown in fig. 5, the state machine setting system may include:
the interaction module 501 is configured to receive information of a state machine input by a user, where the information of the state machine includes at least two states of a processor and a trigger condition of each state, and the information of the state machine further includes real-time requirement information, where the real-time requirement information includes a time requirement for transition from a first state to a second state, and the first state and the second state belong to the at least two states.
A compiling module 502, configured to generate a program for implementing the state machine according to the information of the state machine.
A testing module 503, configured to apply the program to a processor in a testing environment, perform a test, and generate a test report, where the test report includes real-time indication information, and the real-time indication information is used to indicate a time when the processor transitions from the first state to the second state when a trigger condition is met, or whether the time when the processor transitions from the first state to the second state meets the time requirement.
The interaction module 501 is further configured to display the test report to a user.
In one possible implementation, the system further includes:
an obtaining module 504, configured to obtain a state machine tool library, where the state machine tool library includes: multiple states of the processor, and functional information corresponding to each state.
The interaction module 501 is specifically configured to: and displaying the multiple states and the corresponding function information to a user, and acquiring the information of the state selected by the user from the multiple states.
In a possible implementation manner, the information of the state machine further includes output information, where the output information indicates information that needs to be output when the processor is in a target state, and the target state is any one state of the at least two states.
In a possible implementation manner, the interaction module 501, after presenting the test report to the user, is further configured to: receiving a writing confirmation instruction of a user;
the system further comprises:
a programming module 505, configured to write the program for implementing the state machine into a processor to be configured, or into a memory connected to the processor to be configured through an instruction bus; the processor to be configured may be the same as or different from the processor of the test environment.
In one possible implementation, the processor to be configured is the only master device on the lower bus; and/or the processor is not installed with an operating system.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is intended to include such modifications and variations.
Claims (10)
1. A state machine setting method, comprising:
acquiring information of a state machine input by a user, wherein the information of the state machine comprises at least two states of a processor and a trigger condition of each state, the information of the state machine further comprises real-time requirement information, the real-time requirement information comprises a time requirement for switching from a first state to a second state, and the first state and the second state belong to the at least two states;
generating a program for realizing the state machine according to the information of the state machine;
applying the program to a processor of a test environment and performing a test;
and generating a test report according to the test result, and displaying the test report to a user, wherein the test report comprises real-time indication information, and the real-time indication information is used for indicating the time for the processor to be switched from the first state to the second state when a trigger condition is met, or whether the time for the processor to be switched from the first state to the second state meets the time requirement.
2. The method of claim 1, further comprising:
obtaining a state machine tool library, the state machine tool library comprising: multiple states of the processor and function information corresponding to each state;
the acquiring information of the state machine input by the user comprises:
and acquiring information of the state selected by the user from the plurality of states.
3. The method of claim 1, wherein the information of the state machine further comprises output information, the output information indicating information that needs to be output when the processor is in a target state, the target state being any one of the at least two states.
4. The method of claim 1, after presenting the test report to a user, further comprising:
receiving a writing confirmation instruction of a user;
writing the program for realizing the state machine into a processor to be configured or into a memory connected with the processor to be configured through an instruction bus; the processor to be configured may be the same as or different from the processor of the test environment.
5. The method of claim 4, wherein the processor to be configured is the only master on the lower bus; and/or the presence of a gas in the gas,
the processor is not installed with an operating system.
6. A state machine setting system, comprising:
the interaction module is used for receiving information of a state machine input by a user, the information of the state machine comprises at least two states of a processor and a trigger condition of each state, the information of the state machine further comprises real-time requirement information, the real-time requirement information comprises a time requirement for switching from a first state to a second state, and the first state and the second state belong to the at least two states;
the compiling module is used for generating a program for realizing the state machine according to the information of the state machine;
the test module is used for applying the program to a processor of a test environment, testing the processor and generating a test report, wherein the test report comprises real-time indication information, and the real-time indication information is used for indicating the time for the processor to be switched from the first state to the second state when a trigger condition is met, or whether the time for the processor to be switched from the first state to the second state meets the time requirement or not;
the interaction module is further used for displaying the test report to a user.
7. The system of claim 6, further comprising:
an acquisition module to acquire a state machine tool library, the state machine tool library comprising: multiple states of the processor and function information corresponding to each state;
the interaction module is specifically configured to: and displaying the multiple states and the corresponding function information to a user, and acquiring the information of the state selected by the user from the multiple states.
8. The system of claim 6, wherein the information of the state machine further comprises output information indicating information that needs to be output when the processor is in a target state, the target state being any one of the at least two states.
9. The system of claim 6, wherein the interaction module, after presenting the test report to the user, is further configured to: receiving a writing confirmation instruction of a user;
the system further comprises:
the programming module is used for writing the program for realizing the state machine into a processor to be configured or a memory connected with the processor to be configured through an instruction bus; the processor to be configured may be the same as or different from the processor of the test environment.
10. The system of claim 9, wherein the processor to be configured is the only master on the lower bus; and/or the presence of a gas in the gas,
the processor is not installed with an operating system.
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| CN201911345178.9A Active CN111143141B (en) | 2019-12-24 | 2019-12-24 | State machine setting method and system |
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| US20180307587A1 (en) * | 2017-04-20 | 2018-10-25 | Microsoft Technology Licensing, Llc | Debugging tool |
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| CN104076763A (en) * | 2013-03-12 | 2014-10-01 | 洛克威尔自动控制技术股份有限公司 | State machine configurator |
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