CN111124963A - Method for realizing IIC interface slave equipment by CPLD, intelligent terminal and storage medium - Google Patents
Method for realizing IIC interface slave equipment by CPLD, intelligent terminal and storage medium Download PDFInfo
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Abstract
The invention discloses a method for realizing IIC interface slave equipment by a CPLD, an intelligent terminal and a storage medium, wherein the method comprises the following steps: the CPLD detects a read signal or a write signal sent by the master device; if the CPLD detects the reading signal, the CPLD receives data written by the master control CPU and sends the data to the master device; and if the CPLD detects the write signal, the CPLD receives the data written by the master device and sends the data to the master control CPU. According to the invention, the CPLD is used for detecting the level of the clock line, receiving or acquiring the read-write signal sent by the master device, and further sending data from the master control CPU to the master device or writing the data into the master control CPU, so that the function of the master control CPU as an IIC slave is realized under the condition of not occupying an IO pin of the master control CPU.
Description
Technical Field
The invention relates to the technical field of embedded driving, in particular to a method for realizing IIC interface slave equipment by a CPLD, an intelligent terminal and a storage medium.
Background
IIC buses are widely used in embedded devices, and are generally used for communication of slow devices, and the clock frequency is generally below several mhz. The method is divided into a master device and a slave device, point-to-point communication is carried out, a clock signal is generated by the master device, and the slave device receives and transmits data by using a clock of the master device. Most embedded main control CPUs are used as a host, and other peripheral chips are used as slaves.
However, if the device connected to the master CPU via I2C can only be the master, then the master CPU can only be the slave. Then the following problems arise: 1. some main control CPUs do not support a slave device mode; 2. some IO pins of the master control CPU are occupied, and the functions of the slave equipment cannot be realized; 3. by utilizing a GPIO (general purpose input/output) analog mode, the high and low level change of a clock is difficult to capture, the efficiency is very low, and a state machine is not stable.
Disclosure of Invention
In order to solve the problem that the function of a slave device cannot be realized when a main control CPU is installed on an IIC bus provided with a main device in the prior art, the invention provides a method for realizing the slave device with an IIC interface by a CPLD, an intelligent terminal and a storage medium.
The invention is realized by the following technical scheme:
a method for realizing IIC interface slave equipment by a CPLD comprises the following steps: the system comprises an IIC main line, main equipment connected with the IIC main line and a main control CPU connected with the IIC main line through a CPLD module, wherein the IIC main line comprises a clock line and a data line;
the CPLD acquires the level on the clock line and receives a read signal or a write signal on the data line;
when the CPLD receives the reading signal, the CPLD acquires first data sent by the master control CPU and sends the first data to the master device according to the priority sequence;
when the CPLD receives the write signal, the CPLD acquires second data of the master device and writes the second data into the master control CPU;
and the CPLD receives an end signal sent by the master device, and stops sending the first data to the master device or writing the second data into the master control CPU.
The method for realizing the IIC interface slave device by the CPLD, wherein before the CPLD acquires the level on the clock line and receives the read signal or the write signal on the data line, the method further comprises the following steps:
presetting the CPLD to be connected with the clock line and receiving a level signal of the clock line;
and presetting the CPLD to be connected with the data line and receiving or sending data along the data line.
The method for realizing the IIC interface slave device by the CPLD, wherein the step of acquiring the level on the clock line and receiving the read signal or the write signal on the data line by the CPLD specifically comprises the following steps:
when the level of the clock line is from low to high, the CPLD receives the read signal or the write signal on the data line.
The method for the CPLD to implement the IIC interface slave device, wherein when the CPLD receives the read signal, the CPLD obtains first data sent by the main control CPU and sends the first data to the main device in a priority order, specifically includes:
the CPLD acquires part of the first data sent by the main control CPU;
when the CPLD acquires that the level on the clock line is from low to high, the CPLD sends the acquired first data to the master device along the data line;
and the CPLD sends byte sending interruption to the main control CPU, acquires part of the first data sent by the main control CPU again and sends the first data to the main equipment.
The method for realizing the IIC interface slave device by the CPLD, wherein the step of sending the first data to the master device according to the priority order specifically comprises the following steps:
the CPLD preferentially receives and transmits the most significant bit in the first data;
and after the sending of the most significant bit in the first data is finished, the CPLD receives and sends the least significant bit in the first data.
The method for implementing the IIC interface slave device by the CPLD, wherein when the CPLD receives the write signal, the CPLD obtains second data of the master device, and writes the second data into the master CPU specifically includes:
the CPLD acquires partial second data sent by the master device;
the CPLD sends byte sending interruption to the main control CPU and sends part of the second data to the main control CPU;
and the CPLD acquires part of second data sent by the main equipment again and sends the second data to the main control CPU.
The CPLD method for implementing the IIC interface slave device, wherein the obtaining, by the CPLD, a portion of the second data sent by the master device specifically includes:
and the CPLD sequentially acquires single bits of the second data sent by the master device.
The method for the CPLD to implement the IIC interface slave device, where sending a byte sending interrupt to the master CPU and sending part of the second data to the master CPU specifically includes:
when the CPLD acquires the single bit of the second data to reach the target number, the CPLD sends a write-in interrupt to the main control CPU;
and the CPLD writes the second data into the main control CPU.
An intelligent terminal, comprising: the device comprises a memory, a processor and a CPLD (complex programmable logic device) realizing IIC interface slave device program which is stored on the memory and can run on the processor, wherein when the CPLD realizing IIC interface slave device program is executed by the processor, the CPLD realizing IIC interface slave device method is realized.
A storage medium stores a CPLD slave device program for realizing an IIC interface, and when the CPLD slave device program for realizing the IIC interface is executed by a processor, the CPLD slave device method for realizing the IIC interface is realized.
The invention has the beneficial effects that:
according to the invention, the CPLD is used for detecting the level of the clock line, receiving or acquiring the read-write signal sent by the master device, and further sending data from the master control CPU to the master device or writing the data into the master control CPU, so that the function of the master control CPU as an IIC slave is realized under the condition of not occupying an IO pin of the master control CPU.
Drawings
FIG. 1 is a flowchart of a method for implementing an IIC interface slave device by a CPLD according to the present invention;
FIG. 2 is a flowchart illustrating the operation of step S210 in FIG. 1 according to the present invention;
FIG. 3 is a flowchart illustrating the operation of step S220 in FIG. 1 according to the present invention;
fig. 4 is a schematic diagram of an operating environment of an intelligent terminal according to the present invention.
Detailed Description
In order to make the objects, technical solutions and effects of the present invention clearer and clearer, the present invention is further described in detail below with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Referring to fig. 1, the present invention discloses a method for implementing IIC interface slave device by CPLD, which is applied in an IIC provided with a master device, where the IIC refers to an Integrated Circuit bus (Inter-Integrated Circuit), and specifically is a Circuit system in which a peripheral Circuit is Integrated on a single chip microcomputer, and generally, the IIC has a master device and a plurality of slave devices, and the master device sends an instruction to the slave devices to enable the slave devices to execute corresponding operations according to the instruction.
The method for realizing the IIC interface slave device by the CPLD specifically comprises the following steps: the system comprises an IIC main line, main equipment connected with the IIC main line and a main control CPU connected with the IIC main line through a CPLD module, wherein the IIC main line comprises a clock line and a data line.
The CPLD (Complex Programmable Logic Device) is a highly integrated multi-Logic block unit, each Logic block can be connected with each other by using Programmable internal connection lines, and the input or output function of CPLD pins can be turned on or off by programming the Logic blocks. In the present invention, the-transceiving information through the CPLD or separately receiving information to realize the IIC slave function.
The method for realizing the IIC interface slave device by the CPLD specifically comprises the following steps:
s001, presetting the CPLD to be connected with the clock line, and receiving a level signal of the clock line;
and S002, presetting the CPLD to be connected with the data line, and receiving or sending data along the data line.
As can be seen from the above, the IIC slave device mainly functions as: the slave device may receive instructions sent by the master device to perform the corresponding operations. In the IIC, each device transmits data, receives data, or transmits an instruction to a slave device along a data line, and a time point of transmitting and receiving data is dependent on a level rise and fall of the clock line. Since the slave device only executes instructions sent by the master device, such as: sending data to the master device for the master device to read; and writing the data sent by the main device. When the master device needs to read data or write data into the slave device, the master device can actively change the level of the time line to enable the data to be transmitted along the data line, and the slave device can transmit and receive the data according to the level change of the clock line.
Thus, in the present invention, the CPLD only needs to receive a change in the level of the clock line to receive or transmit data along the data line, without actively modifying the level of the clock line. So in steps S001-S002:
the CPLD only receives level signals of a clock line, and the level transmission directions of the CPLD and the clock line are unidirectional, namely 'clock line-CPLD-master control CPU';
the data transmission between the CPLD and the data line is bidirectional, and the data of the master device can be transmitted to the CPLD along the data line or written into the master device by the CPLD.
After the CPLD is connected with the IIC bus, the method for realizing the IIC interface slave device by the CPLD comprises the following steps:
and S100, the CPLD acquires the level on the clock line and receives a read signal or a write signal on the data line.
In step S100, the CPLD obtains the level on the clock line by detecting the level of the clock line once every a period of time, and if the level of the clock line is detected to be low at a certain time and the level of the clock line is detected to be high again, determining that the level of the clock line is rising; otherwise, if the level of the clock line is detected to be high at a certain time and the level of the clock line is detected to be low again, the level of the clock line is judged to be lowered.
The master device sends the command for reading and writing the data of the slave device along the rising of the level of the clock line, so when the rising of the level of the clock line is detected, the CPLD receives the reading signal or the writing signal of the data line.
Referring to fig. 2 and fig. 3, the following sequentially describes the steps executed when the CPLD receives the read signal and the write signal:
s210, when receiving the reading signal, the CPLD acquires first data sent by the main control CPU, and sends the first data to the main device according to the priority order.
Referring to fig. 2, when the master device sends a read signal to the slave device, it indicates that the master device needs to read data in the slave device, which is specifically embodied in the present invention as follows: the master device needs to read data in the main control CPU, where step S210 specifically includes:
s211, the CPLD acquires part of the first data sent by the main control CPU.
S212, when the CPLD acquires that the level on the clock line is from low to high, the CPLD sends the acquired first data to the master device along the data line.
And S213, sending byte sending interruption to the main control CPU by the CPLD, acquiring part of the first data sent by the main control CPU again, and sending the first data to the main equipment.
In step S212, the CPLD sends data in the master CPU to the master device by raising the level of the clock line.
In step S213, the CPLD transmits the data in the main control CPU to the main device for a plurality of times:
the CPLD receives a part of the first data sent by the main control CPU once;
sending part of the first data to the master device along a clock line, and sending a byte sending interrupt to indicate that the CPLD sends the data sent by the master CPU to the master device;
after receiving the byte transmission interruption, the main control CPU continuously transmits part of the first data to the CPLD;
when the CPLD sends all the first data to the master device, the master device sends an end signal to the CPLD through the data line, the CPLD sends a read cycle interrupt to the master control CPU, the master control CPU does not send data to the CPLD any more, and the CPLD stops receiving data from the master control CPU and sending data to the master device.
In step S213, the main control CPU preferably transmits the first data to the master device by: and the master control CPU preferentially sends the most significant bit in the first data to the CPLD, and after the sending of the most significant bit is finished, the least significant bit in the first data is sent to the CPLD until the sending of the first data is finished. And the main control CPU sends the first data to the CPLD according to bits (bit), and when the bits in the CPLD reach 8 bits (8bit), the main control CPU sends the part of the first data to the main equipment.
And S220, when the CPLD receives the write signal, the CPLD acquires second data of the master device and writes the second data into the master control CPU.
Referring to fig. 3, when the master device sends a write signal to the slave device, it indicates that the master device needs to write data into the slave device, which is specifically embodied in the present invention as follows: the master device needs to write data into the main control CPU, where step S220 specifically includes:
s221, the CPLD acquires partial second data sent by the master device.
S222, the CPLD sends byte sending interruption to the main control CPU, and sends part of the second data to the main control CPU.
And S223, the CPLD acquires part of second data sent by the main device again and sends the second data to the main control CPU.
The same as the step S210, the master device transfers data to the master CPU through a CPLD. As a preferred embodiment of the present invention, the master device sends 1-bit (bit) data to the CPLD at a time. And writing part of the second data stored in the CPLD into the master CPU by the master CPU every time when the CPLD continuously acquires bits and accumulates to a target number. Preferably, the target number is 8 bits.
And the CPLD sends write-once interruption to the main control CPU so as to apply for writing the second data into the main control CPU. And after receiving the write interruption, the master control CPU writes the 8-bit data of the second data into the master control CPU through the CPLD.
After the second data are completely sent, the master device sends an end signal to the CPLD through the data line, the CPLD sends a write cycle interrupt to the master control CPU, the master device stops sending data to the CPLD, and the master control CPU stops writing data from the CPLD.
When the read cycle or the write cycle is over, the master device sends an end signal to the CPLD through the IIC bus to end the data transmission, because the step S210 or S220 includes:
s300, the CPLD receives an end signal sent by the master device, and stops sending the first data to the master device or writing the second data into the master control CPU.
The step S300 is specifically as follows:
at the end of the read cycle:
when the CPLD sends all the first data to the master device, the master device sends an end signal to the CPLD through the data line, the CPLD sends a read cycle interrupt to the master control CPU, the master control CPU does not send data to the CPLD any more, and the CPLD stops receiving data from the master control CPU and sending data to the master device.
At the end of the write cycle;
after the second data are completely sent, the master device sends an end signal to the CPLD through the data line, the CPLD sends a write cycle interrupt to the master control CPU, the master device stops sending data to the CPLD, and the master control CPU stops writing data from the CPLD.
Referring to fig. 4, based on the above-mentioned method for implementing IIC interface slave device by CPLD, the present invention provides an intelligent terminal 10, which includes: a memory 11, a processor 12, and a CPLD-enabled IIC interface slave program 13 stored on the memory 11 and operable on the processor 12, the CPLD-enabled IIC interface slave program 13, when executed by the processor 12, implementing the steps of:
s001, presetting the CPLD to be connected with the clock line, and receiving a level signal of the clock line;
and S002, presetting the CPLD to be connected with the data line, and receiving or sending data along the data line.
And S100, the CPLD acquires the level on the clock line and receives a read signal or a write signal on the data line.
The CPLD executes step S210 or step S220, respectively, according to whether the received signal is a read signal or a write signal:
s210, when receiving the reading signal, the CPLD acquires first data sent by the main control CPU, and sends the first data to the main device according to the priority order.
The step S210 specifically includes:
s211, the CPLD acquires part of the first data sent by the main control CPU.
S212, when the CPLD acquires that the level on the clock line is from low to high, the CPLD sends the acquired first data to the master device along the data line.
And S213, sending byte sending interruption to the main control CPU by the CPLD, acquiring part of the first data sent by the main control CPU again, and sending the first data to the main equipment.
And S220, when the CPLD receives the write signal, the CPLD acquires second data of the master device and writes the second data into the master control CPU.
The step S220 specifically includes:
s221, the CPLD acquires partial second data sent by the master device.
S222, the CPLD sends byte sending interruption to the main control CPU, and sends part of the second data to the main control CPU.
And S223, the CPLD acquires part of second data sent by the main device again and sends the second data to the main control CPU.
S300, the CPLD receives an end signal sent by the master device, and stops sending the first data to the master device or writing the second data into the master control CPU.
Based on the method for realizing the IIC interface slave device by the CPLD, the invention provides a storage medium, wherein the storage medium stores a CPLD slave device program for realizing the IIC interface, and the CPLD slave device program for realizing the IIC interface is executed by a processor to realize the method for realizing the IIC interface slave device by the CPLD.
The invention discloses a method for realizing IIC interface slave equipment by a CPLD, which comprises the following steps: the CPLD detects the level of the clock line, receives or acquires a read-write signal sent by the master device, and then sends data to the master device from the master control CPU or writes the data into the master control CPU, so that the function of the master control CPU as an IIC slave is realized. The method for realizing the IIC interface slave device based on the CPLD can realize the same effect as the method for realizing the IIC interface slave device by the CPLD when the intelligent terminal and the storage medium are applied.
It is to be understood that the invention is not limited to the examples described above, but that modifications and variations may be effected thereto by those of ordinary skill in the art in light of the foregoing description, and that all such modifications and variations are intended to be within the scope of the invention as defined by the appended claims.
Claims (10)
1. A method for realizing IIC interface slave equipment by a CPLD is characterized by comprising the following steps: the system comprises an IIC main line, main equipment connected with the IIC main line and a main control CPU connected with the IIC main line through a CPLD module, wherein the IIC main line comprises a clock line and a data line;
the CPLD acquires the level on the clock line and receives a read signal or a write signal on the data line;
when the CPLD receives the reading signal, the CPLD acquires first data sent by the master control CPU and sends the first data to the master device according to the priority sequence;
when the CPLD receives the write signal, the CPLD acquires second data of the master device and writes the second data into the master control CPU;
and the CPLD receives an end signal sent by the master device, and stops sending the first data to the master device or writing the second data into the master control CPU.
2. The CPLD slave method of claim 1, wherein said CPLD further comprises, before obtaining the level on said clock line and receiving a read signal or a write signal on said data line:
presetting the CPLD to be connected with the clock line and receiving a level signal of the clock line;
and presetting the CPLD to be connected with the data line and receiving or sending data along the data line.
3. The CPLD slave device method according to claim 1 or 2, wherein the obtaining of the level on the clock line and the receiving of the read signal or the write signal on the data line by the CPLD specifically includes:
when the level of the clock line is from low to high, the CPLD receives the read signal or the write signal on the data line.
4. The CPLD slave device method according to claim 3, wherein when the CPLD receives the read signal, the CPLD obtains first data sent by the main control CPU, and sends the first data to the master device in the priority order, specifically includes:
the CPLD acquires part of the first data sent by the main control CPU;
when the CPLD acquires that the level on the clock line is from low to high, the CPLD sends the acquired first data to the master device along the data line;
and the CPLD sends byte sending interruption to the main control CPU, acquires part of the first data sent by the main control CPU again and sends the first data to the main equipment.
5. The CPLD method for implementing the IIC interface slave device according to claim 4, wherein the sending the first data to the master device in priority order specifically comprises:
the CPLD preferentially receives and transmits the most significant bit in the first data;
and after the sending of the most significant bit in the first data is finished, the CPLD receives and sends the least significant bit in the first data.
6. The CPLD slave device method according to claim 3, wherein when the CPLD receives the write signal, the CPLD obtains the second data of the master device and writes the second data into the master CPU specifically includes:
the CPLD acquires partial second data sent by the master device;
the CPLD sends byte sending interruption to the main control CPU and sends part of the second data to the main control CPU;
and the CPLD acquires part of second data sent by the main equipment again and sends the second data to the main control CPU.
7. The CPLD slave device method according to claim 6, wherein the obtaining, by the CPLD, a portion of the second data sent by the master device specifically includes:
and the CPLD sequentially acquires single bits of the second data sent by the master device.
8. The CPLD slave device method according to claim 7, wherein the sending, by the CPLD, a byte sending interrupt to the master CPU and sending a portion of the second data to the master CPU specifically includes:
when the CPLD acquires the single bit of the second data to reach the target number, the CPLD sends a write-in interrupt to the main control CPU;
and the CPLD writes the second data into the main control CPU.
9. An intelligent terminal, characterized in that, intelligent terminal includes: a memory, a processor, and a CPLD-enabled IIC interface slave program stored on the memory and executable on the processor, which when executed by the processor, implements the CPLD-enabled IIC interface slave method of any one of claims 1-8.
10. A storage medium storing a CPLD slave device program for implementing an IIC interface, wherein the CPLD slave device program for implementing an IIC interface implements the CPLD slave device method according to any one of claims 1 to 8 when executed by a processor.
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Application publication date: 20200508 |