CN103530261A - Circuit and management method for access to multiple slaves having same I2C address - Google Patents
Circuit and management method for access to multiple slaves having same I2C address Download PDFInfo
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- CN103530261A CN103530261A CN201310523183.0A CN201310523183A CN103530261A CN 103530261 A CN103530261 A CN 103530261A CN 201310523183 A CN201310523183 A CN 201310523183A CN 103530261 A CN103530261 A CN 103530261A
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Abstract
The invention discloses a circuit and a management method for the access to multiple slaves having the same I2C address. The circuit comprises an I2C master and a plurality of I2C slaves. The I2C slaves have the same address. The circuit further comprises a decoder and AND gates. The input end of the decoder is connected with the I2C master. The output ends of the decoder are connected with one input ends of corresponding AND gates. The other input ends of the AND gates are connected with a clock wire. The output ends of the AND gates are connected with clock wires of the corresponding I2C slaves. The circuit and the management method have the advantages that the multiple I2C slaves in the same I2C bus can be independently configured and managed with no need of adding few devices; the circuit is simple in structure and low in cost.
Description
Technical field
The present invention relates to I2C bus field, more specifically, relate to a kind of a plurality of circuit and management methods with identical I2C address slave of accessing.
Background technology
I2C bus is due to advantages such as it are simple, flexible, hardware pin resource is few at present, in communicating by letter between device and device, have a wide range of applications, in the I2C of standard bus protocol, physical link is respectively a serial data (SDA) and a serial clock (SCL).Device in bus is divided into main frame and slave.In common application, as Fig. 1, in I2C bus, be generally a MCU and serve as main frame, remaining peripheral IC serves as slave, and MCU is responsible for other IC in configuration management bus.Because each slave generally all has a unique address, main frame can pass through this address, configures and manage corresponding slave.Configuration communication mode between main frame and slave is as follows:
1, main frame produces initiation of communication sequential, and SCL is high level, and SDA changes from high to low.
2, main frame starts to transmit packet, first transmits appropriate address, and the slave in each bus, when receiving address, can compare with self address, as identical with self address, can send a response signal.
3, Host Detection, after response signal, illustrates that corresponding slave is addressed to, and can carry out reading and writing data.
4, last, main frame is by producing sign off sequential, and SCL is high level, and SDA changes from low to high, finishes communication.
But in actual application, when the slave of carry is more in I2C bus, there will be a plurality of slave addresses same cases, for this situation, adopt aforesaid way main frame to configure separately and to manage thering is the slave of identical address.So head it off is generally by the corresponding hardware pin of configuration slave at present, address is different each other to make it, but the method has certain limitation, cannot meet the needs of more slave.And because the address of part slave is fixed address, cannot configure.Cannot be to thering is independent management and the configuration of a plurality of identical address slaves by traditional circuit and method.
summary of the invention
In order to overcome the deficiency of the identical slave configuration management in a plurality of I2C address in prior art, first a kind of a plurality of circuit with identical I2C address slave of accessing are proposed, adopt this circuit without the hardware pin that increases corresponding slave, can realize and configure separately and manage having the slave of identical address, limitation is little.
To achieve these goals, its technical scheme is:
A kind ofly access a plurality of circuit with identical I2C address slave, comprise I2C main frame and a plurality of I2C slave, I2C slave contains the identical I2C slave in address, also comprise code translator and with door, the input termination I2C main frame of code translator, each output terminal of code translator is connected with an input end of door with corresponding, is connected with clock line with another input end of door, is connected the clock line of corresponding I2C slave with the output terminal of door.
Circuit of the present invention adds one and door by the serial clock SCL link front end of the I2C slave identical in each address, I2C host side adds a code translator, by the SCL of the output of code translator and I2C bus by being connected to the SCL port of corresponding I2C slave with gate logic.Adopt sort circuit mode, when identical address I2C slave is carried out to addressing, I2C main frame is by dragging down the I2C slave scl line of other identical address with gate logic, make it not receive the data message that I2C main frame sends, on hardware, realize " isolation " to it, need addressed I2C slave can receive complete data message, thereby realize thering is independent management and the configuration of the I2C slave of identical address.
It is of the present invention that to have an object be to propose a kind of a plurality of management methods with identical I2C address slave of accessing, for realizing the access of I2C main frame to the identical I2C slave in m address,
I2C main frame is exported by code translator, and keeping corresponding with i I2C slave and door input end is high level, and all the other and an input end are low level, wherein i=0,1 ..., m;
I2C main frame produces initiation of communication sequential, and serial clock SCL is high level, and serial data SDA changes from high to low;
I2C main frame starts to transmit packet, transmission appropriate address, and the I2C slave in each I2C bus, when receiving address, can compare with self address, as identical with self address, can send a response signal;
I2C Host Detection, after response signal, illustrates that corresponding I2C slave is addressed to, and carries out reading and writing data;
I2C main frame is by producing sign off sequential, and serial clock SCL is high level, and serial data SDA changes from low to high, finishes communication.
Adopt this management method, increase is controlled with door output the I2C slave of identical address, makes the I2C slave that need to be configured by accessing I2C bus with door, and other I2C slaves are realized " isolation " with bus.Thereby realized thering is independent management and the configuration of identical address I2C slave.
Compared with prior art, beneficial effect of the present invention is: circuit of the present invention and management method only need increase a small amount of device, can realize independent configuration and management to the I2C slave of a plurality of concrete identical address in same I2C bus; There is simple, the lower-cost advantage of circuit structure.
Accompanying drawing explanation
Fig. 1 is the structural drawing that existing main frame adopts I2C bus access slave.
Fig. 2 is the circuit structure diagram of embodiment mono-.
Fig. 3 is the circuit structure diagram of embodiment bis-.
Embodiment
Below in conjunction with accompanying drawing, the present invention will be further described, but embodiments of the present invention are not limited to this.
Embodiment mono-
As shown in Figure 2, a kind ofly access a plurality of circuit with identical I2C address slave, comprise I2C main frame, four I2C slaves that address is identical, 3-8 line code translator and four and door, the input termination I2C main frame of 3-8 line code translator, each output terminal of 3-8 line code translator is connected with an input end of door with corresponding, is connected with clock line with another input end of door, is connected corresponding I2C slave clock line with the output terminal of door.
Circuit of the present invention adds one and door by the serial clock SCL link front end of the I2C slave identical in each address, I2C host side adds a code translator, by the SCL of the output of code translator and I2C bus by being connected to the SCL port of corresponding I2C slave with gate logic.Adopt sort circuit mode, when identical address I2C slave is carried out to addressing, I2C main frame is by dragging down the I2C slave scl line of other identical address with gate logic, make it not receive the data message that I2C main frame sends, on hardware, realize " isolation " to it, need addressed I2C slave can receive complete data message, thereby realize thering is independent management and the configuration of the I2C slave of identical address.
The identical I2C slave in above-mentioned four addresses is I2C slave 1# to I2C slave 4#, and the management method of host access I2C slave 1# is as follows:
1) main frame is exported by 3-8 line code translator, and keeping I2C slave 1# and door input end is high level, and all the other are low level with door input end.Due to door characteristic: 0 AND X=0,1 AND X=X, all the other and goalkeeper keep low level output, the SCL input end that is I2C slave 2# to I2C slave 4# is low level, so both can guarantee to only have 1# slave can receive complete SDA and SCL data, and other slaves are because SCL is low always, thus do not receive corresponding SDA data, and can not make respective response.
2) main frame produces initiation of communication sequential, and SCL is high level, and SDA changes from high to low.
3) main frame starts to transmit packet, first transmits appropriate address, and the slave in each bus, when receiving address, can compare with self address, as identical with self address, can send a response signal.
4) Host Detection, after response signal, illustrates that corresponding slave is addressed to, and can carry out reading and writing data.
5) last, main frame is by producing sign off sequential, and both SCL was high, and SDA changes from low to high, finishes communication.
Increase is controlled with door output the I2C slave of identical address, makes the I2C slave that need to be configured by accessing I2C bus with door, and other I2C slaves are realized " isolation " with bus.Thereby realized thering is independent management and the configuration of identical address I2C slave.
In actual application, according to the quantity situation of the identical slave in address, can select different code translators, adopt 3-8 line code translator additionally to increase by 3 host hardware pins and just can manage the slave of 8 identical address.If adopt 4-16 code translator, be that 4 host hardware pins of extra increase just can be managed the slave of 16 identical address.Adopt existing and gate logic device with door in the present embodiment, can also adopt as required non-conjunction or " rejection gate " to realize.
Embodiment bis-
As shown in Figure 3, can also adopt with door diode and the resistance that cost is lower, specifically comprise diode D1, diode D2 and resistance R, the anodic bonding of diode D1 and diode D2, and connecing power supply by resistance R, diode D1 and the anode of diode D2 are also connected the clock line of corresponding I2C slave; The negative electrode of diode D1 connects clock line, and the negative electrode of diode D2 connects an output terminal of 3-8 line code translator.
Above-described embodiments of the present invention, do not form limiting the scope of the present invention.Any modification of having done within spiritual principles of the present invention, be equal to and replace and improvement etc., within all should being included in claim protection domain of the present invention.
Claims (6)
1. access a plurality of circuit with identical I2C address slave for one kind, comprise I2C main frame and a plurality of I2C slave, I2C slave contains the identical I2C slave in address, it is characterized in that, also comprise code translator and with door, the input termination I2C main frame of code translator, each output terminal of code translator with corresponding with an input end be connected, be connected with clock line with another input end of door, be connected the clock line of corresponding I2C slave with the output terminal of door.
2. a plurality of circuit with identical I2C address slave of access according to claim 1, it is characterized in that, described and door comprises diode D1, diode D2 and resistance R, the anodic bonding of described diode D1 and diode D2, and connecing power supply by resistance R, diode D1 and the anode of diode D2 are also connected the clock line of corresponding I2C slave; The negative electrode of diode D1 connects clock line, and the negative electrode of diode D2 connects an output terminal of code translator.
3. a plurality of circuit with identical I2C address slave of access according to claim 1 and 2, is characterized in that, described code translator is 3-8 line code translator or 4-16 line code translator.
4. a plurality of management methods with identical I2C address slave of access, for realizing the access of I2C main frame to the identical I2C slave in m address, is characterized in that,
I2C main frame is exported by code translator, and keeping corresponding with i I2C slave and door input end is high level, and all the other and an input end are low level, wherein i=0,1 ..., m;
I2C main frame produces initiation of communication sequential, and serial clock SCL is high level, and serial data SDA changes from high to low;
I2C main frame starts to transmit packet, transmission appropriate address, and the I2C slave in each I2C bus, when receiving address, can compare with self address, as identical with self address, can send a response signal;
I2C Host Detection, after response signal, illustrates that corresponding I2C slave is addressed to, and carries out reading and writing data;
I2C main frame is by producing sign off sequential, and serial clock SCL is high level, and serial data SDA changes from low to high, finishes communication.
5. a plurality of management methods with identical I2C address slave of access according to claim 4, it is characterized in that, described and door comprises diode D1, diode D2 and resistance R, the anodic bonding of described diode D1 and diode D2, and connecing power supply by resistance R, diode D1 and the anode of diode D2 are also connected the clock line of corresponding I2C slave; The negative electrode of diode D1 connects clock line, and the negative electrode of diode D2 connects an output terminal of code translator.
6. according to a plurality of management methods with identical I2C address slave of the access described in claim 4 or 5, it is characterized in that, described code translator is 3-8 line code translator or 4-16 line code translator.
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Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105187899A (en) * | 2015-07-22 | 2015-12-23 | 深圳市特博赛科技有限公司 | Data transmission system |
| CN105677599A (en) * | 2014-11-19 | 2016-06-15 | 中兴通讯股份有限公司 | Host and method and system for managing slaves by host |
| CN106168934A (en) * | 2016-06-29 | 2016-11-30 | 锐捷网络股份有限公司 | A kind of data transmission method and device |
| CN106953939A (en) * | 2017-04-07 | 2017-07-14 | 上海电气集团股份有限公司 | The system and method for the automatic distribution of the mailing address from node of industrial bus |
| CN108093492A (en) * | 2017-12-26 | 2018-05-29 | 上海创程车联网络科技有限公司 | A kind of wireless radio frequency modules serial communication method for remote control equipment |
| CN108255760A (en) * | 2017-12-25 | 2018-07-06 | 北京摩高科技有限公司 | A kind of multipath I 2 C system and data read-write method |
| CN111124963A (en) * | 2019-12-09 | 2020-05-08 | 深圳震有科技股份有限公司 | Method for realizing IIC interface slave equipment by CPLD, intelligent terminal and storage medium |
| CN111352879A (en) * | 2018-12-24 | 2020-06-30 | 沈阳新松机器人自动化股份有限公司 | Same-address slave machine expansion circuit and method based on multi-path gating |
| CN111444127A (en) * | 2020-02-26 | 2020-07-24 | 中国电子科技集团公司第二十八研究所 | Data external memory expansion interface |
| CN111625491A (en) * | 2020-06-29 | 2020-09-04 | 科华恒盛股份有限公司 | Multi-machine serial communication device and method |
| CN112988635A (en) * | 2021-03-10 | 2021-06-18 | 英业达科技有限公司 | Communication system of mainboard and backplate and server that is suitable for thereof |
| CN113032321A (en) * | 2021-05-27 | 2021-06-25 | 上海亿存芯半导体有限公司 | Address extension circuit, communication interface chip and communication system |
| CN116166594A (en) * | 2023-04-26 | 2023-05-26 | 闪极科技(深圳)有限公司 | IIC bus circuit of single-address multi-slave machine and transmission method and device thereof |
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| CN1731383A (en) * | 2005-08-29 | 2006-02-08 | 杭州华为三康技术有限公司 | A system and method for equipment management |
| CN101000488A (en) * | 2006-01-12 | 2007-07-18 | 三星电子株式会社 | Apparatus to recognize memory devices |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105677599A (en) * | 2014-11-19 | 2016-06-15 | 中兴通讯股份有限公司 | Host and method and system for managing slaves by host |
| CN105187899A (en) * | 2015-07-22 | 2015-12-23 | 深圳市特博赛科技有限公司 | Data transmission system |
| CN105187899B (en) * | 2015-07-22 | 2018-06-29 | 深圳市特博赛科技有限公司 | Data transmission system |
| CN106168934A (en) * | 2016-06-29 | 2016-11-30 | 锐捷网络股份有限公司 | A kind of data transmission method and device |
| CN106168934B (en) * | 2016-06-29 | 2018-12-14 | 锐捷网络股份有限公司 | A kind of data transmission method and device |
| CN106953939A (en) * | 2017-04-07 | 2017-07-14 | 上海电气集团股份有限公司 | The system and method for the automatic distribution of the mailing address from node of industrial bus |
| CN108255760A (en) * | 2017-12-25 | 2018-07-06 | 北京摩高科技有限公司 | A kind of multipath I 2 C system and data read-write method |
| CN108093492A (en) * | 2017-12-26 | 2018-05-29 | 上海创程车联网络科技有限公司 | A kind of wireless radio frequency modules serial communication method for remote control equipment |
| CN111352879A (en) * | 2018-12-24 | 2020-06-30 | 沈阳新松机器人自动化股份有限公司 | Same-address slave machine expansion circuit and method based on multi-path gating |
| CN111124963A (en) * | 2019-12-09 | 2020-05-08 | 深圳震有科技股份有限公司 | Method for realizing IIC interface slave equipment by CPLD, intelligent terminal and storage medium |
| CN111444127A (en) * | 2020-02-26 | 2020-07-24 | 中国电子科技集团公司第二十八研究所 | Data external memory expansion interface |
| CN111625491A (en) * | 2020-06-29 | 2020-09-04 | 科华恒盛股份有限公司 | Multi-machine serial communication device and method |
| CN112988635A (en) * | 2021-03-10 | 2021-06-18 | 英业达科技有限公司 | Communication system of mainboard and backplate and server that is suitable for thereof |
| CN113032321A (en) * | 2021-05-27 | 2021-06-25 | 上海亿存芯半导体有限公司 | Address extension circuit, communication interface chip and communication system |
| CN116166594A (en) * | 2023-04-26 | 2023-05-26 | 闪极科技(深圳)有限公司 | IIC bus circuit of single-address multi-slave machine and transmission method and device thereof |
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Application publication date: 20140122 |
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