CN111123066A - Chip test circuit, memory and wafer - Google Patents
Chip test circuit, memory and wafer Download PDFInfo
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- CN111123066A CN111123066A CN201811280386.0A CN201811280386A CN111123066A CN 111123066 A CN111123066 A CN 111123066A CN 201811280386 A CN201811280386 A CN 201811280386A CN 111123066 A CN111123066 A CN 111123066A
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
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- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
The present disclosure relates to a chip test circuit, a memory and a wafer, the chip test circuit provided in the embodiment of the present disclosure includes: a test signal interface for receiving a test signal; one end of the first electrostatic protection circuit is connected with the test signal interface; and a first input end of the signal selection circuit is connected with the other end of the first electrostatic protection circuit, a second input end of the signal selection circuit is used for receiving a working signal, a control end of the signal selection circuit is used for receiving a characteristic signal related to the test signal, and an output end of the signal selection circuit is used for outputting the test signal or the working signal to a chip to be tested. The chip test circuit provided by the embodiment of the disclosure can obtain a test result closer to the normal working state of a chip, improves the reliability of the test result of the chip, and further can improve the yield in the production and processing of the chip.
Description
Technical Field
The present disclosure relates to the field of integrated circuit technologies, and in particular, to a chip test circuit, a memory, and a wafer.
Background
In the production and processing of chips, multiple testing processes are generally involved, for example, before a wafer is cut, preliminary testing of the working electrical characteristics of each chip on the wafer is required, and whether the chip can work normally or meets a specified standard is detected. The Test is usually performed on Automatic Test Equipment (ATE), and the ATE clock is often multiplied by a frequency multiplier circuit and then provides a high-frequency clock to the inside of the chip for testing. In the existing test scheme, a test signal in a test mode directly enters a chip to be tested, which is different from a transmission path of a working signal in a working mode, so that a large error is generated between a test result and an actual working result.
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
The present disclosure is directed to a chip test circuit, a memory and a wafer, so as to overcome, at least to some extent, the technical problem of poor reliability of chip test results due to the limitations of the related art.
According to one aspect of the present disclosure, there is provided a chip test circuit, characterized by comprising:
a test signal interface for receiving a test signal;
one end of the first electrostatic protection circuit is connected with the test signal interface;
and a first input end of the signal selection circuit is connected with the other end of the first electrostatic protection circuit, a second input end of the signal selection circuit is used for receiving a working signal, a control end of the signal selection circuit is used for receiving a characteristic signal related to the test signal, and an output end of the signal selection circuit is used for outputting the test signal or the working signal to a chip to be tested.
In an exemplary embodiment of the present disclosure, the chip test circuit further includes:
the working signal interface is used for receiving the working signal;
one end of the second electrostatic protection circuit is connected with the working signal interface, and the other end of the second electrostatic protection circuit is connected with the second input end of the signal selection circuit;
the first electrostatic protection circuit and the second electrostatic protection circuit have the same circuit structure.
In an exemplary embodiment of the present disclosure, the signal selection circuit includes:
a first switch element, a first pole of which is connected with a first input end of the signal selection circuit, a second pole of which is connected with an output end of the signal selection circuit, and a grid of which is connected with a control end of the signal selection circuit;
a first pole of the second switch element is connected with the second input end of the signal selection circuit, a second pole of the second switch element is connected with the output end of the signal selection circuit, and a grid of the second switch element is connected with the control end of the signal selection circuit through an inverter;
wherein the first switching element and the second switching element have the same switching driving condition.
In an exemplary embodiment of the present disclosure, the signal selection circuit includes:
a first pole of the third switching element is connected with the first input end of the signal selection circuit, a second pole of the third switching element is connected with the output end of the signal selection circuit, and a grid of the third switching element is connected with the control end of the signal selection circuit;
a first pole of the fourth switching element is connected with the second input end of the signal selection circuit, a second pole of the fourth switching element is connected with the output end of the signal selection circuit, and a grid of the fourth switching element is connected with the control end of the signal selection circuit;
wherein the third switching element and the fourth switching element have opposite switching drive conditions.
In an exemplary embodiment of the present disclosure, the signal selection circuit further includes:
and the level shifter is used for adjusting the voltage value of the characteristic signal received by the control end.
In an exemplary embodiment of the present disclosure, the test signal interface includes a test pad of the chip to be tested, and the operation signal interface includes a lead pad of the chip to be tested.
In an exemplary embodiment of the present disclosure, the first electrostatic protection circuit includes:
an intermediate node for connecting the test signal interface and the signal selection circuit;
the anode of the first diode is connected with the intermediate node, and the cathode of the first diode is connected with a first voltage end;
and the anode of the second diode is connected with the second voltage end, and the cathode of the second diode is connected with the middle node.
In an exemplary embodiment of the present disclosure, the first electrostatic protection circuit further includes:
a ballast resistor on a connection path of the intermediate node and the signal selection circuit.
In an exemplary embodiment of the present disclosure, the first voltage terminal is connected to an operating voltage of the chip to be tested, and the second voltage terminal is connected to a ground voltage.
According to one aspect of the present disclosure, there is provided a memory characterized by comprising a chip test circuit as described in any one of the above.
According to one aspect of the present disclosure, a wafer is provided, which is characterized by comprising a plurality of chips to be tested and a chip test circuit corresponding to the chips to be tested.
The chip test circuit provided by the embodiment of the disclosure changes the circuit structure that the test signal directly enters the chip to be tested in the related technology, so that the test signal can obtain the signal communication path which is the same as or close to the working signal of the chip to be tested. Under the condition that the two signal traversal circuit structures are the same or similar, the test result which is closer to the normal working state of the chip can be naturally obtained, the reliability of the test result of the chip is improved, and the yield in the production and processing of the chip can be further improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.
Fig. 1 is a schematic circuit diagram of a chip test circuit according to an exemplary embodiment of the disclosure.
Fig. 2 is a schematic circuit diagram of a signal selection circuit according to an exemplary embodiment of the disclosure.
Fig. 3 is a schematic circuit diagram of a signal selection circuit according to another exemplary embodiment of the disclosure.
Fig. 4 is a schematic circuit diagram of a first esd protection circuit according to another exemplary embodiment of the disclosure.
The reference numerals are explained below:
11-test signal interface;
12-a first electrostatic protection circuit;
13-a signal selection circuit;
14-a chip to be tested;
15-working signal interface;
16-a second electrostatic protection circuit;
21-a first switching element;
22-a second switching element;
23-an inverter;
24-a level shifter;
31-a third switching element;
32-a fourth switching element;
41-intermediate node;
42-a first diode;
43-a first voltage terminal;
44-a second diode;
45-a second voltage terminal;
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.
Although relative terms, such as "upper" and "lower," may be used in this specification to describe one element of an icon relative to another, these terms are used in this specification for convenience only, e.g., in accordance with the orientation of the examples described in the figures. It will be appreciated that if the device of the icon were turned upside down, the element described as "upper" would become the element "lower". When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.
The terms "a," "an," "the," "said," and "at least one" are used to indicate the presence of one or more elements/components/parts/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.; the terms "first," "second," and "third," etc. are used merely as labels, and are not limiting on the number of their objects.
In an exemplary embodiment of the present disclosure, a chip test Circuit is provided, where the Circuit is mainly used to perform a preliminary test on the working electrical characteristics of a chip, for example, the Circuit may be used to perform a wafer level test (CP test) before a wafer is diced, and may also be used to perform other tests in a chip production process.
As shown in fig. 1, the chip test circuit provided in the present exemplary embodiment may mainly include: a test signal interface 11, a first electrostatic protection circuit 12 and a signal selection circuit 13.
The test signal interface 11 is used for receiving a test signal, such as a test clock signal CLKTM。
One end of the first electrostatic protection circuit 12 is connected to the test signal interface 11, and is used for providing electrostatic protection for the chip to be tested on the transmission path of the test signal.
The signal selection circuit 13 has a first input end connected to the other end of the first electrostatic protection circuit 12, a second input end for receiving a working signal, a control end for receiving a characteristic signal related to the test signal, and an output end for outputting the test signal or the working signal to the chip 14 to be tested. And a test clock signal CLKTMCorrespondingly, the working signal may be a normal clock signal CLK of the chip to be tested in a normal working mode, and the characteristic signal may be a clock signal CLK corresponding to the test clock signalTMAn associated characteristic clock signal TMCLKG.
The signal selection circuit 13 may control the gating of the test signal and the working signal according to the characteristic signal received by the control terminal, so as to select to output the test signal or the working signal to the chip 14 to be tested.
The chip test circuit provided by the exemplary embodiment changes a circuit structure that a test signal directly enters a chip to be tested in the related art, so that the test signal can obtain a signal communication path which is the same as or close to a working signal of the chip to be tested. Under the condition that the two signal traversal circuit structures are the same or similar, the test result which is closer to the normal working state of the chip can be naturally obtained, the reliability of the test result of the chip is improved, and the yield in the production and processing of the chip can be further improved.
With continued reference to fig. 1, the chip test circuit provided by the present exemplary embodiment may further include: an operating signal interface 15 and a second electrostatic protection circuit 16.
The working signal interface 15 is used for receiving the working signal, and may be a conventional clock signal CLK, for example.
One end of the second electrostatic protection circuit 16 is connected to the working signal interface 15, the other end of the second electrostatic protection circuit 16 is connected to the second input end of the signal selection circuit 13, and the second electrostatic protection circuit 16 is configured to provide electrostatic protection for the chip to be tested on the transmission path of the working signal.
The first electrostatic protection circuit 12 on the test signal transmission path and the second electrostatic protection circuit 16 on the working signal transmission path have the same circuit structure, so that the test signal and the working signal can have the same traversal circuit structure, and the accuracy of the test result is further improved.
As shown in fig. 2, on the basis of the above exemplary embodiment, the signal selection circuit 13 may further include: a first switching element 21 and a second switching element 22.
The first switch element 21 has a first pole connected to the first input terminal of the signal selection circuit, a second pole connected to the output terminal of the signal selection circuit, and a gate connected to the control terminal of the signal selection circuit.
The second switching element 22 has a first pole connected to the second input terminal of the signal selection circuit, a second pole connected to the output terminal of the signal selection circuit, and a gate connected to the control terminal of the signal selection circuit through an inverter 23.
In the present exemplary embodiment, the first switching element 21 and the second switching element 22 have the same switching drive condition. For example, the first switch element 21 and the second switch element 22 may be NMOS transistors. Based on the same characteristic signal, under the action of the inverter 23, when the first switching element 21 is in the on state, the second switching element 22 is turned off, and when the first switching element 21 is in the off state, the second switching element 22 is turned on, so that selective conduction of the test signal or the operation signal can be realized.
In addition, as shown in fig. 2, the signal selection circuit 13 may further include a level shifter 24 for adjusting a voltage value of the characteristic signal received by the control terminal of the signal selection circuit 13 so as to smoothly turn on or off the corresponding switching element.
In the exemplary embodiment, the signal selection circuit is formed by using the switching elements on the transmission paths of the test signal and the working signal, so that the gating control of the two signals can be realized without remarkably increasing the chip area, the two signals can be ensured to traverse almost the same circuit structure, and the reliability of the test result is improved.
As shown in fig. 3, in another exemplary embodiment, the signal selection circuit 13 may include: a third switching element 31 and a fourth switching element 32.
The third switching element 31 has a first pole connected to the first input terminal of the signal selection circuit, a second pole connected to the output terminal of the signal selection circuit, and a gate connected to the control terminal of the signal selection circuit.
A first pole of the fourth switching element 32 is connected to the second input terminal of the signal selection circuit, a second pole is connected to the output terminal of the signal selection circuit, and a gate is connected to the control terminal of the signal selection circuit.
In the present exemplary embodiment, the third switching element 31 and the fourth switching element 32 have opposite switching drive conditions. For example, the third switching element 31 may be an NMOS transistor, and the fourth switching element 32 may be a PMOS transistor. Based on the same characteristic signal, when the third switching element 31 is in an on state, the fourth switching element 32 is turned off, and when the third switching element 31 is in an off state, the fourth switching element 32 is turned on, so that selective conduction of the test signal or the operation signal can be achieved.
In addition, the signal selection circuit 13 may also select a multiplexer or other electronic elements or circuit units capable of implementing the signal gating function as required, which is not limited in this disclosure.
In another exemplary embodiment of the present disclosure, the test signal interface 11 of the chip test circuit may include a test pad (test pad) of the chip to be tested, and the operation signal interface 15 may include a lead pad (bondpad) of the chip to be tested. For example, in a wafer level test before dicing the wafer, the test pads may be distributed on the scribe lines of the wafer and discarded after the test is completed.
As shown in fig. 4, in another exemplary embodiment of the present disclosure, the first electrostatic protection circuit 12 includes: an intermediate node 41, a first diode 42 and a second diode 44.
The intermediate node 41 is used to connect the test signal interface 11 and the signal selection circuit 13.
The anode of the first diode 42 is connected to the intermediate node 41, the cathode is connected to the first voltage terminal 43, and the first voltage terminal 43 can be connected to the operating voltage VDD of the chip to be tested.
The anode of the second diode 44 is connected to the second voltage terminal 45, the cathode is connected to the intermediate node 41, and the second voltage terminal 45 is connected to the ground voltage.
In addition, the first electrostatic protection circuit 12 may further include a ballast resistor 46, and the ballast resistor 46 is located on the connection path between the intermediate node 41 and the signal selection circuit 13, and may form an RC filter with a parasitic capacitor in a rear circuit, so that the voltage variation on the connection path tends to be smooth.
On the basis of the above exemplary embodiments, the present disclosure also provides a Memory, which may be, for example, a Dynamic Random Access Memory (DRAM). The chip test circuit portion of the memory has been described in detail in the above exemplary embodiments, and thus is not described herein again.
On the basis of the above exemplary embodiments, the present disclosure also provides a wafer including a plurality of chips to be tested and chip test circuits corresponding to the chips to be tested. The chip test circuit portion of the wafer has been described in detail in the above exemplary embodiments, and therefore, the description thereof is omitted here.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
Claims (11)
1. A chip test circuit, comprising:
a test signal interface for receiving a test signal;
one end of the first electrostatic protection circuit is connected with the test signal interface;
and a first input end of the signal selection circuit is connected with the other end of the first electrostatic protection circuit, a second input end of the signal selection circuit is used for receiving a working signal, a control end of the signal selection circuit is used for receiving a characteristic signal related to the test signal, and an output end of the signal selection circuit is used for outputting the test signal or the working signal to a chip to be tested.
2. The chip test circuit according to claim 1, further comprising:
the working signal interface is used for receiving the working signal;
one end of the second electrostatic protection circuit is connected with the working signal interface, and the other end of the second electrostatic protection circuit is connected with the second input end of the signal selection circuit;
the first electrostatic protection circuit and the second electrostatic protection circuit have the same circuit structure.
3. The chip test circuit according to claim 1, wherein the signal selection circuit comprises:
a first switch element, a first pole of which is connected with a first input end of the signal selection circuit, a second pole of which is connected with an output end of the signal selection circuit, and a grid of which is connected with a control end of the signal selection circuit;
a first pole of the second switch element is connected with the second input end of the signal selection circuit, a second pole of the second switch element is connected with the output end of the signal selection circuit, and a grid of the second switch element is connected with the control end of the signal selection circuit through an inverter;
wherein the first switching element and the second switching element have the same switching driving condition.
4. The chip test circuit according to claim 1, wherein the signal selection circuit comprises:
a first pole of the third switching element is connected with the first input end of the signal selection circuit, a second pole of the third switching element is connected with the output end of the signal selection circuit, and a grid of the third switching element is connected with the control end of the signal selection circuit;
a first pole of the fourth switching element is connected with the second input end of the signal selection circuit, a second pole of the fourth switching element is connected with the output end of the signal selection circuit, and a grid of the fourth switching element is connected with the control end of the signal selection circuit;
wherein the third switching element and the fourth switching element have opposite switching drive conditions.
5. The chip test circuit according to claim 3 or 4, wherein the signal selection circuit further comprises:
and the level shifter is used for adjusting the voltage value of the characteristic signal received by the control end.
6. The chip test circuit according to claim 2, wherein the test signal interface comprises a test pad of the chip to be tested, and the operation signal interface comprises a lead pad of the chip to be tested.
7. The chip test circuit according to claim 1, wherein the first electrostatic discharge protection circuit comprises:
an intermediate node for connecting the test signal interface and the signal selection circuit;
the anode of the first diode is connected with the intermediate node, and the cathode of the first diode is connected with a first voltage end;
and the anode of the second diode is connected with the second voltage end, and the cathode of the second diode is connected with the middle node.
8. The chip test circuit according to claim 7, wherein the first electrostatic discharge protection circuit further comprises:
a ballast resistor on a connection path of the intermediate node and the signal selection circuit.
9. The chip test circuit according to claim 7, wherein the first voltage terminal is connected to an operating voltage of the chip to be tested, and the second voltage terminal is connected to a ground voltage.
10. A memory comprising a chip test circuit according to any one of claims 1 to 9.
11. A wafer comprising a plurality of chips to be tested and the chip test circuit of any one of claims 1-9 corresponding to the chips to be tested.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811280386.0A CN111123066A (en) | 2018-10-30 | 2018-10-30 | Chip test circuit, memory and wafer |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811280386.0A CN111123066A (en) | 2018-10-30 | 2018-10-30 | Chip test circuit, memory and wafer |
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| CN111123066A true CN111123066A (en) | 2020-05-08 |
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| CN201811280386.0A Pending CN111123066A (en) | 2018-10-30 | 2018-10-30 | Chip test circuit, memory and wafer |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111965512A (en) * | 2020-07-28 | 2020-11-20 | 广西大学 | Reliability test system and method for ultraviolet light-emitting device and storage medium |
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2018
- 2018-10-30 CN CN201811280386.0A patent/CN111123066A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111965512A (en) * | 2020-07-28 | 2020-11-20 | 广西大学 | Reliability test system and method for ultraviolet light-emitting device and storage medium |
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