CN113764410B - Semiconductor unit device - Google Patents

Semiconductor unit device Download PDF

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Publication number
CN113764410B
CN113764410B CN202010501168.6A CN202010501168A CN113764410B CN 113764410 B CN113764410 B CN 113764410B CN 202010501168 A CN202010501168 A CN 202010501168A CN 113764410 B CN113764410 B CN 113764410B
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interconnection line
metal interconnection
configurable
metal
active region
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CN113764410A (en
Inventor
李卿
刘红霞
曹鹏辉
黄高中
徐烈伟
俞军
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Shanghai Fudan Microelectronics Group Co Ltd
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Shanghai Fudan Microelectronics Group Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76892—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances modifying the pattern
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

A semiconductor cell device comprising: the power supply device comprises a power supply region, a PMOS tube, an NMOS tube, a grounding region, an output end and a metal connecting layer, wherein the metal connecting layer comprises a first metal interconnecting wire and a second metal interconnecting wire, the source electrode of the PMOS tube is coupled with the power supply region, and the grid electrode is coupled with the first metal interconnecting wire; the source electrode of the NMOS tube is coupled with the grounding area, and the grid electrode of the NMOS tube is coupled with the first metal interconnection line; the output end is coupled with the second metal interconnection line; a configurable first via structure is disposed on the first metal interconnect line to connect the first metal interconnect line to the selected first object; the second metal interconnection line is provided with a configurable second through hole structure so as to connect the second metal interconnection line with a selected second object, so that the second object is conducted with the output end. According to the scheme, when the output logic of the semiconductor unit device is required to be changed after the film is formed, ECO winding is not needed, so that the change of the output logic of the semiconductor unit device can be realized, and the ECO cost can be reduced.

Description

Semiconductor unit device
Technical Field
The embodiment of the invention relates to the field of semiconductors, in particular to a semiconductor unit device.
Background
There is often some fixed logic code inside the chip, such as a Read Only Memory (ROM) self-test (Buil In Self Test, BIST) check code, device ID number, version information, etc. These fixed logic encodings map RTL 1'b1/1' b0 to standard Cell libraries by tools for outputting 1'b1 High level logic cells (TIE High Cell, TIEHI) or for outputting 1' b0 Low level logic cells (TIE Low Cell, TIELO).
Typically, these codes will have many intermediate versions that cannot be finalized until the slice is streamed. In the existing TIEHI/TIELO unit, because the positions of the pins of the rear-end layout are different, after the front-end engineer changes the logic, the rear-end engineer is required to perform engineering change order (Engineering Change Order, ECO) winding to complete the whole replacement work. Meanwhile, because the layout of the standard cell library TIEHI/TIELO cells is not compatible, if logic needs to be changed again after the streaming, the ECO cost is high.
Disclosure of Invention
The technical problem solved by the embodiment of the invention is that logic needs to be changed again after the streaming, and ECO cost is high.
To solve the above technical problem, an embodiment of the present invention provides a semiconductor unit device, including: the PMOS transistor comprises a power supply region, a PMOS transistor, an NMOS transistor, a grounding region, an output end and a metal connecting layer, wherein the metal connecting layer comprises a first metal interconnecting wire and a second metal interconnecting wire, a source electrode of the PMOS transistor is coupled with the power supply region, and a grid electrode of the PMOS transistor is coupled with the first metal interconnecting wire; the source electrode of the NMOS tube is coupled with the grounding region, and the grid electrode of the NMOS tube is coupled with the first metal interconnection line; the output end is coupled with the second metal interconnection line; the first metal interconnection line is provided with a configurable first through hole structure, and the position of the configurable first through hole structure is configurable to connect the first metal interconnection line to a selected first object; the second metal interconnection line is provided with a configurable second through hole structure, and the position of the configurable second through hole structure is configurable, so that the second metal interconnection line is connected to a selected second object, and the second object is conducted with the output end, wherein the first object is one of the drain electrode of the PMOS tube and the drain electrode of the NMOS tube, and the second object is the other of the drain electrode of the PMOS tube and the drain electrode of the NMOS tube.
Optionally, the PMOS active region corresponding to the PMOS is located between the power supply region and the NMOS active region corresponding to the NMOS; the NMOS tube active region is positioned between the PMOS tube active region and the grounding region; the grid electrode of the PMOS tube divides the PMOS tube active region into a first PMOS tube active region 321 and a second PMOS tube active region; the grid electrode of the NMOS tube divides the NMOS tube active region into a first NMOS tube active region and a second NMOS tube active region; the first end of the first metal interconnection line is positioned above the first active region of the PMOS tube, and the second end of the first metal interconnection line is positioned above the first active region of the NMOS tube; the first end of the second metal interconnection line is located above the second active region of the PMOS tube, and the second end of the second metal interconnection line is located above the second active region of the NMOS tube.
Optionally, the semiconductor unit device further includes: gate portion and fifth via structure, wherein: the first end of the grid part is used as the grid of the PMOS tube, and the second end of the grid part is used as the grid of the NMOS tube; the metal connection layer further comprises a seventh metal interconnection line, a first end of the seventh metal interconnection line is coupled with the first metal interconnection line, and a second end of the seventh metal interconnection line is connected with the grid part; the fifth through hole structure is arranged at the second end of the seventh metal interconnection line so as to conduct the grid electrode of the PMOS tube and the grid electrode of the NMOS tube with the first metal interconnection line.
Optionally, the configurable first via structure is disposed at the second end of the first metal interconnection line, the first active area of the NMOS transistor is in conduction with the gate of the PMOS transistor, and the first active area of the NMOS transistor is used as the drain of the NMOS transistor; the configurable second through hole structure is arranged at the first end of the second metal interconnection line, the second active region of the PMOS tube is conducted with the second metal interconnection line, and the second active region of the PMOS tube is used as the drain electrode of the PMOS tube.
Optionally, the semiconductor unit device further includes: a configurable third via structure, a configurable fourth via structure, the metal connection layer further comprising: a third metal interconnection line, a fourth metal interconnection line, a fifth metal interconnection line, a sixth metal interconnection line, wherein: the first end of the third metal interconnection line is positioned above the power supply region, and the second end of the third metal interconnection line is positioned above the first active region of the PMOS tube; the first end of the fourth metal interconnection line is positioned above the power supply region, and the second end of the fourth metal interconnection line is positioned above the second active region of the PMOS tube; the first end of the fifth metal interconnection line is positioned above the first active region of the NMOS tube, and the second end of the fifth metal interconnection line is positioned above the grounding region; the first end of the sixth metal interconnection line is located above the second active region of the NMOS tube, and the second end of the sixth metal interconnection line is located above the grounding region; the position of the configurable third through hole structure is configurable, and the configurable third through hole structure is arranged at the second end of the third metal interconnection line; the position of the configurable fourth via structure is configurable, and the configurable fourth via structure is arranged at the first end of the sixth metal interconnection line.
Optionally, the first configurable via structure is disposed at a first end of the first metal interconnection line, the first active region of the PMOS transistor is in conduction with the gate of the NMOS transistor, and the first active region of the PMOS transistor is used as the drain of the PMOS transistor; the configurable second through hole structure is arranged at the second end of the second metal interconnection line, the second active region of the NMOS tube is communicated with the second metal interconnection line, and the second active region of the NMOS tube is used as the drain electrode of the NMOS tube.
Optionally, the metal connection layer further includes: a third metal interconnect line, a fourth metal interconnect line, a fifth metal interconnect line, a sixth metal interconnect line, a configurable third via structure, a configurable fourth via structure, wherein: the first end of the third metal interconnection line is positioned above the power supply region, and the second end of the third metal interconnection line is positioned above the first active region of the PMOS tube; the first end of the fourth metal interconnection line is positioned above the power supply region, and the second end of the fourth metal interconnection line is positioned above the second active region of the PMOS tube; the first end of the fifth metal interconnection line is positioned above the first active region of the NMOS tube, and the second end of the fifth metal interconnection line is positioned above the grounding region; the first end of the sixth metal interconnection line is located above the second active region of the NMOS tube, and the second end of the sixth metal interconnection line is located above the grounding region; the position of the configurable third through hole structure is configurable, and the configurable third through hole structure is arranged at the second end of the fourth metal interconnection line; the position of the configurable fourth via structure is configurable, and the configurable fourth via structure is arranged at the first end of the fifth metal interconnection line.
The embodiment of the invention also provides another semiconductor unit device, which comprises: high level output unit, low level output unit and metal interconnect line, wherein: the metal interconnect lines are provided with configurable via structures whose locations are configurable to connect the metal interconnect lines to a selected object.
Optionally, the configurable via structure is configured to conduct the metal interconnection line with the high-level output unit, or conduct the metal interconnection line with the low-level output unit.
Optionally, the high-level output unit and the low-level output unit are formed on a first metal layer, and the metal interconnection line is formed on a second metal layer.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
the semiconductor unit device includes: the power supply comprises a power supply region, a PMOS tube, an NMOS tube, a grounding region, an output end and a metal connecting layer, wherein the source electrode of the PMOS tube is coupled with the power supply region, the grid electrode of the PMOS tube is coupled with a first metal interconnection line, the source electrode of the NMOS tube is coupled with the grounding region, the grid electrode of the NMOS tube is coupled with the first metal interconnection line, the output end is coupled with a second metal interconnection line, a configurable first through hole structure is arranged on the first metal interconnection line, and a configurable second through hole structure is arranged on the second metal interconnection line. The positions of the first through hole structure and the second through hole structure can be configured, the first metal interconnection line can be connected to a selected first object, the second metal interconnection line can be connected to a second object by configuring the positions of the first through hole structure and the second through hole structure, the first object is one of the drain electrode of the PMOS tube and the drain electrode of the NMOS tube, and the second object is the other of the drain electrode of the PMOS tube and the drain electrode of the NMOS tube. The positions of the first through hole structure and the second through hole structure are configured to adjust the connection object of the first metal interconnection line and the connection object of the second metal interconnection line, and the output logic of the semiconductor unit device is different due to the fact that the connection objects of the first metal interconnection line and the second metal interconnection line are different. Therefore, when the output logic of the semiconductor unit device needs to be changed after the wafer is flowed, the change of the output logic function of the semiconductor unit device can be realized only by modifying the layout of the metal connecting layer to adjust the configuration positions of the first through hole structure and the second through hole structure, namely, only one photomask layer is required to be modified, and the positions of the configurable first through hole structure and the second through hole structure are adjusted, so that the change of the output logic of the semiconductor unit device can be realized, and the ECO winding is not required because the output ends are compatible, thereby the ECO cost is lower.
Drawings
FIG. 1 is a schematic diagram of a prior art TIEHI unit;
FIG. 2 is a schematic diagram of a TIELO unit of the prior art;
fig. 3 is a schematic structural view of a semiconductor unit device in an embodiment of the present invention;
fig. 4 is a circuit diagram corresponding to the semiconductor unit device shown in fig. 3;
fig. 5 is a schematic structural view of another semiconductor unit device in an embodiment of the present invention;
fig. 6 is a circuit diagram corresponding to the semiconductor unit device shown in fig. 5;
fig. 7 is a schematic structural view of yet another semiconductor unit device in an embodiment of the present invention;
fig. 8 is a schematic structural view of still another semiconductor unit device in an embodiment of the present invention.
Detailed Description
As described above, referring to fig. 1, a schematic structural diagram of a TIEHI unit in the prior art is given, referring to fig. 2, a schematic structural diagram of a TIELO unit in the prior art is given, where the output pin position of the conventional TIEHI unit is a, as shown in fig. 1, and the output pin position of the TIELO unit is B, as shown in fig. 2. After the front-end engineer changes the logic, the tail-end engineer ECO winding is needed to complete the whole replacement work because the positions of pins of the rear-end layout TIEHI unit and the TIELO unit are different. Meanwhile, because the layouts of the standard cell library TIEHI cell and the TIELO cell are incompatible, for example, a connection layer, a Metal1 or other layers are incompatible, if logic needs to be changed again after the streaming, the ECO cost is higher.
In an embodiment of the present invention, a semiconductor unit device includes: the power supply comprises a power supply region, a PMOS tube, an NMOS tube, a grounding region, an output end and a metal connecting layer, wherein the source electrode of the PMOS tube is coupled with the power supply region, the grid electrode of the PMOS tube is coupled with a first metal interconnection line, the source electrode of the NMOS tube is coupled with the grounding region, the grid electrode of the NMOS tube is coupled with the first metal interconnection line, the output end is coupled with a second metal interconnection line, a configurable first through hole structure is arranged on the first metal interconnection line, and a configurable second through hole structure is arranged on the second metal interconnection line. The positions of the first through hole structure and the second through hole structure can be configured, the first metal interconnection line can be connected to a selected first object, the second metal interconnection line can be connected to a second object by configuring the positions of the first through hole structure and the second through hole structure, the first object is one of the drain electrode of the PMOS tube and the drain electrode of the NMOS tube, and the second object is the other of the drain electrode of the PMOS tube and the drain electrode of the NMOS tube. The positions of the first through hole structure and the second through hole structure are configured to adjust the connection object of the first metal interconnection line and the connection object of the second metal interconnection line, and the output logic of the semiconductor unit device is different due to the fact that the connection objects of the first metal interconnection line and the second metal interconnection line are different. Therefore, when the output logic of the semiconductor unit device needs to be changed after the wafer is flowed, the change of the output logic function of the semiconductor unit device can be realized only by modifying the layout of the metal connecting layer to adjust the configuration positions of the first through hole structure and the second through hole structure, namely, only one photomask layer is required to be modified, and the positions of the configurable first through hole structure and the second through hole structure are adjusted, so that the change of the output logic of the semiconductor unit device can be realized, and the ECO winding is not required because the output ends are compatible, thereby the ECO cost is lower.
In order to make the above objects, features and advantages of the embodiments of the present invention more comprehensible, the following detailed description of the embodiments of the present invention refers to the accompanying drawings.
Referring to fig. 3, a schematic structural diagram of a semiconductor unit device according to an embodiment of the present invention is provided, and fig. 4 is a circuit diagram corresponding to the semiconductor unit device provided in fig. 3. Referring to fig. 5, a schematic structural diagram of another semiconductor unit device in an embodiment of the present invention is given. Fig. 6 is a circuit diagram corresponding to the semiconductor unit device shown in fig. 5. The structure of the semiconductor unit device will be described below with reference to fig. 3 to 6.
In an implementation, the semiconductor unit device 30 may include: the power supply region 31 (VDD), PMOS transistor, NMOS transistor, ground region 35 (GND), output terminal 368, metal connection layer.
The metal connection layer may include a first metal interconnection line 361 and a second metal interconnection line 362.
The source of the PMOS transistor is coupled to the power region 31, and the gate of the PMOS transistor is coupled to the first metal interconnect 361.
The source of the NMOS transistor is coupled to the ground region 35, and the gate of the NMOS transistor is coupled to the first metal interconnect 361.
The output terminal 368 is coupled to the second metal interconnect 362.
The first metal interconnection line 361 is provided with a configurable first via structure 371, and the position of the configurable first via structure 371 is configurable, so that the first metal interconnection line 361 can be connected to a selected first object.
A second metal interconnect line 362 is provided with a configurable second via structure 372, where the configurable second via structure 372 is located and may connect the second metal interconnect line 362 to a selected second object such that the second object is in communication with the output 368.
The first object is one of the drain electrode of the PMOS tube and the drain electrode of the NMOS tube, and the second object is the other one of the drain electrode of the PMOS tube and the drain electrode of the NMOS tube.
In an embodiment of the present invention, the first metal interconnect 361 is connected to the drain of the NMOS transistor by configuring the position of the first via structure 371, and the second metal interconnect 362 is connected to the drain of the PMOS transistor by configuring the position of the second via structure 372, and the output terminal 368 (VOUT) outputs a high level.
In another embodiment of the present invention, the first metal interconnect 361 is connected to the drain of the PMOS transistor by configuring the position of the first via structure 371, and the second metal interconnect 362 is connected to the drain of the NMOS transistor by configuring the position of the second via structure 372, and the output terminal 368 (VOUT) outputs a low level.
As can be seen from the above, the semiconductor unit device includes: the power supply comprises a power supply region, a PMOS tube, an NMOS tube, a grounding region, an output end and a metal connecting layer, wherein the source electrode of the PMOS tube is coupled with the power supply region, the grid electrode of the PMOS tube is coupled with a first metal interconnection line, the source electrode of the NMOS tube is coupled with the grounding region, the grid electrode of the NMOS tube is coupled with the first metal interconnection line, the output end is coupled with a second metal interconnection line, a configurable first through hole structure is arranged on the first metal interconnection line, and a configurable second through hole structure is arranged on the second metal interconnection line. The positions of the first through hole structure and the second through hole structure can be configured, the first metal interconnection line can be connected to a selected first object, the second metal interconnection line can be connected to a second object by configuring the positions of the first through hole structure and the second through hole structure, the first object is one of the drain electrode of the PMOS tube and the drain electrode of the NMOS tube, and the second object is the other of the drain electrode of the PMOS tube and the drain electrode of the NMOS tube. The positions of the first through hole structure and the second through hole structure are configured to adjust the connection object of the first metal interconnection line and the connection object of the second metal interconnection line, and when the connection objects of the first metal interconnection line and the second metal interconnection line are different, the output logic of the semiconductor unit device is different. Therefore, when the output logic of the semiconductor unit device needs to be changed after the wafer is flowed, the change of the output logic function of the semiconductor unit device can be realized only by modifying the layout of the metal connecting layer to adjust the configuration positions of the first through hole structure and the second through hole structure, namely, only one photomask layer is required to be modified, and the positions of the configurable first through hole structure and the second through hole structure are adjusted, so that the change of the output logic of the semiconductor unit device can be realized, and the ECO winding is not required because the output ends are compatible, thereby reducing the ECO cost.
In a specific implementation, referring to fig. 3 and 5, the PMOS active region corresponding to the PMOS transistor is located between the power supply region 31 and the NMOS active region corresponding to the NMOS transistor. The NMOS transistor active region is located between the PMOS transistor active region and the ground region 35.
The gate of the PMOS transistor divides the PMOS transistor active region into a first PMOS transistor active region 321 and a second PMOS transistor active region 322. The gate of the NMOS transistor divides the NMOS transistor active region into a first NMOS transistor active region 331 and a second NMOS transistor active region 332.
A first end of the first metal interconnection line 361 is located above the PMOS first active region 321, and a second end of the first metal interconnection line 361 is located above the NMOS first active region 331.
A first end of the second metal interconnect 362 is located over the PMOS tube second active region 322, and a second end of the second metal interconnect 362 is located over the NMOS tube second active region 332.
In an embodiment of the present invention, referring to fig. 3, a configurable first via structure 371 is disposed at a second end of the first metal interconnection line 361, the NMOS first active region 331 is electrically connected to the gate of the PMOS, and the NMOS first active region 331 is used as a drain of the NMOS. The configurable second via structure 372 is disposed at the first end of the second metal interconnection line 362, the second active region 322 of the PMOS transistor is in conduction with the second metal interconnection line 362, and the second active region 322 of the PMOS transistor is used as the drain of the PMOS transistor, and the output terminal 368 outputs a high level.
In another embodiment of the present invention, referring to fig. 4, a configurable first via structure 371 is disposed at a first end of the first metal interconnection line 361, the PMOS first active region 321 is conducted with the gate of the NMOS, and the PMOS first active region 321 is used as the drain of the PMOS. The configurable second via structure 372 is disposed at the second end of the second metal interconnection line 362, the second NMOS transistor active region 332 is in conduction with the second metal interconnection line 362, and the second NMOS transistor active region 332 is used as the drain of the NMOS transistor, and the output terminal 368 outputs a low level.
In an implementation, the semiconductor unit device 30 may further include a gate portion and a fifth via structure 375. The first end 341 of the gate portion serves as a gate of the PMOS transistor, and the second end 342 of the gate portion serves as a gate of the NMOS transistor.
In a specific implementation, the metal connection layer may further include a seventh metal interconnection line 367, a first end of the seventh metal interconnection line 367 is coupled with the first metal interconnection line 361, and a second end of the seventh metal interconnection line 367 is connected with the gate portion; the fifth via structure 375 is disposed at the second end of the seventh metal interconnection line 367 to conduct the gate of the PMOS and the gate of the NMOS with the first metal interconnection line 361.
In an implementation, semiconductor cell device 30 may further include a configurable third via structure 373 and a configurable fourth via structure 374. The metal connection layer may further include: third metal interconnect 363, fourth metal interconnect 364, fifth metal interconnect 365, sixth metal interconnect 366.
The first end of the third metal interconnection 363 is located above the power region 31, and the second end of the third metal interconnection 363 is located above the first active region 321 of the PMOS transistor.
A first end of the fourth metal interconnect 364 is located above the power region 31, and a second end of the fourth metal interconnect 364 is located above the PMOS second active region 322.
A first end of the fifth metal interconnect line 365 is located above the NMOS transistor first active region 331, and a second end of the fifth metal interconnect line 365 is located above the ground region 35.
A first end of the sixth metal interconnect 366 is located above the NMOS transistor second active region 332, and a second end of the sixth metal interconnect 366 is located above the ground region 35.
The position of the configurable third via structure 373 is configurable and the position of the configurable fourth via structure 374 is configurable. When the arrangement position of the third via structure 373 and the arrangement position of the fourth via structure 374 are changed, the output logic of the semiconductor unit device 30 is different.
Referring to fig. 3, in an embodiment of the invention, the configurable third via structure 373 is disposed at the second end of the third metal interconnection line 363, so that the first active region 321 of the PMOS transistor is conducted with the third metal interconnection line 363, and the first end of the third metal interconnection line 363 is conducted with the power supply region 31, at this time, the first active region 321 of the PMOS transistor is used as the source of the PMOS transistor, and correspondingly, the second active region 322 of the PMOS transistor is used as the drain of the PMOS transistor. The configurable fourth via structure 374 is disposed at the first end of the sixth metal interconnection line 366, so that the second NMOS transistor active region 332 is electrically connected to the sixth metal interconnection line 366, and the second end of the sixth metal interconnection line 366 is electrically connected to the ground region 35, and at this time, the second NMOS transistor active region 332 serves as the source of the NMOS transistor, and correspondingly, the first NMOS transistor active region 331 serves as the drain of the NMOS transistor.
Referring to fig. 4, in another embodiment of the present invention, the configurable third via structure 373 is disposed at the second end of the fourth metal interconnection line 364, so that the PMOS second active region 322 is conducted with the fourth metal interconnection line 364, and the first end of the fourth metal interconnection line 364 is conducted with the power supply region 31, at this time, the PMOS second active region 322 is used as the source of the MPOS transistor, and correspondingly, the PMOS first active region 321 is used as the drain of the MPOS transistor. The configurable fourth via structure 374 is disposed at the first end of the fifth metal interconnect 365, so that the first active region 331 of the NMOS transistor is conducted with the fifth metal interconnect 365, and the second end of the fifth metal interconnect 365 is conducted with the ground region 35, and at this time, the first active region 331 of the NMOS transistor is used as the source of the NMOS transistor, and the second active region 332 of the NMOS transistor is used as the drain of the NMOS transistor.
In an embodiment of the present invention, the configurable first via structure 371, the configurable second via structure 372, the configurable third via structure 373, the configurable fourth via structure 374, and the fifth via structure 375 may each include a via and a conductive plug disposed within the via pair.
In the implementation, referring to fig. 3 and 4, when the output logic of the semiconductor unit device 30 is changed, the positions of the configurable first via structure 371, the configurable second via structure 372, the configurable third via structure 373 and the configurable fourth via structure 374 may be reconfigured by modifying one photomask layer or modifying the metal connection layer layout.
Specifically, when the output logic of the semiconductor unit device 30 is changed from the high level to the low level, the position of the configurable first via structure 371 is configured from the second end of the first metal interconnection line 361 to the first end of the first metal interconnection line 361, the position of the configurable second via structure 372 is configured from the first end of the second metal interconnection line 362 to the second end of the second metal interconnection line 362, the position of the configurable third via structure 373 is configured from the second end of the third metal interconnection line 363 to the second end of the fourth metal interconnection line 364, and the position of the configurable fourth via structure 374 is configured from the first end of the sixth metal interconnection line 366 to the first end of the fifth metal interconnection line 365, so that the output logic of the semiconductor unit device 30 can be adjusted from the high level to the low level.
Accordingly, when the output logic of the semiconductor unit device 30 is changed from the low level to the high level, the position of the configurable first via structure 371 is configured from the first end of the first metal interconnection line 361 to the second end of the first metal interconnection line 361, the position of the configurable second via structure 372 is configured from the second end of the second metal interconnection line 362 to the first end of the second metal interconnection line 362, the position of the configurable third via structure 373 is configured from the second end of the fourth metal interconnection line 364 to the second end of the third metal interconnection line 363, and the position of the configurable fourth via structure 374 is configured from the first end of the fifth metal interconnection line 365 to the first end of the sixth metal interconnection line 366.
Referring to fig. 7, a schematic structural diagram of still another semiconductor unit device in an embodiment of the present invention is given. Referring to fig. 8, a schematic structural diagram of still another semiconductor unit device in an embodiment of the present invention is given. The structure of the semiconductor unit device will be described with reference to fig. 7 and 8.
In an implementation, the semiconductor cell device 10 may include a high level output unit 11, a low level output unit 12, and a metal interconnection line 13. The metal interconnect lines 13 are provided with configurable via structures 14, the locations of the configurable via structures 14 being configurable, by configuring the locations of the configurable via structures 14, to connect the metal interconnect lines to a selected object.
In an implementation, the selected object may be any one of the high level output unit 11 and the low level output unit 12.
In some embodiments of the present invention, as shown in fig. 7, the configurable via structure 14 may connect the metal interconnect line 13 to the high level output unit 11, so that the configurable via structure 14 may conduct the metal interconnect line 13 with the high level output unit 11 and output a high level.
In other embodiments of the present invention, as shown in fig. 8, the configurable via structure 14 may connect the metal interconnect line 13 to the low level output unit 12, such that the configurable via structure 14 conducts the metal interconnect line 13 with the low level output unit 12, outputting a low level.
In an embodiment of the present invention, the configurable VIA structure 14 may include a VIA (VIA 1) and a conductive plug filled in the VIA.
When the output logic of the semiconductor unit device 10 needs to be changed after the wafer is streamed, for example, when the output logic is changed from a high level to a low level, only one photomask layer needs to be modified, the configurable via structure 14 is conducted between the metal interconnection line 13 and the high level output unit 11, the configurable via structure 14 is modified to conduct between the metal interconnection line 13 and the low level output unit 12, that is, by modifying one photomask layer, the position of the via structure 14 is configured to realize that the selected object conducted with the metal interconnection line 13 is the low level output unit 12 or the high level output unit 11, so as to realize the change of the output logic.
As can be seen from the above, the semiconductor unit device includes a high-level output unit, a low-level output unit, and a metal interconnect line, where a configurable via structure is disposed on the metal interconnect line, and the via structure is configurable, so that the metal interconnect line can be connected to a selected object, for example, the via structure can be used to conduct the metal interconnect line with the high-level output unit or conduct the metal interconnect line with the low-level output unit, and the metal interconnect line is used as an output pin, so that compatibility of the output pin can be achieved. If the output logic needs to be changed after the film is streamed, the output pins are compatible, ECO winding is not needed before and after ECO, and the change of the output logic can be realized by changing the position of the through hole structure by changing one photomask layer, so that the ECO cost can be reduced.
In an implementation, the high level output unit 11 may be a logic unit TIEHI for outputting a 1' b1 high level in a standard cell library. The low level output unit 12 may be used in a standard cell library to output a 1' b0 low level logic unit TIELO.
In an implementation, the high level output unit 11 and the low level output unit 12 may be formed on the first metal layer. The metal interconnection line 13 may be formed at the second metal layer.
It should be noted that the first Metal layer in the embodiment of the present invention may be Metal1. The second Metal layer may be Metal2. The first Metal layer may be Metal2, and the second Metal layer may be Metal3. In the embodiment of the present invention, the "first" of the first metal layers and the "second" of the second metal layers are only used to distinguish that the first metal layer and the second metal layer are not the same metal layer, that is, the metal layers where the high-level output unit 11 and the low-level output unit 12 are located and the metal layer formed by the metal interconnection line 13 are different metal layers.
In an embodiment of the present invention, the first metal layer and the second metal layer may be adjacent.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (7)

1. A semiconductor unit device, characterized by comprising: the power supply region, the PMOS tube, the NMOS tube, the grounding region, the output end and the metal connecting layer, wherein the metal connecting layer comprises a first metal interconnection line and a second metal interconnection line,
the source electrode of the PMOS tube is coupled with the power supply region, and the grid electrode of the PMOS tube is coupled with the first metal interconnection line;
the source electrode of the NMOS tube is coupled with the grounding region, and the grid electrode of the NMOS tube is coupled with the first metal interconnection line;
the output end is coupled with the second metal interconnection line;
the first metal interconnection line is provided with a configurable first through hole structure, and the position of the configurable first through hole structure is configurable to connect the first metal interconnection line to a selected first object; the second metal interconnection line is provided with a configurable second through hole structure, and the position of the configurable second through hole structure is configurable, so that the second metal interconnection line is connected to a selected second object, and the second object is conducted with the output end, wherein the first object is one of the drain electrode of the PMOS tube and the drain electrode of the NMOS tube, and the second object is the other of the drain electrode of the PMOS tube and the drain electrode of the NMOS tube.
2. The semiconductor unit device of claim 1, wherein,
the PMOS tube active region corresponding to the PMOS tube is positioned between the power supply region and the NMOS tube active region corresponding to the NMOS tube;
the NMOS tube active region is positioned between the PMOS tube active region and the grounding region;
the grid electrode of the PMOS tube divides the PMOS tube active region into a first PMOS tube active region and a second PMOS tube active region;
the grid electrode of the NMOS tube divides the NMOS tube active region into a first NMOS tube active region and a second NMOS tube active region;
the first end of the first metal interconnection line is positioned above the first active region of the PMOS tube, and the second end of the first metal interconnection line is positioned above the first active region of the NMOS tube;
the first end of the second metal interconnection line is located above the second active region of the PMOS tube, and the second end of the second metal interconnection line is located above the second active region of the NMOS tube.
3. The semiconductor cell device of claim 2, further comprising: gate portion and fifth via structure, wherein:
the first end of the grid part is used as the grid of the PMOS tube, and the second end of the grid part is used as the grid of the NMOS tube;
the metal connection layer further comprises a seventh metal interconnection line, a first end of the seventh metal interconnection line is coupled with the first metal interconnection line, and a second end of the seventh metal interconnection line is connected with the grid part;
the fifth through hole structure is arranged at the second end of the seventh metal interconnection line so as to conduct the grid electrode of the PMOS tube and the grid electrode of the NMOS tube with the first metal interconnection line.
4. The semiconductor unit device of claim 2, wherein,
the configurable first through hole structure is arranged at the second end of the first metal interconnection line, the first active region of the NMOS tube is communicated with the grid electrode of the PMOS tube, and the first active region of the NMOS tube is used as the drain electrode of the NMOS tube;
the configurable second through hole structure is arranged at the first end of the second metal interconnection line, the second active region of the PMOS tube is conducted with the second metal interconnection line, and the second active region of the PMOS tube is used as the drain electrode of the PMOS tube.
5. The semiconductor unit device according to any one of claims 2 to 4, further comprising: a configurable third via structure, a configurable fourth via structure, the metal connection layer further comprising: a third metal interconnection line, a fourth metal interconnection line, a fifth metal interconnection line, a sixth metal interconnection line, wherein:
the first end of the third metal interconnection line is positioned above the power supply region, and the second end of the third metal interconnection line is positioned above the first active region of the PMOS tube;
the first end of the fourth metal interconnection line is positioned above the power supply region, and the second end of the fourth metal interconnection line is positioned above the second active region of the PMOS tube;
the first end of the fifth metal interconnection line is positioned above the first active region of the NMOS tube, and the second end of the fifth metal interconnection line is positioned above the grounding region;
the first end of the sixth metal interconnection line is located above the second active region of the NMOS tube, and the second end of the sixth metal interconnection line is located above the grounding region;
the position of the configurable third through hole structure is configurable, and the configurable third through hole structure is arranged at the second end of the third metal interconnection line;
the position of the configurable fourth via structure is configurable, and the configurable fourth via structure is arranged at the first end of the sixth metal interconnection line.
6. The semiconductor unit device of claim 2, wherein,
the configurable first through hole structure is arranged at the first end of the first metal interconnection line, the first active region of the PMOS tube is communicated with the grid electrode of the NMOS tube, and the first active region of the PMOS tube is used as the drain electrode of the PMOS tube;
the configurable second through hole structure is arranged at the second end of the second metal interconnection line, the second active region of the NMOS tube is communicated with the second metal interconnection line, and the second active region of the NMOS tube is used as the drain electrode of the NMOS tube.
7. The semiconductor unit device according to claim 2, 3, or 6, wherein the metal connection layer further comprises: a third metal interconnect line, a fourth metal interconnect line, a fifth metal interconnect line, a sixth metal interconnect line, a configurable third via structure, a configurable fourth via structure, wherein:
the first end of the third metal interconnection line is positioned above the power supply region, and the second end of the third metal interconnection line is positioned above the first active region of the PMOS tube;
the first end of the fourth metal interconnection line is positioned above the power supply region, and the second end of the fourth metal interconnection line is positioned above the second active region of the PMOS tube;
the first end of the fifth metal interconnection line is positioned above the first active region of the NMOS tube, and the second end of the fifth metal interconnection line is positioned above the grounding region;
the first end of the sixth metal interconnection line is located above the second active region of the NMOS tube, and the second end of the sixth metal interconnection line is located above the grounding region;
the position of the configurable third through hole structure is configurable, and the configurable third through hole structure is arranged at the second end of the fourth metal interconnection line;
the position of the configurable fourth via structure is configurable, and the configurable fourth via structure is arranged at the first end of the fifth metal interconnection line.
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