CN111108694B

CN111108694B - Multi-channel passive intermodulation digital cancellation circuit

Info

Publication number: CN111108694B
Application number: CN201780095095.1A
Authority: CN
Inventors: 王昊; 陈莹莹; 罗宇平
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2017-10-27
Filing date: 2017-10-27
Publication date: 2021-09-14
Anticipated expiration: 2037-10-27
Also published as: WO2019080124A1; US20200252094A1; US10911084B2; EP3687074A1; EP3687074A4; CN111108694A; EP3687074B1

Abstract

The invention discloses a multi-channel PIM digital cancellation circuit, which comprises: the device comprises a first frequency shift variable-rate module, a second frequency shift variable-rate module, a first conversion circuit, a second conversion circuit, a duplexer, a second transmitting duplexer, a channel combiner, a third conversion circuit, a cascade filter circuit, a PIM canceller, a feedback circuit and a first adder. The cascade filter circuit compensates channel responses such as time delay difference, phase difference and the like generated after a transmitting signal passes through a digital domain downlink, a digital-to-analog converter and an analog domain downlink; the cascade filter circuit simulates the uneven group delay characteristic of a duplexer in the multi-channel PIM digital cancellation circuit; the cascade filter fits the S parameter of the channel combiner in the multi-channel PIM digital cancellation circuit, and the combining process of the channel combiner is accurately fitted in a digital domain, so that the invention can generate a signal capable of canceling the PIM interference signal of a radio frequency system in multi-emission and multi-reception of the channel combiner.

Description

Multi-channel passive intermodulation digital cancellation circuit

Technical Field

The application relates to the field of passive intermodulation cancellation, in particular to a multi-channel passive intermodulation digital cancellation circuit

Background

In a Frequency Division Duplex (FDD) system multi-carrier base station communication system, under a multi-carrier and large transmission bandwidth scene, an antenna feed system can generate Passive Inter Modulation (PIM) interference signals due to bad parts, screw looseness, vibration and the like, and when Frequency points of the PIM interference signals fall in a receiving Frequency band, the receiving signal Frequency spectrum can be overlapped or expanded, so that the receiving sensitivity of a base station system is seriously influenced, and further the network uplink throughput rate is influenced.

In view of the above problems, in the prior art, a PIM canceller is proposed. The PIM canceller can model and cancel PIM interference signals falling into a receiving frequency band in a non-linear mode on a digital domain. But PIM interference signals of a multi-transmitting and receiving radio frequency system with a channel combiner, such as an electric bridge, a V network structure and the like, cannot be counteracted.

Disclosure of Invention

The embodiment of the invention discloses a multi-channel passive intermodulation digital cancellation circuit, which can solve the problem that PIM interference signals of a radio frequency system in multi-transmitting and receiving of a combiner in the forms of an electric bridge, a V network structure and the like cannot be cancelled.

In a first aspect, an embodiment of the present invention provides a multi-channel PIM digital cancellation circuit, including:

the device comprises a first frequency shift variable-rate module, a second frequency shift variable-rate module, a first conversion circuit, a second conversion circuit, a duplexer, a second transmitting duplexer, a channel combiner, a third conversion circuit, a cascade filter circuit, a PIM canceller, a feedback circuit and a first adder;

an input port of the first frequency shift variable rate module is used as a first input port of the multi-channel PIM digital cancellation circuit, an output port of the first frequency shift variable rate module is connected with an input port of the first conversion circuit, an output port of the first conversion circuit is connected with a first input port of the duplexer, and a first output port of the duplexer is connected with a first input/output port of the channel combiner;

an input port of the second frequency shift variable rate module is used as a second input port of the multi-channel PIM digital cancellation circuit, an output port of the second frequency shift variable rate module is connected with an input port of the second conversion circuit, an output port of the second conversion circuit is connected with an input port of the second transmitting duplexer, and an output port of the second transmitting duplexer is connected with a second input/output port of the channel combiner;

a first input port of the cascade filter module is connected with an output port of the first frequency shift variable rate module, a second input port of the cascade filter module is connected with an output port of the second frequency shift variable rate module, the first output port and the second output port of the cascade filter module are both connected with an input port of the PIM canceller, and an output port of the PIM canceller is connected with a first input port of the first adder;

the first input/output port of the channel combiner is connected with the second input port of the duplexer, the second output port of the duplexer is connected with the input port of the third converting circuit, the output port of the third converting circuit is connected with the second input port of the first adder, and the output port of the first adder is the output port of the multi-channel PIM digital cancellation circuit.

In one possible embodiment, the cascaded filter circuit includes:

a first channel filter, a second channel filter, a first equalization filter, a second equalization filter, a first linear filter, a second linear filter, a third linear filter, a fourth linear filter, a second adder, and a third adder;

the input port of the first channel filter and the input port of the second channel filter are respectively a first input port and a second input port of the cascade filter circuit, the output port of the first channel filter is connected with the input port of the first equalization filter, and the output port of the second channel filter is connected with the input port of the second equalization filter;

an output port of the first equalization filter is connected to an input port of the first linear filter and an input port of the second linear filter, and an output port of the second equalization filter is connected to an input port of the third linear filter and an input port of the fourth linear filter;

the output ports of the first linear filter and the third linear filter are respectively connected with the first input port and the second input port of the second adder, and the output ports of the second linear filter and the fourth linear filter are respectively connected with the first input port and the second input port of the third adder;

the output port of the second adder and the output port of the third adder are respectively a first output port and a second output port of the cascade filter circuit.

In a possible embodiment, the first conversion circuit comprises:

a first digital domain downlink, a first digital-to-analog converter, and a first analog domain downlink;

the input port of the first digital domain downlink is the input port of the first conversion circuit, the output port of the first digital domain downlink is connected with the input port of the first digital-to-analog converter, the output port of the first digital-to-analog converter is connected with the input port of the first analog domain downlink, and the output port of the first analog domain downlink is the output port of the first conversion circuit.

In one possible embodiment, the second conversion circuit includes:

a second digital domain downlink, a second digital-to-analog converter, and a second analog domain downlink;

the input port of the second digital domain downlink is an input port of the second conversion circuit, the output port of the second digital domain downlink is connected with the input port of the second digital-to-analog converter, the output port of the second digital-to-analog converter is connected with the input port of the second analog domain downlink, and the output port of the second analog domain downlink is an output port of the second conversion circuit.

In one possible embodiment, the duplexer includes:

a first transmit duplexer and a receive duplexer;

an input port of the first transmitting duplexer is a first input port of the duplexer, and an output port of the first transmitting duplexer is a first output port of the duplexer;

the input port of the receiving duplexer is the second input port of the duplexer, and the output port of the receiving duplexer is the second output port of the duplexer.

In one possible embodiment, the third conversion circuit includes:

the device comprises a first analog-to-digital conversion circuit and an analog domain uplink;

the input port of the analog domain uplink is the input port of the third conversion circuit, the output port of the analog domain uplink is connected with the input port of the first analog-to-digital converter, and the output port of the first analog-to-digital converter is the output port of the third conversion circuit.

In one possible embodiment, the feedback circuit includes:

the combiner, the second analog-to-digital converter, the digital domain feedback link and the third memory;

the input port of the combiner is the input port of the feedback circuit, and the output port of the combiner is connected with the input port of the second analog-to-digital converter;

an output port of the second analog-to-digital converter is connected with an input port of the digital domain feedback link, and an output port of the digital domain feedback link is connected with an input port of the third memory.

In one possible embodiment, the multi-channel PIM digital cancellation circuit further comprises a first data collection node U0, a second data collection node U1, and a third data collection node S0;

the first data acquisition node U0 is located at the output port of the first frequency-shift variable rate module, the second data acquisition node U1 is located at the output port of the second frequency-shift variable rate module, and the third data acquisition node S0 is located at the output port of the second digital domain downlink.

In one possible embodiment, the multi-channel PIM digital cancellation circuit further comprises a first coupling node P0 and a second coupling node P1;

the first coupling node P0 is connected with the output port of the first transmitting duplexer, and the second coupling node P1 is connected with the output port of the second transmitting duplexer.

In one possible embodiment, the multi-channel PIM digital cancellation circuit further comprises a first memory and a second memory;

the input port of the first memory is connected with the output port of the first frequency shift variable rate module, and the input port of the second memory is connected with the output port of the second frequency shift variable rate module.

In one possible embodiment, the multi-channel PIM digital cancellation circuit further comprises a processor comprising a first processor, a second processor, and a third processor;

the output port of the first processor is connected with the input port of the coefficient register of the first channel filter and the input port of the coefficient register of the second channel filter;

the output port of the second processor is connected with the input port of the coefficient register of the first equalization filter and the input port of the coefficient register of the second equalization filter;

the output port of the third processor is connected to the input port of the coefficient register of the first linear filter, the input port of the coefficient register of the second linear filter, the input port of the coefficient register of the third linear filter, and the input port of the coefficient register of the fourth linear filter.

In a possible embodiment, the first processor is configured to store the data collected from the first data collection node U0 in the first memory;

the first processor is further configured to store the data collected from the second data collection node U1 in the second memory;

the first processor is further configured to store the data collected from the third data collecting node S0 in the third memory.

In a possible embodiment, the first processor is further configured to:

retrieving from the first memory the data collected from the first data collection node U0, retrieving from the second memory the data collected from the second data collection node U1, retrieving from the third memory the data collected from the third data collection node S0;

performing linear interpolation fitting on the data collected from the first data collection node U0, the data collected from the second data collection node U1 and the data collected from the third data collection node S0 to obtain filter coefficients of the first channel filter and filter coefficients of the second channel filter;

and respectively downloading the filter coefficient of the first channel filter and the filter coefficient of the second channel filter into a coefficient register of the first channel filter and a coefficient register of the second channel filter.

In a possible embodiment, the second processor is further configured to:

acquiring S parameters of the duplexer;

performing linear interpolation fitting on the S parameter of the duplexer to obtain a filter coefficient of the first equalization filter and a filter coefficient of the second equalization filter;

and downloading the filter coefficient of the first equalization filter and the filter coefficient of the second equalization filter into a coefficient register of the first equalization filter and a coefficient register of the second equalization filter respectively.

In a possible embodiment, the third processor is further configured to:

obtaining an S parameter of the channel combiner;

performing linear interpolation fitting on the S parameter of the channel combiner to obtain a filter coefficient of the first linear filter, a filter coefficient of the second linear filter, a filter coefficient of the third linear filter and a filter coefficient of the fourth linear filter;

downloading the filter coefficients of the first linear filter, the second linear filter, the third linear filter and the fourth linear filter into a coefficient register of the first linear filter, a coefficient register of the second linear filter, a coefficient register of the third linear filter and a coefficient register of the fourth linear filter, respectively.

It can be seen that, in the solution of the embodiment of the present invention, the channel filter in the cascaded filter circuit compensates the channel response inconsistency, such as the delay difference, the phase difference, etc., of the transmission signal generated after passing through the digital domain downlink, the digital-to-analog converter, and the analog domain downlink; the equalization filter in the cascade filter circuit is used for simulating the uneven group delay characteristic of a duplexer in the multi-channel PIM digital cancellation circuit; the linear filter of the cascade filter is used for fitting the S parameter of the channel combiner in the multi-channel PIM digital cancellation circuit, and the combining process of the channel combiner is accurately fitted in a digital domain, so that the multi-channel PIM digital cancellation circuit can generate a signal capable of canceling the PIM interference signal of a radio frequency system in multi-transmitting and multi-receiving of the channel combiner.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic structural diagram of a multi-channel PIM digital cancellation circuit according to an embodiment of the present invention;

fig. 2 is a schematic structural diagram of a cascaded filter circuit according to an embodiment of the present invention;

fig. 3 is a schematic diagram illustrating a partial structure of a multi-channel PIM digital cancellation circuit according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of another multi-channel PIM digital cancellation circuit according to an embodiment of the present invention;

fig. 5 is a schematic structural diagram of another cascaded filter circuit according to an embodiment of the present invention;

fig. 6 is a schematic partial structure diagram of another multi-channel PIM digital cancellation circuit according to an embodiment of the present invention.

Detailed Description

The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a multi-channel digital PIM cancellation circuit according to an embodiment of the present invention. As shown in fig. 1, the multi-channel PIM digital cancellation circuit includes: .

A first frequency shift variable rate module 101, a first memory 102, a first conversion circuit 103, a duplexer 104, a channel combiner 105, a second frequency shift variable rate module 106, a second memory 107, a second conversion circuit 108, a second transmitting duplexer 109, a cascade filter circuit 110, a PIM canceller 111, a third conversion circuit 112, a feedback circuit 113, and a first adder 114.

The input port of the first frequency shift variable rate module 101 is a first input port of the multi-channel PIM digital cancellation circuit, the output port of the first frequency shift variable rate module 101 is connected to the input port of the first conversion circuit 103, the output port of the first conversion circuit 103 is connected to a first input port of the duplexer 104, and a first output port of the duplexer 104 is connected to a first input/output port of the channel combiner 105.

Specifically, the first conversion circuit 103 includes a first digital domain downlink 1031, a first digital-to-analog converter 1032, and a first analog domain downlink 1033. An input port of the first digital domain downlink 1031 is an input port of the first conversion circuit 103, an output port of the first digital domain downlink 1031 is connected to an input port of the first digital-to-analog converter 1032, an output port of the first digital-to-analog converter 1032 is connected to an input port of the first analog domain downlink 1033, and an output port of the first analog domain downlink 1033 is an output port of the first conversion circuit.

Specifically, the duplexer 104 includes a first transmitting duplexer 1041 and a receiving duplexer 1042. The input port 1041 of the first transmitting duplexer is a first input port of the duplexer 104, the output port of the first transmitting duplexer 1041 is a first output port of the duplexer 104, and the input port and the output port of the receiving duplexer 1042 are a second input port and a second output port of the duplexer 104, respectively.

Note that the output port of the first transmitting duplexer 1041 and the input port of the receiving duplexer 1042 are both connected to a common pin of the duplexer 104. The duplexer 104 has an input/output port as viewed from the outside. The input/output port is connected to a first input/output port of the channel combiner 105.

The output port of the first converting circuit is connected to the first input port of the duplexer 104, specifically, the output port of the first converting circuit is connected to the input port of the first transmitting duplexer 1041 in the duplexer 104, and the first output port of the duplexer 104 is connected to the first input output port of the channel combiner 105, specifically, the output port of the first transmitting duplexer 1041 in the duplexer 104 is connected to the first input output port of the channel combiner 105.

The input port of the second frequency shift variable rate module 106 is a second input port of the multi-channel PIM digital cancellation circuit, the output port of the second frequency shift variable rate module 106 is connected to the input port of the second switching circuit 108, the output port of the second switching circuit 108 is connected to the input port of the second transmitting duplexer 109, and the output port of the second transmitting duplexer 109 is connected to a second input/output port of the channel combiner 105.

Specifically, the second conversion circuit 108 includes a second digital domain downlink 1081, a second digital-to-analog converter 1082, and a second analog domain downlink 1083. The input port of the second digital domain downlink 1081 is the input port of the second conversion circuit 108, the output port of the second digital domain downlink 1081 is connected to the input port of the second digital-to-analog converter 1082, the output port of the second digital-to-analog converter 1082 is connected to the input port of the second analog domain downlink 1083, and the output port of the second analog domain downlink 1083 is the output port of the second conversion circuit 108.

The multi-channel PIM digital cancellation circuit further comprises a first data acquisition node U0 and a second data acquisition node U1. The first data acquisition node U0 is coupled to an output port of the first frequency shift rate module 101, and the second data acquisition node U1 is coupled to an output port of the second frequency shift rate module 106. The first input port of the cascade filter circuit 110 is connected to the first data acquisition node U0, and the second input port of the cascade filter circuit 110 is connected to the second data acquisition node U1, in other words, the first input port of the cascade filter circuit 110 is connected to the output port of the first frequency shift rate module 101, and the second input port of the cascade filter circuit 110 is connected to the output port of the second frequency shift rate module 106. A first output port and a second output port of the cascade filter circuit 110 are both connected to an input port of the PIM canceller 111, and an output port of the PIM canceller 111 is connected to a first input port of the first adder 114.

Further, the input port of the first memory 102 is connected to the first data collection node U0, and the input port of the second memory 107 is connected to the first data collection node U1. In other words, the input port of the first memory 102 is connected to the output port of the first shift rate module 101, and the input port of the second memory 107 is connected to the output port of the second shift rate module 106.

The first input/output port of the channel combiner 105 is connected to the second input port of the duplexer 104 (i.e., the input port of the receiving duplexer 1042), the second output port of the duplexer 104 (i.e., the output port of the receiving duplexer 1042) is connected to the input port of the third converting circuit 112, the output port of the third converting circuit 112 is connected to the second input port of the first adder 114, and the output port of the first adder 114 is the output port of the multi-channel PIM digital cancellation circuit.

Specifically, the third conversion circuit 112 includes a first analog-to-digital converter 1121 and an analog domain uplink 1122. The input port of the analog domain uplink is an input port of the third converter circuit, the output port of the analog domain uplink is connected with the input port of the first analog-to-digital converter, and the output port of the first analog-to-digital converter is an output port of the third converter circuit.

The multi-channel PIM digital cancellation circuit further comprises a first coupling node P0 and a second coupling node P1. The first coupling node P0 is located between the first output port of the duplexer 104 (i.e., the output port of the first transmitting duplexer 1041) and the first input/output port of the channel combiner 105, and the second coupling node P1 is located between the second transmitting duplexer 109 and the second input/output port of the channel combiner 105. The first coupling node P0 and the second coupling node P1 are both connected to an input port of the feedback circuit 113.

Specifically, the feedback circuit 113 includes a combiner 1131, a second analog-to-digital converter 1132, a digital domain feedback link 1133, and a third memory 1134. An input port of the combiner 1131 is an input port of the feedback circuit 114, an output port of the combiner 1131 is connected to an input port of the second analog-to-digital converter 1132, the second analog-to-digital converter 1132 is connected to an input port of the digital domain feedback link 1133, and an output port of the digital domain feedback link 1133 is connected to an input port of the third memory 1134.

Specifically, the operation process of the multi-channel PIM digital cancellation circuit is as follows:

the sending direction is as follows: the first transmission signal Ch0 is input to the multi-channel PIM digital cancellation circuit through the input port of the first frequency shift rate module 101. The first frequency shift/rate change module 101 performs frequency shift, rate change, and wave suppression on the first transmission signal Ch0 in sequence, and then transmits a first transmission signal obtained after the processing to a first digital domain downlink 1031 in the first conversion circuit 103, where the first digital domain downlink 1031 performs digital pre-distortion, Quadrature Modulation Compensation (QMC) and other processing on the first transmission signal, and transmits a second transmission signal obtained after the processing to the first digital-to-analog converter 1032, and the first digital-to-analog converter 1032 converts the second transmission signal from a digital domain to an analog domain, in other words, the first digital-to-analog converter 1032 converts the second transmission signal from a digital signal to an analog signal, and obtains a third transmission signal, and transmits the third transmission signal to the first analog domain downlink 1033. The first analog domain downlink 1033 performs power amplification and other processing on the third transmit signal to obtain a fourth transmit signal, and transmits the fourth transmit signal to the first duplexer 104, and the first transmit duplexer 1041 transmits the fourth transmit signal to the channel combiner 105.

Similarly, the second transmitting signal Ch1 is input to the multi-channel PIM digital cancellation circuit through the input port of the second frequency shift rate module 106. The second frequency shift/rate conversion module 106 sequentially performs frequency shift, rate conversion, and wave suppression on the second transmission signal Ch1, and then transmits the fifth transmission signal obtained after the processing to the second digital domain downlink 1081 in the second conversion circuit 108, the second digital domain downlink 1081 performs digital predistortion, Quadrature Modulation Compensation (QMC) and other processing on the sixth transmission signal, and transmits the sixth transmission signal obtained after the processing to the second digital-to-analog converter 1082, and the first digital-to-analog converter 1082 converts the sixth transmission signal from the digital domain to the analog domain, in other words, the second digital-to-analog converter 1082 converts the sixth transmission signal from a digital signal to an analog signal, obtains a seventh transmission signal, and transmits the seventh transmission signal to the second analog domain downlink 1083. The second analog domain downlink 1083 performs power amplification and other processing on the seventh transmit signal to obtain an eighth transmit signal, and transmits the eighth transmit signal to the second duplexer 109, and the first duplexer 109 transmits the eighth transmit signal to the channel coupler 105.

The QMC processing is specifically to compensate for phase offset, amplitude offset, and local oscillator leakage in an Analog Quadrature Modulation (AQM) process. This function is implemented in particular by the QMC module.

The channel combiner 105 combines the fourth transmitting signal and the eighth transmitting signal together, and sends the combined signal to the antenna port to be transmitted.

The signals collected at the first coupling node P0 and the second coupling node P1 are the fourth transmission signal and the eighth transmission signal, respectively. After the fourth transmission signal and the eighth transmission signal are transmitted to the input port of the feedback circuit 113 (i.e., the input port of the combiner 1131), the combiner 1131 superimposes the fourth transmission signal and the eighth transmission signal to obtain a first processed signal, i.e., the first processed signal is the fourth transmission signal + the eighth transmission signal. The second analog-to-digital converter 1132 converts the first processed signal from an analog domain to a digital domain, that is, converts the first processed signal from an analog signal to a digital signal to obtain a second processed signal, and the second digital domain downlink performs frequency shift and variable rate processing on the second processed signal to obtain a third processed signal, and stores the third processed signal in the third memory 1134.

After the first transmission signal and the fifth transmission signal are input to the first input port and the second input port of the cascade filter circuit 110, the cascade filter circuit 110 outputs a first filtered signal and a second filtered signal from the first output port and the second port thereof, respectively, according to the first transmission signal and the second transmission signal. After the first filtered signal and the second filtered signal are input to the input port of the PIM canceller 111, the PIM canceller 111 generates a PIM cancelled signal according to the first filtered signal and the second filtered signal, and outputs the PIM cancelled signal from the output port of the PIM canceller.

The multi-channel PIM digital cancellation circuit further comprises a processor. After the first shift frequency rate module 101 outputs a first transmission signal, the processor stores the first transmission signal in the first memory 102, that is, the data acquired by the processor from the first data acquisition node U0 is stored in the first memory 102. Similarly, after the second frequency shift rate module 106 outputs a fifth transmission signal, the processor stores the fifth transmission signal in the second memory 107, that is, the processor stores the data acquired from the second data acquisition node U1 in the second memory 107.

It should be noted that the first Memory 102, the second Memory 107, and the third Memory 1134 may be Random Access Memories (RAMs). The first memory 102, the second memory 107, and the third memory 1134 are different RAMs.

The receiving direction is as follows: after receiving the first receiving signal, the antenna of the channel combiner 105 transmits the first receiving signal to the receiving duplexer 1042, the receiving duplexer 1042 transmits the first receiving signal to the analog domain uplink 1122, and the analog domain uplink performs low-noise amplification, filtering, and the like on the first receiving signal to obtain a second receiving signal. The first analog-to-digital converter 1032 converts the second received information from an analog domain to a digital domain, i.e., converts the second received signal from an analog signal to a digital signal, and obtains a third received signal.

The first adder 114 subtracts the PIM cancellation signal generated by the PIM canceller 111 from the third received signal to obtain a corrected signal, that is, a corrected signal, which is the third received signal — the PIM cancellation signal.

The third received signal may be regarded as the first transmitted signal Ch0 plus a PIM interference signal, and the PIM cancellation signal is a PIM interference signal simulated by the multi-channel PIM digital cancellation circuit. The corrected signal, i.e., the first transmission signal Ch0, is obtained by subtracting the PIM offset signal from the third reception signal.

The circuit architecture and the operation principle of the cascaded filter circuit are specifically described below.

Referring to fig. 2, fig. 2 is a schematic structural diagram of a cascaded filter circuit according to an embodiment of the present invention. As shown in fig. 2, the circuit 110 includes: a first channel filter 1101, a second channel filter 1102, a first equalization filter 1103, a second equalization filter 1104, a first linear filter 1105, a second linear filter 1106, a third linear filter 1107, a fourth linear filter 1108, a second adder 1109, and a third adder 1110.

An input port of the first channel filter 1101 and an input port of the second channel filter 1102 are respectively a first input port and a second input port of the cascade filter circuit 110, the input port of the first channel filter 1101 is connected to the input port of the first equalization filter 1103, and the input port of the second channel filter 1102 is connected to the input port of the second equalization filter 1104. An input port of the first linear filter 1105 and an input port of the second linear filter 1106 are both connected to an output port of the first equalization filter 1103, and an input port of the third linear filter 1107 and an input port of the fourth linear filter 1108 are both connected to an output port of the second equalization filter 1104. An output port of the first linear filter 1105 and an output port of the third linear filter 1107 are connected to a first input port and a second input port of the second adder 1109, respectively, and an output port of the second linear filter 1106 and an output port of the fourth linear filter 1108 are connected to a first input port and a second input port of the third adder 1110, respectively. An output port of the second adder 1109 and an output port of the third adder 1110 are a first output port and a second output port of the cascade filter circuit 110, respectively.

After the first processed signal U0 is input to the first channel filter 1101, the first channel filter 1101 outputs a third filtered signal F1; after the second processed signal U1 is input to the second channel filter 1102, the second channel filterThe filter 1102 outputs a fourth filtered signal F2. Wherein,

and FIR _ CH0 and FIR _ CH1 are filter coefficients of the first channel filter 1101 and filter coefficients of the second channel filter 1102, respectively. After the third filtered signal F1 is input to the first equalizer filter 1103, the first equalizer filter 1103 outputs a fifth filtered signal F3; after the fourth filtered signal F2 is input to the second equalizer filter 1104, the second pass filter 1104 outputs a fourth filtered signal F4. Wherein,

and DUP _ EQ1 and DUP _ EQ2 are the filter coefficients of the first equalizer filter 1103 and the second equalizer filter 1104, respectively. After the fifth filtered signal F3 is inputted into the first linear filter 1105 and the second linear filter 1106, the first linear filter 1105 and the second linear filter 1106 respectively output a seventh filtered signal F5 and an eighth filtered signal F6; after the sixth filtered signal F4 is input to the third linear filter 1107 and the fourth linear filter 1108, the third linear filter 1107 and the fourth linear filter 1108 output a ninth filtered signal F7 and a tenth filtered signal F8, respectively. Wherein,

and the HB _ FIR1, HB _ FIR2, HB _ FIR3 and HB _ FIR4 are the filter coefficient of the first linear filter 1105, the filter coefficient of the second linear filter 1106, the filter coefficient of the third linear filter 1107 and the filter coefficient of the fourth linear filter 1108, respectively. The seventh filtered signal F5 and the ninth filtered signal F7 are inputted to the second adder 1109 through the first input port and the second input port of the second adder 1109, respectively, and then the second adder 1109 outputs a first filtered signal TX 0; the eighth filtered signal F6 and the tenth filtered signal F8 respectively pass throughThe third adder 1110 outputs the second filter signal TX1 after the first input port and the second input port of the third adder 1110 are input to the third adder 1110. Wherein, TX0 ═ F5+ F7, TX1 ═ F6+ F8.

It is noted that, as mentioned above

Is the convolution operator.

The first channel filter 1101 and the second channel filter 1102 compensate for channel response inconsistencies, such as a delay difference and a phase difference, which are generated when the first transmission signal Ch0 and the second transmission signal Ch1 pass through different channels, so that the first filtered signal and the second filtered signal input by the PIM canceller 111 respectively match the characteristics of the first fourth transmission signal and the eighth transmission signal input by the channel combiner. The first equalizing filter 1103 and the second equalizing filter 1104 are used to simulate the group delay unevenness of the transmitting duplexer. The four sets of linear filters are used to simulate the combining relationship and process of the multi-channel combiner 105.

The connection relationship between the processor and other parts of the multi-channel PIM digital cancellation circuit and the operation process of the processor are described in detail below.

As shown in fig. 3, the multi-channel PIM digital cancellation circuit further includes a processor 115, and the processor 115 includes a first processor 1151, a second processor 1152 and a third processor 1153.

An output port of the first memory 102, an output port of the second memory 107, and an output port of the third memory 1134 are all connected to an input port of the first processor 1151, and an input port of the coefficient register 1101 of the first channel filter and an input port of the coefficient register 1102 of the second channel filter are all connected to an output port of the first processor 1151. An input port of the coefficient register 1103 of the first equalization filter and an input port of the coefficient register 1104 of the second equalization filter are connected to an output port of the second processor 1152, and an input port of the coefficient register 1105 of the first linear filter, an input port of the coefficient register 1106 of the second linear filter, an input port of the coefficient register 1107 of the third linear filter and an input port of the coefficient register 1108 of the fourth linear filter are connected to an output port of the third processor 1153.

The first processor 1151 acquires the first transmission signal from the first memory 102, the fifth transmission signal from the second memory 107, and the third processed signal from the third memory 1134. The first processor 1151 performs LS linear interpolation fitting according to the first transmitted signal, the fifth transmitted signal, and the third processed signal to obtain a filter coefficient FIR _ CH0 of the first channel filter 1101 and a filter coefficient FIR _ CH1 of the second channel filter 1102. After the first processor 1151 obtains the FIR _ CH0 and the FIR _ CH1, the first processor 1151 downloads the FIR _ CH0 and the FIR _ CH1 to the coefficient register 1101 of the first channel filter and the coefficient register 1102 of the second channel filter, respectively.

Before the first equalizing filter 1103 and the second equalizing filter 1104 in the cascaded filtering circuit 110 operate, the second processor 1152 performs a test on the transmit signal and the receive signal of the duplexer 104 (including the first transmit duplexer 1041 and the receive duplexer 1042) to obtain two sets of group delay parameters or S parameters of the duplexer 104. When the obtained data is the S parameter of the duplexer, the second processor 1152 converts the S parameter of the duplexer into a group delay parameter. The second processor 1152 performs LS linear interpolation fitting according to the two groups of group delay parameters to obtain a filter coefficient DUP _ EQ1 of the first equalization filter and a filter coefficient DUP _ EQ2 of the second equalization filter. After the second processor 1152 acquires the DUP _ EQ1 and the DUP _ EQ2, the second processor 1152 downloads the DUP _ EQ1 and the DUP _ EQ2 to the coefficient register 1103 of the first equalizer filter and the coefficient register 1104 of the second equalizer filter, respectively.

Before the third processor 1153 operates the channel combiner 105, the third processor 1153 tests the channel combiner to obtain the S-parameter of the channel combiner. The third processor 1153 then obtains frequency response information of signals from P0 to H0, P0 to H1, P1 to H0, and P1 to H1 (see fig. 1 herein) according to the S parameter. The third processor 1153 performs linear interpolation fitting on the four responses by using four sets of linear filters (including the first linear filter 1105, the second linear filter 1106, the third linear filter 1107, and the fourth linear filter 1108), to obtain filter coefficients of the four sets of linear filters: HB _ FIR1, HB _ FIR2, HB _ FIR3, and HB _ FIR 4. The third processor downloads the four filter coefficients HB _ FIR1, HB _ FIR2, HB _ FIR3, and HB _ FIR4 to the coefficient register 1105 of the first linear filter, the coefficient register 1106 of the second linear filter, the coefficient register 1107 of the third linear filter, and the coefficient register 1108 of the fourth linear filter, respectively.

It should be noted that the first processor 1151, the second processor 1152 and the third processor 1153 may all be DSP chips, and the first processor 1151, the second processor 1152 and the third processor 1153 may be the same DSP chip or different DSP chips.

It should be noted that the channel combiner in the multi-channel PIM digital cancellation circuit described in fig. 1 to 3 is a bridge.

In a possible embodiment, when the channel combiner in the multi-channel PIM digital cancellation circuit is a combiner in a V-network structure, as shown in fig. 4. Fig. 4 is a schematic structural diagram of a multi-channel PIM digital cancellation circuit according to an embodiment of the present invention. As shown in fig. 4, the circuit includes:

a first frequency shift variable rate module 401, a first memory 402, a first switching circuit 403, a duplexer 404, a channel combiner 405, a second frequency shift variable rate module 406, a second memory 407, a second switching circuit 408, a second transmit duplexer 409, a cascade filter circuit 410, a PIM canceller 411, a third switching circuit 412, a feedback circuit 413, and a first adder 414.

It should be noted that, in the multi-channel PIM digital cancellation circuit, except for the channel combiner 405 and the cascade filter circuit 410, the relevant description of the connection relationship and the function of other circuits or modules may refer to the relevant description of the embodiment shown in fig. 1, and is not described herein again.

The first input/output port of the channel combiner 410 is connected to the first output port of the duplexer 404 (i.e., the output port of the first transmitting duplexer 4041) and the second input port (i.e., the input port of the receiving duplexer 4042), and the second input/output port of the channel combiner 410 is connected to the output port of the second transmitting duplexer 409. The channel combiner also comprises N antennas, and a first input/output port and a second input/output port of the channel combiner are connected with the N antennas.

The signals output by the first transmitting duplexer are transmitted through the N antennas of the channel combiner, and the signals output by the second transmitting duplexer are transmitted through the N antennas of the channel combiner.

The structure and operation of the cascaded filter circuit are described below.

Referring to fig. 5, fig. 5 is a schematic structural diagram of a cascaded filter circuit according to an embodiment of the present invention. As shown in fig. 5, the cascade filter circuit includes: a first channel filter, a second channel filter, a first equalization filter, a second equalization filter, N linear filters, and N/2 adders. The N linear filters are, in order, linear filter 1, linear filter 2, linear filter 3, linear filter 4, linear filter 5, linear filter 6.. linear filter N-1 and linear filter N, and are numbered 1, 2, 3, 4, 5, 6.. No. N-1 and N, respectively. The N/2 adders are an adder 1, an adder 2 and an adder 3 in sequence, and are numbered 1, 2 and 3. Wherein N is an even number greater than 2.

The input port of the first channel filter and the input port of the second channel filter are respectively a first input port and a second input port of the cascade filter circuit. An output port of the first channel filter is connected to an input port of the first equalizer filter, and an output port of the second channel filter is connected to an input port of the second equalizer filter. An output port of the first equalization filter is connected to an input port of an odd-numbered line filter of the N linear filters, and an output port of the second equalization filter is connected to an input port of an even-numbered line filter of the N linear filters.

The output ports of every two linear filters (including the output port of the linear filter i and the output port of the linear filter j) of the N linear filters are connected to the first input port and the second input port of the adder m. Wherein the number i of the linear filter i and the number j of the linear filter j satisfy the following relationship: the difference between j and i is 1, j is an even number greater than 2 and less than or equal to N/2, and i is an odd number greater than 0 and less than N/2. The number m of the adder m is j/2. And the output ports of the N/2 adders are the output ports of the cascade filter circuit.

The first processed signal U0 is input to the first channel filter, which outputs a first filtered signal F1; after the second processed signal U1 is input to the second pass filter, the second pass filter outputs a second filtered signal F2. Wherein,

and FIR _ CH0 and FIR _ CH1 are respectivelyThe filter coefficients of the first channel filter and the filter coefficients of the second channel filter. After the first filtered signal F1 is input to the first equalizer filter, the first equalizer filter outputs a third filtered signal F3; the second pass filter outputs a fourth filtered signal F4 after the second filtered signal F2 is input to the second equalizer filter. Wherein,

and DUP _ EQ1 and DUP _ EQ2 are the filter coefficients of the first equalization filter and the filter coefficients of the second equalization filter, respectively.

After the third filtered signal F3 passes through the odd-numbered linear filters of the N linear filters, the odd-numbered linear filters of the N linear filters output first linear filtered signals S1, S3, and S5. After the fourth filtered signal F4 passes through the even-numbered linear filter of the N linear filters, the even-numbered linear filter of the N linear filters outputs the first linear filtered signals S2, S4, and S6. Wherein, the above

And HB _ FIR1, HB _ FIR3, HB _ FIRs 5... HB _ FIR (N-1) are respectively odd numbered ones of the N linear filters, and HB _ FIR2, HB _ FIR4, HB _ FIRs 6.. HB _ FIRN are respectively odd numbered ones of the N linear filters.

After the first linear filtering signals S1, S2, S3, S4, S5, S6...... S (N-1) and SN are input to the N/2 adders, N/2 second linear filtering signals TX1, TX2, and tx3...... TX (N/2) are obtained. TX (N/2) ═ S (N-1) + SN, wherein TX1 ═ S1+ S2, TX2 ═ S3+ S4, and TX3 ═ S5+ S6.

As shown in fig. 6, the multi-channel PIM digital cancellation circuit further includes a processor including a first processor, a second processor, and a third processor.

An output port of the first memory, an output port of the second memory, and an output port of the third memory are all connected to an input port of the first processor, and an input port of a coefficient register of the first channel filter and an input port of a coefficient register of the second channel filter are all connected to an output port of the first processor. The input ports of the coefficient registers of the first equalization filter and the input ports of the coefficient registers of the second equalization filter are both connected to the output port of the second processor, and the input ports of the coefficient registers of the N groups of linear filters are both connected to the output port of the third processor.

The first processor acquires the first transmission signal from the first memory, acquires the fifth transmission signal from the second memory, and acquires the third processed signal from the third memory. The first processor performs LS linear interpolation fitting according to the first transmitted signal, the fifth transmitted signal, and the third processed signal to obtain a filter coefficient FIR _ CH0 of the first channel filter and a filter coefficient FIR _ CH1 of the second channel filter. After the first processor acquires the FIR _ CH0 and the FIR _ CH1, the first processor downloads the FIR _ CH0 and the FIR _ CH1 to the coefficient register of the first channel filter and the coefficient register of the second channel filter, respectively.

Before the first equalization filter and the second equalization filter in the cascaded filter circuit work, the second processor tests the transmitting signal and the receiving signal of the duplexer (including the first transmitting duplexer and the receiving duplexer) to obtain two groups of group delay parameters or S parameters of the duplexer. And when the obtained data is the S parameter of the duplexer, the second processor converts the S parameter of the duplexer into a group delay parameter. And the second processor performs LS linear interpolation fitting according to the two groups of group delay parameters to obtain a filter coefficient DUP _ EQ1 of the first equalization filter and a filter coefficient DUP _ EQ2 of the second equalization filter. After the second processor 1152 acquires the DUP _ EQ1 and the DUP _ EQ2, the second processor downloads the DUP _ EQ1 and the DUP _ EQ2 to the coefficient register of the first equalizer filter and the coefficient register of the second equalizer filter, respectively.

Before the combiner of the V-network structure works, the third processor tests the channel combiner to obtain the S parameter of the combiner of the V-network structure. The third processor then derives frequency response information (shown here in fig. 4) of signals from P0 to H0, P0 to H1, P0 to H2.... P0 to H (M-1), P1 to H0, P1 to H1, and P1 to H2.. P1 to H (M-1), M being N/2, from the S parameter. The third processor adopts N groups of linear filters to respectively perform linear interpolation fitting on the N paths of responses to obtain the filter coefficients of the N groups of linear filters: HB _ FIR1, HB _ FIR2, HB _ FIRs 3. The third processor downloads the N filter coefficients to coefficient registers of N sets of linear filters, respectively.

The first channel filter and the second channel filter compensate for channel response inconsistencies, such as a delay difference and a phase difference, which are generated when the first transmission signal Ch0 and the second transmission signal Ch1 pass through different channels, so that the first filtered signal and the second filtered signal input by the PIM canceller respectively match the characteristics of the first, fourth, and eighth transmission signals input by the channel combiner. The first equalization filter and the second equalization filter are used for simulating the group delay unevenness characteristic of the transmitting duplexer. The N groups of linear filters are used for simulating the combination relation and the process of the combiner of the V network structure.

It should be noted that, for simplicity of description, the above-mentioned method embodiments are described as a series of acts or combination of acts, but those skilled in the art will recognize that the present invention is not limited by the order of acts, as some steps may occur in other orders or concurrently in accordance with the invention. Further, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that the acts and modules referred to are not necessarily required by the invention.

In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.

In the embodiments provided in the present application, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one type of division of logical functions, and there may be other divisions when actually implementing, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of some interfaces, devices or units, and may be an electric or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The above embodiments of the present invention are described in detail, and the principle and the implementation of the present invention are explained by applying specific embodiments, and the above description of the embodiments is only used to help understanding the method of the present invention and the core idea thereof; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in view of the above, the content of the present specification should not be construed as a limitation to the present invention.

Claims

1. A multi-channel passive intermodulation PIM digital cancellation circuit, comprising:

a first input/output port of the channel combiner is connected with a second input port of the duplexer, a second output port of the duplexer is connected with an input port of the third conversion circuit, an output port of the third conversion circuit is connected with a second input port of the first adder, and an output port of the first adder is an output port of the multi-channel PIM digital cancellation circuit;

wherein the first conversion circuit comprises: a first digital domain downlink, a first digital-to-analog converter, and a first analog domain downlink; the input port of the first digital domain downlink is the input port of the first conversion circuit, the output port of the first digital domain downlink is connected with the input port of the first digital-to-analog converter, the output port of the first digital-to-analog converter is connected with the input port of the first analog domain downlink, and the output port of the first analog domain downlink is the output port of the first conversion circuit;

alternatively, the second conversion circuit includes: a second digital domain downlink, a second digital-to-analog converter, and a second analog domain downlink; the input port of the second digital domain downlink is an input port of the second conversion circuit, the output port of the second digital domain downlink is connected with the input port of the second digital-to-analog converter, the output port of the second digital-to-analog converter is connected with the input port of the second analog domain downlink, and the output port of the second analog domain downlink is an output port of the second conversion circuit;

alternatively, the third conversion circuit includes: the device comprises a first analog-to-digital conversion circuit and an analog domain uplink; the input port of the analog domain uplink is the input port of the third conversion circuit, the output port of the analog domain uplink is connected with the input port of the first analog-to-digital converter, and the output port of the first analog-to-digital converter is the output port of the third conversion circuit.

2. The circuit of claim 1, wherein the cascaded filter circuit comprises:

3. The circuit of claim 1, wherein the duplexer comprises:

a first transmit duplexer and a receive duplexer;

4. The circuit of claim 1, wherein the feedback circuit comprises:

5. The circuit of claim 1 wherein the multi-channel PIM digital cancellation circuit further comprises a first data acquisition node U0, a second data acquisition node U1, and a third data acquisition node S0;

6. The circuit of claim 3, wherein the multi-channel PIM digital cancellation circuit further comprises a first coupling node P0 and a second coupling node P1;

7. The circuit of claim 2, wherein the multi-channel PIM digital cancellation circuit further comprises a first memory and a second memory;

8. The circuit of claim 7, wherein the multi-channel PIM digital cancellation circuit further comprises a processor comprising a first processor, a second processor, and a third processor;

9. The circuit of claim 8,

the multi-channel PIM digital cancellation circuit further comprises a first data acquisition node U0, a second data acquisition node U1 and a third data acquisition node S0;

the first data acquisition node U0 is located at an output port of the first frequency shift rate module, the second data acquisition node U1 is located at an output port of the second frequency shift rate module, the third data acquisition node S0 is located at an output port of the second digital domain downlink;

the first processor is used for storing the data collected from the first data collecting node U0 into the first memory;

10. The circuit of claim 9, wherein the first processor is further configured to:

11. The circuit of claim 9, wherein the second processor is further configured to:

acquiring S parameters of the duplexer;

12. The circuit of claim 9, wherein the third processor is further configured to:

obtaining an S parameter of the channel combiner;

13. A multi-channel passive intermodulation PIM digital cancellation circuit, comprising:

the feedback circuit includes:

14. A multi-channel passive intermodulation PIM digital cancellation circuit, comprising:

wherein the multi-channel PIM digital cancellation circuit further comprises a first memory and a second memory; the input port of the first memory is connected with the output port of the first frequency shift variable rate module, and the input port of the second memory is connected with the output port of the second frequency shift variable rate module.