CN111103492A - Multipath high-speed signal acquisition aging screening test bed - Google Patents
Multipath high-speed signal acquisition aging screening test bed Download PDFInfo
- Publication number
- CN111103492A CN111103492A CN201911408670.6A CN201911408670A CN111103492A CN 111103492 A CN111103492 A CN 111103492A CN 201911408670 A CN201911408670 A CN 201911408670A CN 111103492 A CN111103492 A CN 111103492A
- Authority
- CN
- China
- Prior art keywords
- circuit
- module
- signal connection
- aging
- speed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/003—Environmental or reliability tests
Landscapes
- Engineering & Computer Science (AREA)
- Environmental & Geological Engineering (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The invention belongs to the technical field of aging screening test equipment, and particularly relates to a multi-path high-speed signal acquisition aging screening test bed which comprises a control panel, wherein the control panel comprises an FPGA module, a leakage current sampling module, a DIO, a relay array switching circuit and a fuse detection circuit module, the leakage current sampling module comprises a high-speed ADC, an analog signal conditioning circuit, an IV conversion circuit and a calibration circuit, the aging panel is respectively in signal connection with the IV conversion circuit, the relay array switching circuit and the fuse detection circuit module, the signals of the relay array switching circuit and the fuse detection circuit module are respectively in signal connection with the DIO signal, the DIO is in signal connection with the FPGA module, the IV conversion circuit is sequentially in signal connection with the analog signal conditioning circuit, the high-speed ADC and the FPGA module, the high-speed ADC is in signal connection with the calibration circuit, and the calibration circuit is in signal.
Description
Technical Field
The invention belongs to the technical field of aging screening test equipment, and particularly relates to a multi-channel high-speed signal acquisition aging screening test bed.
Background
Reliability analysis is a measure of the ability of an electronic component to function without failure when placed into service. The service life of the electronic element is divided into an aging period, a service life period and a loss period. Wherein, the early failure exists in the aging period, and the failure rate is higher; the failure rate is more stable in the service life period; and the failure rate is higher during the wear period. The reliability screening test is to eliminate defective products caused by potential undesirable factors from a batch of products. After the early failure screening is eliminated, the failure rate of the product can be reduced by one to two orders of magnitude. At present, two test modes are mainly used in a high-temperature direct-current aging test of a capacitor, wherein the first mode is that samples are manually installed at high temperature, then electrode leads at two ends of each sample are led to the outside of a box body to be measured, and finally, each sample is manually measured and tested. The second method is to measure data of each station by a polling method, which is much more advanced than the first method, but because the data measurement integration requires time in the polling measurement process, and the station switching also requires time, all stations basically need 5 minutes for polling measurement once. As the capacitor requirements of military industry and aerospace level are very strict, and the screening quantity of products is very large, in order to improve the acquisition efficiency and fill the blank of the test tool in China, a high-speed acquisition test system is designed.
Disclosure of Invention
The purpose of the invention is: the utility model aims at providing a multichannel high speed signal gathers ageing screening test bench, 512 way high speed signal processing apparatus that comprises the FPGA chip, gather the leakage current of all stations in real time, and transmit to the host computer and carry out signal processing, because every ageing board is equipped with the high-speed data system that gathers of a set of special leakage current, realize quick leakage current collection, can realize the data monitoring of the time of every station 10ms intermittence, select unqualified product fast, realize screening the component in batches, shorten testing personnel's operating time, the work efficiency of enterprise is improved.
In order to achieve the technical purpose, the technical scheme adopted by the invention is as follows:
a multipath high-speed signal acquisition aging screening test bed comprises a case, a high-temperature test incubator, an upper computer system, an RS232 serial server, a power distribution plate, a control plate power supply and an aging plate, wherein the upper computer system is in signal connection with the RS232 serial server, the RS232 serial server is in signal connection with the power distribution plate, the control plate and the high-temperature test incubator respectively, the control plate is in signal connection with the aging plate, the RS232 serial server adopts an RS232 full duplex communication mode for communication, the upper computer system adopts a parallel communication network framework, the control plate comprises an FPGA module, a leakage current sampling module, a DIO, a relay array switching circuit and a fuse detection circuit module, the leakage current sampling module comprises a high-speed ADC (analog-to-digital converter), an IV switching circuit and a calibration circuit, the aging plate is in signal connection with the IV switching circuit, the relay array switching circuit and the fuse detection circuit module respectively, relay array switching circuit and fuse detection circuit module signal all with DIO signal connection, DIO and FPGA module signal connection, IV converting circuit in proper order with analog signal conditioning circuit, high-speed ADC and FPGA module signal connection, high-speed ADC and calibration circuit signal connection, calibration circuit and FPGA module signal connection, the FPGA module and RS232 serial port server signal connection.
By adopting the technical scheme, the control panel power supplies provide power for the control panel and the aging panel, the upper computer system is connected with the power distribution plate through the RS232 serial server, so that the control panel power is reasonably distributed to each control panel, the power distribution plate, the control panel and the high-temperature test incubator transmit detected signals to the upper computer system through the RS232 serial server, and the RS232 serial server adopts an RS232 full-duplex communication mode for communication, so that channels work independently and are matched with the upper computer system through a parallel communication network framework, and the detection interval time of the aging panel is shortened; the leakage current sampling module is used for acquiring leakage current signals of stations, a high-precision sampling resistor is arranged in the IV conversion circuit and used for acquiring and converting leakage current into voltage signals, the analog signal conditioning circuit is used for filtering and smoothing signals to accurately improve high-speed acquired data, the high-speed ADC is used for changing the acquired signals into digital signals in real time, the calibration circuit is used for providing a reference for sampling and providing reference calibration to ensure the accuracy of data acquisition, and the leakage current data of all the stations can be efficiently acquired in real time through the cooperation of the FPGA module, the high-speed ADC, the analog signal conditioning circuit, the IV conversion circuit and the calibration circuit; the DIO is a digital input/output circuit and is used for connecting a relay array and detecting a fuse detection circuit module, the relay array switching circuit achieves the purpose of array driving through the combination of a latch and a relay driving unit, the fuse detection circuit module can detect the on-off state of a station fuse in real time, and an FPGA module transmits collected signals to an upper computer system through an RS232 serial server.
Further defined, the FPGA module includes a crystal oscillator, a filter circuit, an auxiliary circuit, a power supply module, a MAX232 converter, an RS232, 10/100M adaptive PHY, an RJ45, and an FPGA core processor. Such structure, the power module provides normal working power supply for the FPGA module, the crystal oscillator provides the clock for it, filter circuit and auxiliary circuit cooperation make signal isolation and high frequency signal filter, avoid the interference of external signal to its work, MAX232 converter and 10/100M self-adaptation PHY are FPGA core processor and the interactive important channel of external data, RS232 and RJ45 are used for gathering the data transmission of FPGA module to RS232 serial port server, handle by upper computer system at last.
Further, the FPGA core processor includes AD control and caching, gain amplification control, and algorithm processing. With the structure, the collected data is processed by an algorithm and data in the FPGA core processor and is finally cached, so that the data collection is completed.
Further defined, the analog signal conditioning circuit includes a low pass filter, a programmable amplifier, and an input pre-processing circuit. The structure carries out front-end filtering through the input preprocessing circuit, carries out amplification operation on signals through the program control amplifier and carries out smooth filtering on the signals through the low-pass filter, processes analog signals and is convenient for the high-speed ADC to process data.
Further, the IV conversion circuit is in signal connection with the input preprocessing circuit, the program controlled amplifier, and the low pass filter in sequence, and the low pass filter is in signal connection with the high speed ADC. The structure is reasonable and convenient for signal processing.
Further, the FPGA module and the high-speed ADC are communicated and interacted in real time by adopting an I2C bus protocol.
Further limiting, the aging board is provided with thirty-two paths of clamp boards, and the control board is provided with an FPGA high-speed acquisition module, and thirty-two paths of DIO, thirty-two paths of fuse detection circuit modules, thirty-two paths of relay array switching circuits and thirty-two paths of leakage current sampling modules which are in one-to-one correspondence with the thirty-two paths of clamp boards. According to the structure, the aging board is provided with thirty-two stations and is independently controlled to control whether a test sample is connected into the loop or not, so that the test sample can be withdrawn from the loop when the sample is invalid or abnormal in the test process, and the samples at other stations cannot be influenced and burnt.
Further limiting, the number of the control board power supplies is four, the number of the control boards is sixteen, one control board power supply supplies power for the four control boards, the number of the aging boards is the same as that of the control boards, and the aging boards correspond to the control boards one by one. Such structure, the power supply is reasonable to sixteen passageways are constituteed to sixteen control panels, and the single channel has thirty two stations for total five hundred twelve stations can be detected at a high speed simultaneously, realize screening the component in batches, shorten test personnel's operating time, improve the work efficiency of enterprise
Further limit, the clamp plate is a primary and secondary clamp. By adopting the structure, only the sub-clamp needs to be replaced aiming at different clamps, so that the use is convenient.
Further limiting, the upper computer system adopts SQLite database independent data management. The structure facilitates the playback and storage of channel data through the management of the SQLite database.
Compared with the prior art, the invention has the following advantages:
1. the 512-channel high-speed signal processing device formed by the FPGA chip collects leakage currents of all stations in real time and transmits the leakage currents to the upper computer system for signal processing, data monitoring of 10ms intermittent time of each station can be achieved, unqualified products can be rapidly screened out, elements can be screened in batches, working time of testers is shortened, and working efficiency of enterprises is improved;
2. the single channel is 32 stations, so that the 32 relays are independently controlled to control whether a test sample is connected into the loop or not, the test sample can be withdrawn from the test loop when the sample fails or is abnormal in the test process, and the samples at other stations cannot be influenced and burnt;
3. the RS232 serial port server adopts an RS232 full duplex communication mode for communication, so that the channels work independently, and are matched with an upper computer system by adopting a parallel communication network framework, and the detection interval time of the aging board is shortened;
4. the clamp plate is a primary and secondary clamp, and only the secondary clamp needs to be replaced aiming at different clamps, so that the use is convenient;
5. through the management of the SQLite database, the channel data can be conveniently played back and stored.
Drawings
The invention is further illustrated by the non-limiting examples given in the accompanying drawings;
FIG. 1 is a schematic diagram of a signal connection structure of a control board of an embodiment of a multi-path high-speed signal acquisition aging screening test bed according to the present invention;
FIG. 2 is a schematic structural diagram of an FPGA module of an embodiment of the aging screening test bed for multi-channel high-speed signal acquisition of the present invention;
FIG. 3 is a schematic diagram of the working principle of collecting leakage current signals in an embodiment of the aging screening test bed for collecting multi-channel high-speed signals according to the present invention;
FIG. 4 is a schematic diagram of a signal connection structure of an embodiment of the aging screening test bed for multi-channel high-speed signal acquisition of the present invention;
Detailed Description
In order that those skilled in the art can better understand the present invention, the following technical solutions are further described with reference to the accompanying drawings and examples.
As shown in figures 1-4, a multi-channel high-speed signal acquisition aging screening test bed comprises a chassis, a high-temperature test incubator, a host computer system, an RS232 serial port server, a power distribution board, a control board power supply and an aging board, wherein the host computer system is in signal connection with the RS232 serial port server, the RS232 serial port server is in signal connection with the power distribution board, the control board and the high-temperature test incubator respectively, the control board is in signal connection with the aging board, the RS232 serial port server adopts an RS232 full duplex communication mode for communication, the host computer system adopts a parallel communication network framework, the control board comprises an FPGA module, a leakage current sampling module, a DIO, a relay array switching circuit and a fuse detection circuit module, the leakage current sampling module comprises a high-speed ADC, an analog signal conditioning circuit, an IV switching circuit and a calibration circuit, the aging board is in signal connection with the IV switching circuit, the relay, the relay array switching circuit and the fuse detection circuit module are in signal connection with DIO signals, the DIO is in signal connection with an FPGA module, the IV conversion circuit is in signal connection with an analog signal conditioning circuit, a high-speed ADC and the FPGA module in sequence, the high-speed ADC is in signal connection with a calibration circuit, the calibration circuit is in signal connection with the FPGA module, the FPGA module is in signal connection with an RS232 serial server, the FPGA module comprises a crystal oscillator, a filter circuit, an auxiliary circuit, a power supply module, an MAX232 converter, an RS232, 10/100M self-adaptive PHY, an RJ45 and an FPGA core processor, the FPGA core processor comprises AD control and cache, gain amplification control and algorithm processing, the analog signal conditioning circuit comprises a low-pass filter, a program-controlled amplifier and an input preprocessing circuit, the IV conversion circuit is in signal connection with the input preprocessing circuit, the program-controlled amplifier and the low-pass filter in sequence, and the, the FPGA module and the high-speed ADC are communicated in real time by adopting an I2C bus protocol, the aging board is provided with thirty-two paths of clamp boards, the control board is internally provided with an FPGA high-speed acquisition module and thirty-two paths of DIO which correspond to the thirty-two paths of clamp boards one by one, a thirty-two path fuse detection circuit module, a thirty-two path relay array switching circuit and thirty-two paths of leakage current sampling modules, the number of control board power supplies is four, the number of control boards is sixteen, one control board power supply supplies power for the four control boards, the number of the aging boards is the same as that of the control boards, the aging boards correspond to the control boards one by one, the upper computer system adopts an SQLite database to manage independent data, and.
By adopting the technical scheme, the control panel power supplies provide power for the control panel and the aging panel, the upper computer system is connected with the power distribution plate through the RS232 serial server, so that the control panel power is reasonably distributed to each control panel, the power distribution plate, the control panel and the high-temperature test incubator transmit detected signals to the upper computer system through the RS232 serial server, and the RS232 serial server adopts an RS232 full-duplex communication mode for communication, so that channels work independently and are matched with the upper computer system through a parallel communication network framework, and the detection interval time of the aging panel is shortened; the leakage current sampling module is used for acquiring leakage current signals of stations, a high-precision sampling resistor is arranged in the IV conversion circuit and used for acquiring and converting leakage current into voltage signals, the analog signal conditioning circuit is used for filtering and smoothing signals to accurately improve high-speed acquired data, the high-speed ADC is used for changing the acquired signals into digital signals in real time, the calibration circuit is used for providing a reference for sampling and providing reference calibration to ensure the accuracy of data acquisition, and the leakage current data of all the stations can be efficiently acquired in real time through the cooperation of the FPGA module, the high-speed ADC, the analog signal conditioning circuit, the IV conversion circuit and the calibration circuit; the system comprises a DIO (digital input/output) circuit, a relay array and a fuse detection circuit module, wherein the DIO circuit is used for connecting a relay array and detecting the fuse detection circuit module, the relay array switching circuit is combined with a relay driving unit through a latch so as to achieve the purpose of array driving, the fuse detection circuit module can detect the on-off state of a station fuse in real time, and an FPGA (field programmable gate array) module transmits an acquired signal to an upper computer system through an RS232 serial server; the power supply module provides a normal working power supply for the FPGA module, the crystal oscillator provides a clock for the FPGA module, the filter circuit and the auxiliary circuit are matched to isolate signals and filter high-frequency signals, so that interference of external signals on the work of the FPGA module is avoided, the MAX232 converter and the 10/100M self-adaptive PHY are important channels for interaction of the FPGA core processor and external data, and the RS232 and RJ45 are used for transmitting the data of the FPGA module to the RS232 serial server for collection and finally are processed by the upper computer system; the acquired data is processed by an algorithm and data in an FPGA core processor and is cached finally, so that data acquisition is completed; the input preprocessing circuit is used for front-end filtering, the programmable control amplifier is used for carrying out amplification operation on the signals, the low-pass filter is used for carrying out smooth filtering on the signals, and the analog signals are processed, so that the high-speed ADC is convenient to process data; the aging board is provided with thirty-two stations and is independently controlled to control whether a test sample is connected into the loop or not, so that the test sample can be withdrawn from the test loop when the sample fails or is abnormal in the test process, and the samples at other stations cannot be influenced and burnt; sixteen control panels form sixteen channels, and each single channel has thirty-two stations, so that five hundred and twelve stations can be simultaneously detected at high speed, elements can be screened in batches, the working time of testers is shortened, and the working efficiency of enterprises is improved; the primary and secondary clamps are used, and only the secondary clamp needs to be replaced aiming at different clamps, so that the use is convenient; through the management of the SQLite database, the channel data can be conveniently played back and stored.
The working principle of collecting the leakage current signal is that the leakage current signal is detected through an IV conversion circuit, the current-voltage conversion process of the signal is completed, then the current-voltage conversion process of the signal enters the front end of an input preprocessing circuit for filtering, then the signal enters a program control amplifier for carrying out amplification operation on the signal, the amplified signal is subjected to smooth filtering through a low-pass filter, data collection is completed through a high-speed ADC, the collected data is transmitted to an FPGA core processor through an I2C bus, and algorithm and data processing are carried out through internal AD control and cache, gain amplification control and algorithm processing.
The 512-channel high-speed signal processing device composed of the FPGA chip collects leakage current of all stations in real time and transmits the leakage current to the upper computer for signal processing, and each aging board is provided with a set of special leakage current high-speed collection data system, so that rapid leakage current collection is realized, data monitoring of 10ms intermittent time of each station can be realized, unqualified products are rapidly screened, elements are screened in batches, the working time of testers is shortened, and the working efficiency of enterprises is improved.
The foregoing embodiments are merely illustrative of the principles of the present invention and its efficacy, and are not to be construed as limiting the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. The utility model provides an ageing screening test platform of high-speed signal acquisition of multichannel, includes quick-witted case, high temperature test incubator, host computer system, RS232 serial servers, power distribution board, control panel power and ageing board, host computer system and RS232 serial servers signal connection, RS232 serial servers respectively with power distribution board, control panel and high temperature test incubator signal connection, control panel and ageing board signal connection, its characterized in that: the RS232 serial port server adopts an RS232 full duplex communication mode for communication, the upper computer system adopts a parallel communication network framework, the control panel comprises an FPGA module, a leakage current sampling module, a DIO, a relay array switching circuit and a fuse detection circuit module, the leakage current sampling module comprises a high-speed ADC, an analog signal conditioning circuit, an IV conversion circuit and a calibration circuit, the aging board is respectively connected with the IV conversion circuit, the relay array switching circuit and the fuse detection circuit module through signals, the relay array switching circuit and the fuse detection circuit module are in signal connection with DIO signals, the DIO is in signal connection with the FPGA module, the IV conversion circuit is in signal connection with the analog signal conditioning circuit, the high-speed ADC and the FPGA module in sequence, the high-speed ADC is in signal connection with the calibration circuit, the calibration circuit is in signal connection with the FPGA module, and the FPGA module is in signal connection with the RS232 serial server.
2. The multi-path high-speed signal acquisition aging screening test bed of claim 1, wherein: the FPGA module comprises a crystal oscillator, a filter circuit, an auxiliary circuit, a power supply module, a MAX232 converter, RS232, 10/100M self-adaptive PHY, RJ45 and an FPGA core processor.
3. The multi-path high-speed signal acquisition aging screening test bed of claim 2, wherein: the FPGA core processor comprises AD control and cache, gain amplification control and algorithm processing.
4. The multi-path high-speed signal acquisition aging screening test bed of claim 2, wherein: the analog signal conditioning circuit comprises a low-pass filter, a program-controlled amplifier and an input preprocessing circuit.
5. The multi-path high-speed signal acquisition aging screening test bed of claim 4, wherein: the IV conversion circuit is sequentially in signal connection with the input preprocessing circuit, the program control amplifier and the low-pass filter, and the low-pass filter is in signal connection with the high-speed ADC.
6. The multi-channel high-speed signal acquisition aging screening test bench of any one of claims 1-5, wherein: and the FPGA module and the high-speed ADC are communicated and interacted in real time by adopting an I2C bus protocol.
7. The multi-path high-speed signal acquisition aging screening test bed of claim 6, wherein: the aging board is provided with thirty-two clamp boards, and the control board is internally provided with an FPGA high-speed acquisition module, thirty-two DIO and thirty-two fuse detection circuit modules which correspond to the thirty-two clamp boards one by one, thirty-two relay array switching circuits and thirty-two leakage current sampling modules.
8. The multi-path high-speed signal acquisition aging screening test bed of claim 7, wherein: the number of the control board power supplies is four, the number of the control boards is sixteen, one control board power supply supplies power for the four control boards, the number of the aging boards is the same as that of the control boards, and the aging boards correspond to the control boards one by one.
9. The multi-channel high-speed signal acquisition aging screening test rig according to any one of claims 1-8, wherein: the clamp plate is a primary and secondary clamp.
10. The multi-path high-speed signal acquisition aging screening test bed of claim 9, wherein: and the upper computer system adopts the independent data management of the SQLite database.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911408670.6A CN111103492A (en) | 2019-12-31 | 2019-12-31 | Multipath high-speed signal acquisition aging screening test bed |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911408670.6A CN111103492A (en) | 2019-12-31 | 2019-12-31 | Multipath high-speed signal acquisition aging screening test bed |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN111103492A true CN111103492A (en) | 2020-05-05 |
Family
ID=70424113
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911408670.6A Pending CN111103492A (en) | 2019-12-31 | 2019-12-31 | Multipath high-speed signal acquisition aging screening test bed |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN111103492A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114584143A (en) * | 2022-05-06 | 2022-06-03 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Dynamic life test board and test method for analog-to-digital converter |
| CN117310561A (en) * | 2023-11-03 | 2023-12-29 | 广州赛睿检测设备有限公司 | Electrolytic capacitor test positive and negative connection detection method based on leakage current detection |
-
2019
- 2019-12-31 CN CN201911408670.6A patent/CN111103492A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114584143A (en) * | 2022-05-06 | 2022-06-03 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Dynamic life test board and test method for analog-to-digital converter |
| CN114584143B (en) * | 2022-05-06 | 2022-09-23 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Dynamic life test board and test method for analog-to-digital converter |
| CN117310561A (en) * | 2023-11-03 | 2023-12-29 | 广州赛睿检测设备有限公司 | Electrolytic capacitor test positive and negative connection detection method based on leakage current detection |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109617628B (en) | Multifunctional detection device and method for multi-meter-in-one acquisition equipment | |
| CN108508396B (en) | Multi-table-in-one acquisition equipment detection system and method | |
| CN204631150U (en) | Three-phase under-voltage protection relay function test macro | |
| CN111103492A (en) | Multipath high-speed signal acquisition aging screening test bed | |
| CN103344891B (en) | Method and device for locating partial discharge of high voltage cable | |
| CN108845281B (en) | Online comparison detection method for power quality monitoring device | |
| CN105785306A (en) | Voltage transformer on-line group calibration method and apparatus | |
| CN101482602A (en) | Detection analysis system of relay-protection tester | |
| CN104849582A (en) | System and method for overcurrent protection and voltage monitoring device burn-in test | |
| CN201527306U (en) | Dynamically detecting system for infrared focal plane detector component | |
| CN203178431U (en) | Full-automatic testing system for circuit boards | |
| CN203658527U (en) | An ultrasonic partial discharge detection device for high-voltage electrical equipment | |
| CN212134828U (en) | Multipath high-speed signal acquisition aging screening test bed | |
| CN114994503A (en) | Circuit board detection device | |
| CN105577297B (en) | Radio frequency active product tester and its test method and test system | |
| CN201600444U (en) | Voltage monitor intelligent verification platform | |
| CN105738849A (en) | Digital power quality detection system | |
| CN208937653U (en) | A kind of test fixture of track circuit trackside monitoring and maintenance system | |
| CN205176183U (en) | Detection apparatus for be used for laser instrument on -line measuring that ages | |
| CN112858786A (en) | Modular resistance voltage measuring device and method | |
| CN201653544U (en) | Laser ageing detection device | |
| CN112034362A (en) | Power battery multichannel synchronous detection board | |
| CN105425117A (en) | UHF partial discharge sensor accuracy detection system | |
| CN219978510U (en) | Device for consistency inspection of current transformer | |
| CN218675079U (en) | Third-order intermodulation test fixture |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |