CN111095508A - 半导体元件的安装构造以及半导体元件与基板的组合 - Google Patents

半导体元件的安装构造以及半导体元件与基板的组合 Download PDF

Info

Publication number
CN111095508A
CN111095508A CN201880058813.2A CN201880058813A CN111095508A CN 111095508 A CN111095508 A CN 111095508A CN 201880058813 A CN201880058813 A CN 201880058813A CN 111095508 A CN111095508 A CN 111095508A
Authority
CN
China
Prior art keywords
electrode
substrate
semiconductor element
metal
solder layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201880058813.2A
Other languages
English (en)
Inventor
小野关仁
福住志津
铃木直也
野中敏央
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Showa Denko Materials Co ltd
Original Assignee
Hitachi Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd filed Critical Hitachi Chemical Co Ltd
Publication of CN111095508A publication Critical patent/CN111095508A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H01L2224/13013—Shape in top view being rectangular or square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H01L2224/13014—Shape in top view being circular or elliptic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13113—Bismuth [Bi] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13116—Lead [Pb] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13199—Material of the matrix
    • H01L2224/132—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13201—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13211—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13199—Material of the matrix
    • H01L2224/132—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13201—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13213—Bismuth [Bi] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13199—Material of the matrix
    • H01L2224/132—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13238—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13239—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13199—Material of the matrix
    • H01L2224/132—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13238—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13244—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/13198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13199—Material of the matrix
    • H01L2224/132—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13238—Material of the matrix with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13247—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16148—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a bonding area protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/29386—Base material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009—Pre-treatment of the bump connector or the bonding area
    • H01L2224/81024—Applying flux to the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81444—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81447—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81455—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/8238—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/82385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

半导体元件的安装构造由具有元件电极的半导体元件与具有基板电极的基板经由所述元件电极与所述基板电极连接而成，该基板电极设于与所述半导体元件对置的一侧的面的与所述元件电极对置的位置，所述元件电极以及所述基板电极的一方是在前端部具有焊料层的第一突起电极，所述元件电极以及所述基板电极的另一方是在表面具有一个或两个以上的金属凸部的第一电极焊盘，所述第一电极焊盘所具有的所述金属凸部穿入所述第一突起电极所具有的所述焊料层，所述第一电极焊盘所具有的所述金属凸部的底部面积相对于所述第一电极焊盘的面积为70％以下、或者相对于在所述前端部具有焊料层的第一突起电极的所述焊料层的最大截面积为75％以下。

Description

半导体元件的安装构造以及半导体元件与基板的组合
技术领域
本发明涉及半导体元件的安装构造以及半导体元件与基板的组合。
背景技术
以往，作为将半导体元件安装于基板的方法，已知有使用金线等金属细线的引线键合连接方式。另一方面，为了应对针对半导体装置的小型化、轻薄化、高功能化、高集成化、高速化等的要求，正在推广经由被称作凸块的导电性突起将半导体元件与基板连接的倒装芯片连接方式(FC连接方式)。FC连接方式为了连接半导体元件与基板，被广泛用于BGA(Ball Grid Array：球栅阵列)、CSP(Chip Size Package：芯片尺寸封装)等。COB(Chip OnBoard：板上芯片封装)型的连接方式也相当于FC连接方式。另外，FC连接方式也被广泛用于连接半导体元件间的COC(Chip On Chip：芯片内建芯片)型的连接方式(例如参照专利文献1)。
为了应对半导体装置的进一步的小型化、轻薄化以及高功能化的要求，正在普及通过上述连接方式进行了层叠化以及多级化的芯片堆叠型封装以及POP(Package OnPackage：封装体叠层)。另外，TSV(Through-Silicon Via：硅通孔)方式也开始被广泛普及。这种层叠化以及多级化技术由于三维地配置半导体元件等，因此与二维地配置半导体元件等的方法相比，能够减小封装面积。特别是，TSV技术对于半导体的性能提高、噪声降低、安装面积的削减以及省电力化也是有效的，作为下一代的半导体布线技术而被关注。
在包括凸块或布线的连接部中使用了导电材料。作为导电材料的具体例，可列举焊料、锡、金、银、铜、镍以及含有多种这些物质的金属材料。若在构成连接部的金属的表面生成氧化膜、或附着氧化物等杂质，则要连接的电路部件间的连接性以及绝缘可靠性降低，存在损害采用上述连接方式的优点的隐患。作为抑制这种不良情况的方法，可列举在连接前对基板表面以及半导体元件的表面的至少一方施以OSP(Organic SolderabilityPreservatives：有机可焊性保护剂)处理中所使用的预焊剂、防锈处理剂等而进行预处理的方法。但是，在预处理后预焊剂、防锈处理剂等残留于连接部，也存在因残留的预焊剂、防锈处理剂等恶化而连接部的连接可靠性降低的情况。
另一方面，通过用半导体用粘合剂密封半导体元件与基板的连接部的方法，能够一并进行电路部件间的电连接和连接部的密封。因此，可抑制连接部中所使用的金属的氧化、杂质向连接部的附着等，能够保护连接部免受外部环境的影响。因而，能够有效地提高连接性、绝缘可靠性、作业性、生产性等。
另外，在用FC连接方式制造半导体装置时，有时源于半导体元件与基板的热膨胀系数之差或半导体元件彼此的热膨胀系数之差的热应力集中在连接部而引起连接不良。为了避免引发源于热膨胀系数之差的连接不良，用粘合剂组合物密封邻接的两个电路部件(半导体元件、基板等)的空隙是有效的。特别是，在半导体元件与基板中大多使用热膨胀系数不同的成分，因此要求利用粘合剂组合物密封半导体装置来提高耐热冲击性。
使用了粘合剂组合物的FC连接方式能够大致分为Capillary-Flow方式和Pre-Applied方式(例如，参照专利文献2～6)。Capillary-Flow方式是在半导体元件以及基板的连接后，通过毛细管现象在半导体元件以及基板间的空隙注入液状的粘合剂组合物的方式。Pre-Applied方式是在半导体元件以及基板的连接前，在对半导体元件或基板上供给了糊状或膜状的粘合剂组合物之后连接半导体元件与基板的方式。
另外，公开了一种半导体元件的安装构造，为了提高半导体元件的突起电极与安装用布线基板的电极焊盘的接合强度、使安装可靠性提高，将突起电极与金属凸部对位而将在元件面形成有所述突起电极的半导体元件接合于在绝缘基板的上表面的与所述突起电极对置的位置形成有设有所述金属凸部的电极焊盘的布线基板，其特征在于，所述金属凸部的顶部陷入所述突起电极，并且所述金属凸部的侧面与所述电极焊盘的上表面的所成的角度以及接合部中的所述金属凸部的侧面与所述突起电极的侧面的所成的角度为90°以上(例如，参照专利文献7)。
现有技术文献
专利文献
专利文献1：日本特开2008－294382号公报
专利文献2：日本特开2001－223227号公报
专利文献3：日本特开2002－283098号公报
专利文献4：日本特开2005－272547号公报
专利文献5：日本特开2006－169407号公报
专利文献6：日本特开2006－188573号公报
专利文献7：日本特开2003－45911号公报
发明内容
发明要解决的课题
一般来说，在使用了粘合剂组合物(底部填充材料)的Pre-Applied方式的半导体装置的制造中，进行底部填充材料向半导体元件与基板之间的赋予以及底部填充材料的加热固化。目前，在该方式中，按每一个半导体装置进行底部填充材料向半导体元件与基板之间的赋予以及底部填充材料的加热固化。因此，使用了现行的Pre-Applied方式的底部填充材料的半导体装置的制造的生产效率差，生产效率的提高成为重要课题。
另外，作为能够实现低成本化的FC连接方式，是使用了导电性糊剂的方式。该方式在半导体元件形成突起电极后，在突起电极的前端转印导电性糊剂，使基板电极与突起电极接触，从而获得电导通。该方式下的连接电阻取决于导电性糊剂的厚度、导电粒子的填充率等，通常与焊料连接相比连接电阻变高为课题。
为了解决该状况，考虑如下方法：在没有粘合剂组合物的状态下将半导体元件临时搭载于基板后，进行基于回流的统一焊料连接，用Capillary-Flow方式进行底部填充材料的赋予以及底部填充材料的加热固化。然而，伴随着近年来的半导体装置的小型化的发展，以存储器以及逻辑为代表的半导体元件的包括凸块或布线的连接部也在进行窄间距化。因此，在没有粘合剂组合物的状态下将半导体元件临时搭载于基板后，若通过回流进行焊料连接，则存在因加热工序即回流时的振动以及基板的处理而产生连接部的位置偏移的情况。另外，关于用TSV方式使半导体元件多层化，在临时搭载后半导体元件非常不稳定，因此基于相同的理由，若进行基于回流的统一焊料连接，则存在在连接部产生位置偏移的情况。因在连接部产生位置偏移，半导体元件与基板的连接精度恶化。
本发明的一方式是鉴于上述以往的情况而完成的，目的在于提供半导体元件与基板的连接精度优异的半导体元件的安装构造。另外，本发明的另一方式的目的在于提供不易产生半导体元件与基板的连接部中的位置偏移的半导体元件与基板的组合。
用来解决课题的手段
用于实现所述课题的具体方法如下所述。
＜1＞一种半导体元件的安装构造，由具有元件电极的半导体元件与具有基板电极的基板经由所述元件电极与所述基板电极连接而成，该基板电极设于所述基板的与所述半导体元件对置的一侧的面的与所述元件电极对置的位置，
所述元件电极以及所述基板电极的一方是在前端部具有焊料层的第一突起电极，
所述元件电极以及所述基板电极的另一方是在表面具有一个或两个以上的金属凸部的第一电极焊盘，
所述第一电极焊盘所具有的所述金属凸部穿入所述第一突起电极所具有的所述焊料层，
所述第一电极焊盘所具有的所述金属凸部的底部面积相对于在所述前端部具有焊料层的第一突起电极的所述焊料层的最大截面积为75％以下。
＜2＞如＜1＞所述的半导体元件的安装构造，其中，
在所述半导体元件的和与所述基板对置的一侧相反的一侧，一个或两个以上的其他半导体元件以各半导体元件彼此经由元件电极连接的状态层叠，
在处于连接关系的两个半导体元件中，一个半导体元件所具有的元件电极以及另一个半导体元件所具有的元件电极的一方是在前端部具有焊料层的第二突起电极，
一个半导体元件所具有的元件电极以及另一个半导体元件所具有的元件电极的另一方是在表面具有一个或两个以上的金属凸部的第二电极焊盘，
所述第二电极焊盘所具有的所述金属凸部穿入所述第二突起电极所具有的所述焊料层，
所述第二电极焊盘所具有的所述金属凸部的底部面积相对于在所述前端部具有焊料层的第二突起电极的所述焊料层的最大截面积为75％以下。
＜3＞如＜1＞或＜2＞所述的半导体元件的安装构造，其中，
所述金属凸部的形状为圆柱或立方体。
＜4＞如＜1＞～＜3＞中任一项所述的半导体元件的安装构造，其中，
所述金属凸部形成为在高度方向上至少重叠有两个圆柱或立方体的形状。
＜5＞如＜1＞～＜4＞中任一项所述的半导体元件的安装构造，其中，所述金属凸部使用光刻法而形成。
＜6＞如＜1＞～＜5＞中任一项所述的半导体元件的安装构造，其中，
通过加压，以所述第一电极焊盘所具有的所述金属凸部的至少一部分穿入所述第一突起电极所具有的所述焊料层的状态，将所述半导体元件与所述基板临时固定，通过加热，使所述第一突起电极所具有的所述焊料层熔融而将所述元件电极与所述基板电极连接，从而获得所述半导体元件的安装构造。
＜7＞一种半导体元件与基板的组合，包括：半导体元件，具有元件电极；以及基板，具有基板电极，该基板电极设于所述基板的与所述半导体元件对置一侧的面的与所述元件电极对置的位置，
所述元件电极以及所述基板电极的一方是在前端部具有焊料层的突起电极，
所述元件电极以及所述基板电极的另一方是在表面具有一个或两个以上的金属凸部的电极焊盘，
所述金属凸部的底部面积相对于在所述前端部具有焊料层的突起电极的所述焊料层的最大截面积为75％以下。
＜8＞一种半导体元件的安装构造，由具有元件电极的半导体元件与具有基板电极的基板经由所述元件电极与所述基板电极连接而成，该基板电极设于所述基板的与所述半导体元件对置的一侧的面的与所述元件电极对置的位置，
所述元件电极以及所述基板电极的一方是在前端部具有焊料层的第一突起电极，
所述元件电极以及所述基板电极的另一方是在表面具有一个或两个以上的金属凸部的第一电极焊盘，
所述第一电极焊盘所具有的所述金属凸部穿入所述第一突起电极所具有的所述焊料层，
所述第一电极焊盘所具有的所述金属凸部的底部面积相对于所述第一电极焊盘的面积为70％以下。
＜9＞如＜8＞所述的半导体元件的安装构造，其中，
在所述半导体元件的和与所述基板对置的一侧相反的一侧，一个或两个以上的其他半导体元件以各半导体元件彼此经由元件电极连接的状态层叠，
在处于连接关系的两个半导体元件中，一个半导体元件所具有的元件电极以及另一个半导体元件所具有的元件电极的一方是在前端部具有焊料层的第二突起电极，
一个半导体元件所具有的元件电极以及另一个半导体元件所具有的元件电极的另一方是在表面具有一个或两个以上的金属凸部的第二电极焊盘，
所述第二电极焊盘所具有的所述金属凸部穿入所述第二突起电极所具有的所述焊料层，
所述第二电极焊盘所具有的所述金属凸部的底部面积相对于所述第二电极焊盘的面积为70％以下。
＜10＞如＜8＞或＜9＞所述的半导体元件的安装构造，其中，
所述金属凸部的形状为圆柱或立方体。
＜11＞如＜8＞～＜10＞中任一项所述的半导体元件的安装构造，其中，
所述金属凸部形成为，在高度方向上至少重叠有两个圆柱或立方体的形状。
＜12＞如＜8＞～＜11＞中任一项所述的半导体元件的安装构造，其中，
所述金属凸部使用光刻法而形成。
＜13＞如＜8＞～＜12＞中任一项所述的半导体元件的安装构造，其中，
通过加压，以所述第一电极焊盘所具有的所述金属凸部的至少一部分穿入所述第一突起电极所具有的所述焊料层的状态，将所述半导体元件与所述基板临时固定，通过加热，将所述第一突起电极所具有的所述焊料层熔融而将所述元件电极与所述基板电极连接，从而获得半导体元件的安装构造。
＜14＞一种半导体元件与基板的组合，包括：半导体元件，具有元件电极；以及基板，具有基板电极，该基板电极设于所述基板的与所述半导体元件对置的一侧的面的与所述元件电极对置位置，
所述元件电极以及所述基板电极的一方是在前端部具有焊料层的突起电极，
所述元件电极以及所述基板电极的另一方是在表面具有一个或两个以上的金属凸部的电极焊盘，
所述金属凸部的底部面积相对于所述电极焊盘的面积为70％以下。
发明效果
根据本发明的一方式，能够提供半导体元件与基板的连接精度优异的半导体元件的安装构造。另外，根据本发明的另一方式，能够提供不易产生半导体元件与基板的连接部中的位置偏移的半导体元件与基板的组合。
附图说明
图1A是表示连接半导体元件以及基板前的状态的主要部分剖面图。
图1B是表示连接半导体元件以及基板前的状态的俯视图。
图2是表示将半导体元件临时搭载于基板的状态的主要部分剖面图。
图3是表示连接半导体元件以及基板之后的状态的主要部分剖面图。
具体实施方式
以下，参照附图对应用了本发明的半导体元件的安装构造以及半导体元件与基板的组合的一例进行详细说明。但是，本发明并不限定于以下的公开。在以下的公开中，除了特别明示的情况以外，其构成要素(也包括要素步骤等)不是必须的。关于数值及其范围也相同，并不是限制本发明。另外，各图中的部件的大小是概念性的，部件间的大小的相对关系并不限定于此。
在本说明书中，在“工序”这一用语中，除了与其他工序独立的工序以外，即使在无法与其他工序明确区分的情况下，只要可实现该工序的目的，则也包括该工序。
在本说明书中，在使用“～”表示的数值范围内，“～”的前后所记载的数值分别作为最小值以及最大值而被包含。
在本公开中阶段性地记载的数值范围内，在一个数值范围内记载的上限值或下限值也可以置换为其他阶段性地记载的数值范围的上限值或下限值。另外，在本公开中记载的数值范围内，该数值范围的上限值或下限值也可以置换为实施例所示的值。
在本公开中，各成分也可以含有多种相应的物质。
在本公开中，在“层”或“膜”这一用语中，当观察该层或膜所存在的区域时，除了形成于该区域的整体的情况以外，还包括仅形成于该区域的一部分的情况。
在本公开中，“层叠”这一用语表示对层进行层叠，可以是结合二个以上的层，也可以为能够拆装二个以上的层。
＜半导体元件的安装构造＞
本公开的第一半导体元件的安装构造，由具有元件电极的半导体元件与具有基板电极的基板经由所述元件电极与所述基板电极连接而成，该基板电极设于所述基板的与所述半导体元件对置的一侧的面的与所述元件电极对置的位置，所述元件电极以及所述基板电极的一方是在前端部具有焊料层的第一突起电极，所述元件电极以及所述基板电极的另一方是在表面具有一个或两个以上的金属凸部的第一电极焊盘，所述第一电极焊盘所具有的所述金属凸部穿入所述第一突起电极所具有的所述焊料层，所述第一电极焊盘所具有的所述金属凸部的底部面积相对于在所述前端部具有焊料层的第一突起电极的所述焊料层的最大截面积设为75％以下。
另外，本公开的第二半导体元件的安装构造，由具有元件电极的半导体元件与具有基板电极的基板经由所述元件电极与所述基板电极连接而成，该基板电极设于所述基板的与所述半导体元件对置的一侧的面的与所述元件电极对置的位置，所述元件电极以及所述基板电极的一方是在前端部具有焊料层的第一突起电极，所述元件电极以及所述基板电极的另一方是在表面具有一个或两个以上的金属凸部的第一电极焊盘，所述第一电极焊盘所具有的所述金属凸部穿入所述第一突起电极所具有的所述焊料层，所述第一电极焊盘所具有的所述金属凸部的底部面积相对于所述第一电极焊盘的面积设为70％以下。
在本公开中，有时将第一半导体元件的安装构造以及第二半导体元件的安装构造合起来称作“半导体元件的安装构造”。
在本公开中，第一突起电极以及第一电极焊盘构成有助于半导体元件与基板的连接的元件电极或基板电极。另外，后述的第二突起电极以及第二电极焊盘构成有助于半导体元件彼此的连接的元件电极。以下，在本公开中，有时将第一突起电极以及第二突起电极合起来而简单称作突起电极。另外，有时将第一电极焊盘以及第二电极焊盘合起来而简单称作电极焊盘。
根据本公开的半导体元件的安装构造，可获得半导体元件与基板的连接精度优异的半导体元件的安装构造。其理由并不明确，但推测如下。
在本公开的半导体元件的安装构造中，半导体元件与基板经由元件电极与基板电极而连接。在此，元件电极以及基板电极的一方是在前端部具有焊料层的突起电极，元件电极以及基板电极的另一方是在表面具有一个或两个以上的金属凸部的电极焊盘。在将半导体元件与基板连接的情况下，在半导体元件被临时搭载于基板之后供于回流等加热工序。在将半导体元件临时搭载于基板时，金属凸部被按压于焊料层，因此金属凸部的前端的至少一部分成为穿入焊料层的状态。焊料与其他金属材料相比熔融温度低且硬度也低，因此金属凸部的前端的至少一部分容易穿入焊料层。通过金属凸部的前端的至少一部分穿入焊料层，临时搭载于基板的半导体元件容易被临时固定于基板上。因此，在处理临时搭载有半导体元件的基板时，被临时搭载的半导体元件不易因回流等加热工序中的振动等而从基板脱落，不易产生半导体元件的位置偏移。因此，推测本公开的半导体元件的安装构造的半导体元件与基板的连接精度优异。本公开的半导体元件的安装构造尤其对具有被窄间距化的连接部的半导体元件的安装构造是有效的。
另外，在本公开中，“连接”是指半导体元件以及基板或半导体元件彼此经由电极(即，元件电极或基板电极)而物理连接。
作为连接半导体元件与基板的方法，并未特别限制。从生产效率的观点出发，可列举如下方法：通过加压，以所述第一电极焊盘所具有的所述金属凸部的至少一部分穿入所述第一突起电极所具有的所述焊料层的状态，将所述半导体元件与所述基板临时固定，通过加热，使所述第一突起电极所具有的所述焊料层熔融而将所述元件电极与所述基板电极连接。
更具体而言，使突起电极与电极焊盘对位，在突起电极的前端部的焊料层与电极焊盘的表面的一个或两个以上的金属凸部接触的状态下进行加压。由此，电极焊盘的金属凸部的顶部穿入突起电极的焊料层而半导体元件被临时搭载于基板。之后，能够使用以回流为代表的加热装置，使构成焊料层的焊料熔融，使突起电极与电极焊盘焊料连接。
在将半导体元件临时搭载于基板时，为了提高焊料的润湿性、使连接可靠，也可以对突起电极以及电极焊盘的至少一方赋予助焊剂。
在焊料层与金属凸部接触的状态下进行加压时所施加的压力的大小并未特别限定。与一般的倒装芯片的安装工序相同，能够考虑突起电极的数量、突起电极的高度的偏差、由加压导致的突起电极或基板上的布线的变形量等而进行设定。具体而言，例如，优选设定为，每一个突起电极受到的负载为1gf(0.0098N)～20gf(0.196N)左右。另外，例如，优选设定为施加于一个半导体元件的负载为5N～200N左右。
若每一个突起电极受到的负载为0.0098N以上、或施加于半导体元件的负载为5N以上，则有半导体元件的临时固定力充分而不易产生后段的工序中的半导体元件的位置偏移的倾向。若每一个突起电极受到的负载为0.196N以下、或施加于半导体元件的负载为200N以下，则有可抑制因负载过大而导致的半导体元件的损伤的产生的倾向。
也可以在焊料层与金属凸部接触的状态下进行加压时，对基板以及半导体元件的至少一方进行加热。关于加热温度，从生产性以及由输送装置输送半导体元件时的处理性的观点出发，优选以焊料不熔融的温度进行，优选以210℃以下的温度进行，更优选以200℃以下的温度进行。
半导体元件的种类并未特别限制，能够使用由硅、锗等同一种类的元素构成的元素半导体、砷化镓、磷化铟等化合物半导体等。还能够列举：未被树脂等封装的芯片(裸片)其本身；被树脂等封装的被称作CSP、BGA(Ball Grid Array：球栅阵列)等的半导体封装等。另外，半导体元件也可以是沿高度方向以及平面方向的至少一方配置多个半导体元件的构成。在沿高度方向配置多个半导体元件的情况下，多个半导体元件也可以通过TSV来连接。
作为突起电极，若在前端部具有焊料层，则不特别限定。作为突起电极，也可以是金属柱与设于金属柱的前端的焊料层的组合。具有焊料层的突起电极的材质除了具有焊料以外，并未特别限制，能够从通常所使用的材质中进行选择。
突起电极的间隔优选为1μm～100μm，更优选为10μm～70μm，进一步优选为30μm～50μm。
焊料层的厚度优选为0.1μm～50μm，更优选为1μm～30μm，进一步优选为5μm～20μm。若焊料层的厚度为0.1μm以上，则能够充分确保金属凸部向焊料层的穿入量，临时固定力不易变小，因此有不易产生后段的工序中的位置偏移的倾向。若焊料层的厚度为50μm以下，则有用于使焊料层熔融而将元件电极与基板电极连接的处理时间不易变长的倾向。另外，有不易产生将元件电极与基板电极连接时的邻接的电极间的电短路的倾向。
在突起电极为具有金属柱与设于金属柱的前端的焊料层的构成的情况下，具有以金、银、铜、锡、镍等为主要成分的金属层的金属柱例如也可以通过镀覆形成。构成金属柱的金属层既可以含有单一成分，也可以含有多种成分。另外，金属层可以是单层构造，也可以是层叠有多个金属层的层叠构造。作为金属柱的材质，由于电阻小且耐蝕性相对较高，因此能够优选使用铜。
作为焊料层的焊料材料，能够使用锡－银系焊料、锡－铅系焊料、锡－铋系焊料、锡－铜系焊料、金－铜系焊料、锡－银－铜系焊料等，从环境问题以及安全性的观点出发，能够优选使用金－铜系焊料、锡－铜系焊料、锡－铋系焊料、锡－银系焊料、锡－银－铜系焊料等无铅焊料。
在铜制的金属柱上形成焊料层的情况下，从提高连接可靠性的观点出发，也可以为了抑制金属成分间的扩散而在铜制的金属柱与焊料层之间形成镍层。另外，为了使电极焊盘的金属凸部容易穿入焊料层，也可以在由镀覆、印刷等在焊料层形成突起电极后，不对焊料层进行加热处理。
基板的种类并未特别限制，能够列举：FR4、FR5等含有纤维基材的有机基板；不含有纤维基材的积层型(build up)的有机基板；聚酰亚胺、聚酯等有机膜；在含有氧化铝、玻璃、硅等无机材料的基材等上形成有包括连接用的电极的导体布线的布线板。在基板上，也可以通过半加成法(semi–additive process)、减成法(subtractive process)等方法形成电路、基板电极等。
基板也可以是硅(Si)。硅(Si)制的基板的尺寸、厚度等并未被限制。作为硅(Si)制的基板，能够列举在表面形成有包括连接用的电极的导体布线的晶片。另外，在硅(Si)制的基板上，也可以形成有布线、晶体管、其他电子元件、贯通电极(TSV)等。
金属凸部也可以使用光刻法而形成。
在使用光刻技术在电极焊盘的表面形成金属凸部的情况下，能够经过如下工艺而形成：对残留有晶种层的电极焊盘面赋予感光性的光致抗蚀剂，进行曝光、显影、镀覆，剥离光致抗蚀剂，蚀刻晶种层。关于形成金属凸部的方法，并不限定于上述方法。
作为形成金属凸部的方法，除了使用光刻法形成的方法以外，也能够使用如下方法：利用球形焊接器将金、铜等金属线焊接于电极焊盘上、形成柱状、并以特定的长度进行切割的方法，使用3D打印机来形成的方法，通过切削加工形成的方法等。
金属凸部的材质并未特别限制，也可以使用铜、镍等各种金属。在金属凸部的材质中使用了铜的情况下，能够获得具备具有散热效果的连接电阻少的连接部的半导体元件的安装构造。
另外，为了使电极间的连接可靠，也可以在金属凸部的表面实施金镀覆、镍/金镀覆、OSP(Organic Solderability Preservatives：有机可焊性保护剂)处理等。作为OSP的市售品，可列举四国化成工业株式会社的耐热型水溶性预焊剂Tafuesu(日文：タフエース)F2(LX)PK等。
金属凸部的形状并未特别限定。作为金属凸部的形状，可列举圆柱、立方体、三棱柱等。
在将金属凸部的形状设为圆柱或立方体时，金属凸部的顶部与被这些顶部穿入而塑性变形的突起电极的前端部的焊料层相互良好地啮合。因此，相对于回流处理时的外力也能够获得足够的强度，有能够进一步抑制连接部的位置偏移的产生的倾向。
另外，金属凸部也可以设为在高度方向上至少重叠两个圆柱、立方体、三棱柱等的形状。在该情况下，优选的是，相对于电极焊盘的表面设于最上层的圆柱、立方体、三棱柱等的底部面积比相对于电极焊盘的表面设于最下层的圆柱、立方体、三棱柱等的底部面积小。由此，使得金属凸部的顶部容易穿入突起电极的焊料层，金属凸部与突起电极的焊料层的啮合变得良好，有相对于回流处理时的外力的强度变高而更不易产生位置偏移的倾向。
从向焊料层穿入的容易性出发，作为金属凸部的形状，优选圆柱或立方体。
另外，金属凸部也可以是在高度方向上至少重叠两个圆柱或立方体的形状。
另外，电极焊盘也可以在表面具有两个以上的金属凸部。在表面上具有两个以上的金属凸部的情况下，各金属凸部的形状既可以相同也可以不同。
电极焊盘中的金属凸部的高度优选为突起电极的焊料层的厚度以下。通过将金属凸部的高度设为焊料层的厚度以下，使得金属凸部容易穿入焊料层。金属凸部尽可能深地穿入焊料层更能增大强度，有能够抑制连接部的位置偏移的倾向。金属凸部的高度并未特别限定，从能够增大金属凸部向焊料层的穿入量的观点以及工业生产性的观点出发，优选为0.1μm～50μm，更优选为0.5μm～30μm，进一步优选为1μm～10μm。为了提高基于焊料熔融的金属凸部与突起电极的连接形成时的焊料的润湿性，也能够在金属凸部的最表面形成以金为主要成分的含金层。含金层的形成方法并未特别限定，能够使用镀覆、溅射等方法。
在本公开的第一半导体元件的安装构造中，为了使电极焊盘的金属凸部穿入突起电极的焊料层，金属凸部的底部面积相对于突起电极的焊料层的最大截面积设为75％以下，优选为70％以下，更优选为50％以下，进一步优选为40％以下。若金属凸部的底部面积相对于突起电极的焊料层的最大截面积为75％以下，则金属凸部穿入突起电极的焊料层变得容易，可抑制连接部的位置偏移。另外，从能够防止金属凸部穿入突起电极的焊料层时的金属凸部的折断、倾倒等的观点出发，金属凸部的底部面积相对于突起电极的焊料层的最大截面积优选为5％以上，更优选为10％以上。在本公开中，焊料层的最大截面积是指，从高度方向观察突起电极时的焊料层的面积。
另外，在本公开的第二半导体元件的安装构造中，为了使电极焊盘的金属凸部穿入突起电极的焊料层，金属凸部的底部面积相对于电极焊盘的面积设为70％以下，优选为50％以下，更优选为40％以下。若金属凸部的底部面积相对于电极焊盘的面积为70％以下，则金属凸部穿入突起电极的焊料层变得容易，可抑制连接部的位置偏移。另外，金属凸部的底部面积相对于电极焊盘的面积可以为5％以上，也可以为10％以上。
金属凸部的底部面积是指，从高度方向观察金属凸部时的该金属凸部所占的面积。另外，在金属凸部为在高度方向上重叠有圆柱、立方体、三棱柱等的形状的情况下，金属凸部的底部面积是指，设于最下层的圆柱、立方体、三棱柱等的底部面积。另外，在电极焊盘在表面具有两个以上的金属凸部的情况下，金属凸部的底部面积是指，各金属凸部的底部面积的合计。
在本公开的第二半导体元件的安装构造中，相对于从高度方向观察突起电极时的焊料层的面积(焊料层的最大截面积)的金属凸部的底部面积可以为75％以下，可以为70％以下，可以为50％以下，也可以为40％以下。另外，相对于从高度方向观察突起电极时的焊料层的面积的金属凸部的底部面积可以为5％以上，可以为10％以上，也可以为15％以上。
在本公开的半导体元件的安装构造中，也可以在半导体元件的和与基板对置的一侧相反的一侧，一个或两个以上的其他半导体元件以各半导体元件彼此经由元件电极连接的状态层叠。在层叠多个半导体元件的情况下，在处于连接关系的两个半导体元件中，一个半导体元件所具有的元件电极以及另一个半导体元件所具有的元件电极的一方是在前端部具有焊料层的第二突起电极，一个半导体元件所具有的元件电极以及另一个半导体元件所具有的元件电极的另一方是在表面具有一个或两个以上的金属凸部的第二电极焊盘，第二电极焊盘所具有的金属凸部穿入第二突起电极所具有的焊料层，第二电极焊盘所具有的金属凸部的底部面积相对于在前端部具有焊料层的第二突起电极的焊料层的最大截面积为75％以下、或者第二电极焊盘所具有的金属凸部的底部面积相对于第二电极焊盘的面积也可以为70％以下。
第二电极焊盘所具有的金属凸部的底部面积相对于在前端部具有焊料层的第二突起电极的焊料层的最大截面积可以为70％以下，可以为50％以下，也可以为40％以下。另一方面，第二电极焊盘所具有的金属凸部的底部面积相对于在前端部具有焊料层的第二突起电极的焊料层的最大截面积可以为5％以上，可以为10％以上，也可以为15％以上。
另外，第二电极焊盘所具有的金属凸部的底部面积相对于第二电极焊盘的面积可以为50％以下，也可以为40％以下。另一方面，第二电极焊盘所具有的金属凸部的底部面积相对于第二电极焊盘的面积可以为5％以上，可以为10％以上，也可以为15％以上。
层叠多个半导体元件的情况下的突起电极以及电极焊盘的详细情况、以及用于连接突起电极与电极焊盘的方法的详细情况如上所述。
接下来，参照附图，对本公开的半导体元件的安装构造及其制造方法的具体例进行说明。但是，本发明并不限定于这些方式。另外，在各附图中示出了突起电极与电极焊盘的金属凸部的连接部附近的主要部分。
图1A是表示连接半导体元件以及基板前的状态的主要部分剖面图，图1B是表示连接半导体元件以及基板前的基板的状态的俯视图，图2是表示将半导体元件临时搭载于基板的状态的主要部分剖面图，图3是表示连接半导体元件以及基板之后的状态的主要部分剖面图。另外，在以下的附图中，对元件电极为突起电极、基板电极为电极焊盘的构成进行说明，但本公开并不限定于此，也可以是元件电极为电极焊盘、基板电极为突起电极的构成。
在图1A、图1B、图2以及图3中，附图标记1表示包括未图示的电极焊盘的半导体元件，附图标记2表示形成于半导体元件1的元件面的电极焊盘上的由铜等金属构成的金属柱(支柱)，附图标记3表示设于金属柱2的前端部的焊料层。在图1A中，由金属柱2以及焊料层3构成突起电极。另外，附图标记6表示基板，附图标记4表示形成于基板6的表面的与突起电极对置的位置的电极焊盘，附图标记5表示设于电极焊盘4的表面的金属凸部。突起电极形成于半导体元件的元件面，电极焊盘4形成于基板6的表面的与突起电极对置的位置。
首先，如图1A所示，进行半导体元件1的突起电极与设于与突起电极对置的电极焊盘4的金属凸部5的对位。接着，如图2所示，在突起电极与具有金属凸部5的电极焊盘4对置的状态下进行加压，使电极焊盘4的金属凸部5穿入突起电极的焊料层3而临时搭载。
之后，在将半导体元件1临时搭载于基板6的状态下，使用以回流为代表的加热装置，使焊料层3熔融，使半导体元件1的突起电极(元件电极)与基板6的具有金属凸部5的电极焊盘4(基板电极)焊料连接。通过经过以上的工序，制造如图3所示的金属凸部5穿入焊料层3的半导体元件的安装构造。
也可以在焊料连接完成后，进行用树脂材料填埋半导体元件与基板之间的密封。有时通过使用与制作物的构造、使用环境等相匹配的适当的密封树脂材料，能够提高制作物的使用环境下的动作的可靠性。树脂密封的方法并未限定，能够使用在半导体元件与基板之间流入液状树脂材料的毛细管底部填充工艺、在模塑工序中流入液状树脂、熔融的颗粒状树脂等的模具底部填充工艺等。也能够使用在液状树脂中添加由二氧化硅、氧化铝、氮化硅、氮化硼等无机材料、有机材料等构成的粒子的方法。若使用氧化铝、氮化硅、氮化硼等粒子，则能够提高树脂材料的热传导率，在使用发热量多的半导体元件的情况下，能够提高散热特性，有能够提高半导体的动作的稳定性的倾向。
＜半导体元件与基板的组合＞
本公开的第一半导体元件与基板的组合，包括：半导体元件，具有元件电极；以及基板，具有基板电极，该基板电极设于所述基板的与所述半导体元件对置一侧的面的与所述元件电极对置的位置，所述元件电极以及所述基板电极的一方是在前端部具有焊料层的突起电极，所述元件电极以及所述基板电极的另一方是在表面具有一个或两个以上的金属凸部的电极焊盘，所述金属凸部的底部面积相对于在所述前端部具有焊料层的突起电极的所述焊料层的最大截面积设为75％以下。
另外，本公开的第二半导体元件与基板的组合，包括：半导体元件，具有元件电极；以及基板，具有基板电极，该基板电极设于所述基板的与所述半导体元件对置的一侧的面的与所述元件电极对置的位置，所述元件电极以及所述基板电极的一方是在前端部具有焊料层的突起电极，所述元件电极以及所述基板电极的另一方是在表面具有一个或两个以上的金属凸部的电极焊盘，所述金属凸部的底部面积相对于所述电极焊盘的面积设为70％以下。
在本公开中，有时将第一半导体元件与基板的组合以及第二半导体元件与基板的组合合起来称作“半导体元件与基板的组合”。
也可以通过使用本公开的半导体元件与基板的组合来制造本公开的半导体元件的安装构造。
本公开的半导体元件与基板的组合中所含的半导体元件、基板、电极焊盘、突起电极等的详细情况与本公开的半导体元件的安装构造的情况相同。
另外，以上只不过是本公开的实施方式的例示，本公开并不限定于这些，可以在不脱离本公开的主旨的范围内施加各种变更以及改进。
【实施例】
以下，通过实施例对本发明进行具体说明，但本发明并不限定于这些实施例。
[实施例1]
作为半导体元件，准备了具有铝布线的、尺寸为10mm×8mm、厚度为725μm的硅芯片(株式会社WALTS，商品名“WALTS－TEG WM40－0102JY”，突起电极(凸块)：Sn－Ag系焊料，凸块焊料厚度：8μm，凸块间隔：40μm，铜支柱的高度：15μm，凸块尺寸：
Figure BDA0002406956360000171
)。
在硅晶片上，在与“WALTS－TEG WM40－0102JY”的凸块位置对置的位置，使用半加成法，用直径26μm、厚度2μm的镀覆铜形成了电极焊盘。此时，不蚀刻晶种层。接着，在所制作的电极焊盘的表面，同样地使用半加成法，制作纵20μm、横3μm、高度5μm的金属凸部，最后，蚀刻电极焊盘的晶种层，制作了具有金属凸部的电极焊盘。将其切割成10mm×8mm而制作基板，并将其用于评价。
接着，以使硅芯片的具有凸块的面朝向基板侧、凸块与基板接触的方式，利用加压用部件从硅芯片之上以100N的负载进行加压，使基板的金属凸部穿入凸块的焊料层。此时，在对硅芯片的凸块赋予助焊剂之后进行了加压。如此，制作了临时搭载有硅芯片(半导体元件)的基板。
使上述临时搭载有硅芯片的基板通过IR回流炉(株式会社村田制作所，商品名“TNP225－337EM”)，将焊料熔融，将硅芯片的凸块焊料连接于基板。另外，以使IR回流炉内的加热最高温度为260℃的方式设定了温度分布。
[实施例2]
在硅晶片上，在与“WALTS－TEG WM40－0102JY”的凸块位置对置的位置，使用半加成法，用直径26μm、厚度2μm的镀覆铜形成了电极焊盘。此时，不蚀刻晶种层。接着，在所制作的电极焊盘的表面上，同样地使用半加成法，在电极焊盘上制作两个纵20μm、横3μm、高度5μm的金属凸部，最后，蚀刻电极焊盘的晶种层，制作了具有金属凸部的电极焊盘。将其切割成10mm×8mm并用于评价，除此以外与实施例1相同。
[实施例3]
在硅晶片上，在与“WALTS－TEG WM40－0102JY”的凸块位置对置的位置，使用半加成法，用直径26μm、厚度2μm的镀覆铜形成了电极焊盘。此时，不蚀刻晶种层。接着，在所制作的电极焊盘的表面，同样地使用半加成法，在电极焊盘上制作纵10μm、横10μm、高度5μm的金属凸部，最后，蚀刻电极焊盘的晶种层，制作了具有金属凸部的电极焊盘。将其切割成10mm×8mm并用于评价，除此以外与实施例1相同。
[实施例4]
在硅晶片上，在与“WALTS－TEG WM40－0102JY”的凸块位置对置的位置，使用半加成法，用直径26μm、厚度2μm的镀覆铜形成了电极焊盘。此时，不蚀刻晶种层。接着，在所制作的电极焊盘的表面，同样地使用半加成法，在电极焊盘上制作直径16μm、高度5μm的金属凸部，最后，蚀刻电极焊盘的晶种层，制作了具有金属凸部的电极焊盘。将其切割成10mm×8mm并用于评价，除此以外与实施例1相同。
[实施例5]
在硅晶片上，在与“WALTS－TEG WM40－0102JY”的凸块位置对置的位置，使用半加成法，用直径26μm、厚度2μm的镀覆铜形成了电极焊盘。此时，不蚀刻晶种层。接着，在所制作的电极焊盘的表面，同样地使用半加成法，在电极焊盘上制作了直径16μm、高度2μm的金属凸部。在该制作的圆柱状的金属凸部上表面，同样地使用半加成法，制作直径8μm、高度3μm的金属凸部，最后，蚀刻电极焊盘的晶种层，制作了具有金属凸部的电极焊盘。将其切割成10mm×8mm并用于评价，除此以外与实施例1相同。
[比较例1]
除了在实施例1的电极焊盘的表面不制作金属凸部以外，与实施例1相同。
[比较例2]
在硅晶片上，在与“WALTS－TEG WM40－0102JY”的凸块位置对置的位置，使用半加成法，用直径26μm、厚度2μm的镀覆铜形成了电极焊盘。此时，不蚀刻晶种层。接着，在所制作的电极焊盘的表面，同样地使用半加成法，在电极焊盘上制作直径24μm、高度5μm的金属凸部，最后，蚀刻电极焊盘的晶种层，制作了具有金属凸部的电极焊盘。将其切割成10mm×8mm并用于评价，除此以外与实施例1相同。
[比较例3]
在硅晶片上，在与“WALTS－TEG WM40－0102JY”的凸块位置对置的位置，使用半加成法，用直径26μm、厚度2μm的镀覆铜形成了电极焊盘。此时，不蚀刻晶种层。接着，在所制作的电极焊盘的表面，同样地使用半加成法，在电极焊盘上制作直径22μm、高度5μm的金属凸部，最后，蚀刻电极焊盘的晶种层，制作了具有金属凸部的电极焊盘。将其切割成10mm×8mm并用于评价，除此以外与实施例1相同。
对上述获得的半导体元件的安装构造如以下那样进行了安装后的位置偏移的确认。将评价结果示于表1。
＜硅芯片与基板的位置偏移的确认＞
位置偏移的确认通过如下方式进行：对使基板的金属凸部穿入硅芯片的焊料凸块而将硅芯片临时搭载于基板、并通过加热处理进行了焊料连接的半导体元件的安装构造，通过X射线观察装置(Nordson Advanced Technology株式会社，商品名“XD－7600NT100－CT”)来确认硅芯片的焊料凸块与基板的电极焊盘部分的位置偏移。对位置偏移按照以下的评价基准进行了评价。
另外，位置偏移为，测定5个部位，求出了其算术平均值。
－评价基准－
A：硅芯片的凸块与基板的电极焊盘部分的位置偏移的平均为小于10μm。
B：硅芯片的凸块与基板的电极焊盘部分的位置偏移的平均为10μm以上且小于15μm。
C：硅芯片的凸块与基板的电极焊盘部分的位置偏移的平均为15μm以上。
【表1】
Figure BDA0002406956360000201
[实施例6]
作为半导体元件，准备了在与突起电极相反的一面的相同的位置具有电极焊盘、具有能够层叠的铝布线的、尺寸为10mm×8mm、厚度为50μm的硅芯片(株式会社WALTS，商品名“WALTS－TEG WM40－0101JY”，突起电极(凸块)：Sn－Ag系焊料，凸块焊料厚度：8μm，凸块间隔：40μm，铜支柱的高度：15μm，凸块尺寸：
Figure BDA0002406956360000211
电极焊盘：焊盘尺寸：
Figure BDA0002406956360000212
焊盘高度：6μm)。将用与实施例1相同的方法在该“WALTS－TEG WM40－0101JY”的电极焊盘上制作了纵20μm、横3μm、高度5μm的金属凸部的制品用于评价。
接着，以使硅芯片的具有凸块的面朝向基板侧、凸块与基板接触的方式，利用加压用部件从硅芯片之上以100N的负载进行加压，使基板的金属凸部穿入凸块的焊料层。此时，在对硅芯片的凸块赋予助焊剂之后进行了加压。同样地，在相同条件下层叠四层相同的硅芯片，制作了临时搭载有四层硅芯片(半导体元件)的基板，除此以外与实施例1相同。
[实施例7]
在实施例1中，使临时搭载有硅芯片的基板通过IR回流炉，在进行了焊料连接的基板上，使用喷射分配机(武藏高科技株式会社，商品名“FAD2500”)涂覆日立化成株式会社的液状密封材料：CEL－C－3730，在165℃下固化2个小时，除此以外与实施例1相同。
[实施例8]
在硅晶片上，在与“WALTS－TEG WM40－0102JY”的凸块位置对置的位置，使用半加成法，用直径26μm、厚度2μm的镀覆铜形成了电极焊盘。此时，不蚀刻晶种层。接着，在所制作的电极焊盘的表面，同样地使用半加成法，在电极焊盘上制作直径16.4μm、高度5μm的金属凸部，最后，蚀刻电极焊盘的晶种层，制作了具有金属凸部的电极焊盘。将其切割成10mm×8mm并用于评价，除此以外与实施例1相同。
[实施例9]
在硅晶片上，在与“WALTS－TEG WM40－0102JY”的凸块位置对置的位置，使用半加成法，用直径26μm、厚度2μm的镀覆铜形成了电极焊盘。此时，不蚀刻晶种层。接着，在所制作的电极焊盘的表面，同样地使用半加成法，在电极焊盘上制作直径15μm、高度5μm的金属凸部，最后，蚀刻电极焊盘的晶种层，制作了具有金属凸部的电极焊盘。将其切割成10mm×8mm并用于评价，除此以外与实施例1相同。
[实施例10]
在硅晶片上，在与“WALTS－TEG WM40－0102JY”的凸块位置对置的位置，使用半加成法，用直径26μm、厚度2μm的镀覆铜形成了电极焊盘。此时，不蚀刻晶种层。接着，在所制作的电极焊盘的表面，同样地使用半加成法，在电极焊盘上制作直径14μm、高度5μm的金属凸部，最后，蚀刻电极焊盘的晶种层，制作了具有金属凸部的电极焊盘。将其切割成10mm×8mm并用于评价，除此以外与实施例1相同。
[实施例11]
在硅晶片上，在与“WALTS－TEG WM40－0102JY”的凸块位置对置的位置，使用半加成法，用直径26μm、厚度2μm的镀覆铜形成了电极焊盘。此时，不蚀刻晶种层。接着，在所制作的电极焊盘的表面，同样地使用半加成法，在电极焊盘上制作直径17μm、高度5μm的金属凸部，最后，蚀刻电极焊盘的晶种层，制作了具有金属凸部的电极焊盘。将其切割成10mm×8mm并用于评价，除此以外与实施例1相同。
对上述获得的实施例6～实施例11的半导体元件的安装构造如以下那样进行了安装后的位置偏移的确认。同时，对实施例1～实施例5以及比较例1～比较例3的半导体元件的安装构造也同样地进行了评价。将评价结果示于表2以及表3。
＜硅芯片与基板的位置偏移的确认＞
位置偏移的确认通过如下方式进行：对使基板的金属凸部穿入硅芯片的焊料凸块而将硅芯片临时搭载于基板、并通过加热处理进行了焊料连接的半导体元件的安装构造，通过X射线观察装置(Nordson Advanced Technology株式会社，商品名“XD－7600NT100－CT”)来确认硅芯片的焊料凸块与基板的电极焊盘部分的位置偏移。
另外，位置偏移为，测定20个部位，求出了硅芯片的凸块与基板的电极焊盘部分的位置偏移为小于10μm的部位的比例(百分率)。
【表2】
Figure BDA0002406956360000231
【表3】
Figure BDA0002406956360000232
如表1～表3所示，可知本公开的半导体元件的安装构造不易产生位置偏移，且连接精度优异。
通过参照2017年9月15日提出申请的日本专利申请2017－177487号的公开的整体而将其并入本说明书。
另外，如同具体且单独地记载各个文献、专利申请以及技术标准通过参照而并入的情况那样，本说明书所记载的所有文献、专利申请以及技术标准通过参照而引入本说明书。
附图标记说明
1 半导体元件
2 金属柱
3 焊料层
4 电极焊盘
5 金属凸部
6 基板

Claims (14)

1.一种半导体元件的安装构造，由具有元件电极的半导体元件与具有基板电极的基板经由所述元件电极与所述基板电极连接而成，该基板电极设于所述基板的与所述半导体元件对置的一侧的面的与所述元件电极对置的位置，
所述元件电极以及所述基板电极的一方是在前端部具有焊料层的第一突起电极，
所述元件电极以及所述基板电极的另一方是在表面具有一个或两个以上的金属凸部的第一电极焊盘，
所述第一电极焊盘所具有的所述金属凸部穿入所述第一突起电极所具有的所述焊料层，
所述第一电极焊盘所具有的所述金属凸部的底部面积相对于在所述前端部具有焊料层的第一突起电极的所述焊料层的最大截面积为75％以下。
2.如权利要求1所述的半导体元件的安装构造，其中，
在所述半导体元件的和与所述基板对置的一侧相反的一侧，一个或两个以上的其他半导体元件以各半导体元件彼此经由元件电极连接的状态层叠，
在处于连接关系的两个半导体元件中，一个半导体元件所具有的元件电极以及另一个半导体元件所具有的元件电极的一方是在前端部具有焊料层的第二突起电极，
一个半导体元件所具有的元件电极以及另一个半导体元件所具有的元件电极的另一方是在表面具有一个或两个以上的金属凸部的第二电极焊盘，
所述第二电极焊盘所具有的所述金属凸部穿入所述第二突起电极所具有的所述焊料层，
所述第二电极焊盘所具有的所述金属凸部的底部面积相对于在所述前端部具有焊料层的第二突起电极的所述焊料层的最大截面积为75％以下。
3.如权利要求1或2所述的半导体元件的安装构造，其中，
所述金属凸部的形状为圆柱或立方体。
4.如权利要求1～3中任一项所述的半导体元件的安装构造，其中，
所述金属凸部形成为在高度方向上至少重叠有两个圆柱或立方体的形状。
5.如权利要求1～4中任一项所述的半导体元件的安装构造，其中，
所述金属凸部使用光刻法而形成。
6.如权利要求1～5中任一项所述的半导体元件的安装构造，其中，
通过加压，以所述第一电极焊盘所具有的所述金属凸部的至少一部分穿入所述第一突起电极所具有的所述焊料层的状态，将所述半导体元件与所述基板临时固定，通过加热，使所述第一突起电极所具有的所述焊料层熔融而将所述元件电极与所述基板电极连接，从而获得所述半导体元件的安装构造。
7.一种半导体元件与基板的组合，包括：半导体元件，具有元件电极；以及基板，具有基板电极，该基板电极设于所述基板的与所述半导体元件对置一侧的面的与所述元件电极对置的位置，
所述元件电极以及所述基板电极的一方是在前端部具有焊料层的突起电极，
所述元件电极以及所述基板电极的另一方是在表面具有一个或两个以上的金属凸部的电极焊盘，
所述金属凸部的底部面积相对于在所述前端部具有焊料层的突起电极的所述焊料层的最大截面积为75％以下。
8.一种半导体元件的安装构造，由具有元件电极的半导体元件与具有基板电极的基板经由所述元件电极与所述基板电极连接而成，该基板电极设于所述基板的与所述半导体元件对置的一侧的面的与所述元件电极对置的位置，
所述元件电极以及所述基板电极的一方是在前端部具有焊料层的第一突起电极，
所述元件电极以及所述基板电极的另一方是在表面具有一个或两个以上的金属凸部的第一电极焊盘，
所述第一电极焊盘所具有的所述金属凸部穿入所述第一突起电极所具有的所述焊料层，
所述第一电极焊盘所具有的所述金属凸部的底部面积相对于所述第一电极焊盘的面积为70％以下。
9.如权利要求8所述的半导体元件的安装构造，其中，
在所述半导体元件的和与所述基板对置的一侧相反的一侧，一个或两个以上的其他半导体元件以各半导体元件彼此经由元件电极连接的状态层叠，
在处于连接关系的两个半导体元件中，一个半导体元件所具有的元件电极以及另一个半导体元件所具有的元件电极的一方是在前端部具有焊料层的第二突起电极，
一个半导体元件所具有的元件电极以及另一个半导体元件所具有的元件电极的另一方是在表面具有一个或两个以上的金属凸部的第二电极焊盘，
所述第二电极焊盘所具有的所述金属凸部穿入所述第二突起电极所具有的所述焊料层，
所述第二电极焊盘所具有的所述金属凸部的底部面积相对于所述第二电极焊盘的面积为70％以下。
10.如权利要求8或9所述的半导体元件的安装构造，其中，
所述金属凸部的形状为圆柱或立方体。
11.如权利要求8～10中任一项所述的半导体元件的安装构造，其中，
所述金属凸部形成为，在高度方向上至少重叠有两个圆柱或立方体的形状。
12.如权利要求8～11中任一项所述的半导体元件的安装构造，其中，
所述金属凸部使用光刻法而形成。
13.如权利要求8～12中任一项所述的半导体元件的安装构造，其中，
通过加压，以所述第一电极焊盘所具有的所述金属凸部的至少一部分穿入所述第一突起电极所具有的所述焊料层的状态，将所述半导体元件与所述基板临时固定，通过加热，将所述第一突起电极所具有的所述焊料层熔融而将所述元件电极与所述基板电极连接，从而获得半导体元件的安装构造。
14.一种半导体元件与基板的组合，包括：半导体元件，具有元件电极；以及基板，具有基板电极，该基板电极设于所述基板的与所述半导体元件对置的一侧的面的与所述元件电极对置位置，
所述元件电极以及所述基板电极的一方是在前端部具有焊料层的突起电极，
所述元件电极以及所述基板电极的另一方是在表面具有一个或两个以上的金属凸部的电极焊盘，
所述金属凸部的底部面积相对于所述电极焊盘的面积为70％以下。
CN201880058813.2A 2017-09-15 2018-09-14 半导体元件的安装构造以及半导体元件与基板的组合 Pending CN111095508A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2017177487 2017-09-15
JP2017-177487 2017-09-15
PCT/JP2018/034302 WO2019054509A1 (ja) 2017-09-15 2018-09-14 半導体素子の実装構造及び半導体素子と基板との組み合わせ

Publications (1)

Publication Number Publication Date
CN111095508A true CN111095508A (zh) 2020-05-01

Family

ID=65722810

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201880058813.2A Pending CN111095508A (zh) 2017-09-15 2018-09-14 半导体元件的安装构造以及半导体元件与基板的组合

Country Status (7)

Country Link
US (1) US11444054B2 (zh)
JP (1) JPWO2019054509A1 (zh)
KR (1) KR102574011B1 (zh)
CN (1) CN111095508A (zh)
SG (1) SG11202002226QA (zh)
TW (2) TW201933561A (zh)
WO (1) WO2019054509A1 (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7259942B2 (ja) * 2019-03-29 2023-04-18 株式会社村田製作所 樹脂多層基板、および樹脂多層基板の製造方法
CN115312408A (zh) * 2021-05-04 2022-11-08 Iqm 芬兰有限公司 用于竖直互连的电镀
WO2024009498A1 (ja) * 2022-07-08 2024-01-11 株式会社レゾナック 半導体装置の製造方法、基板及び半導体素子
CN116884862B (zh) * 2023-09-07 2023-11-24 江苏长晶科技股份有限公司 一种基于3d打印的凸点制作方法及芯片封装结构

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10270498A (ja) * 1997-03-27 1998-10-09 Toshiba Corp 電子装置の製造方法
JP2003031613A (ja) * 2001-07-12 2003-01-31 Matsushita Electric Works Ltd フリップチップ実装体及びフリップチップ実装方法
CN101295692A (zh) * 2007-04-06 2008-10-29 株式会社日立制作所 半导体装置
US20100314745A1 (en) * 2009-06-11 2010-12-16 Kenji Masumoto Copper pillar bonding for fine pitch flip chip devices
JP2015228524A (ja) * 2015-09-02 2015-12-17 日立化成株式会社 液状感光性接着剤

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3078781B2 (ja) * 1998-06-16 2000-08-21 松下電器産業株式会社 半導体装置の製造方法及び半導体装置
JP2001223227A (ja) 2000-02-08 2001-08-17 Nitto Denko Corp 半導体封止用樹脂組成物および半導体装置
JP2002283098A (ja) 2001-03-28 2002-10-02 Sumitomo Bakelite Co Ltd 半田ペースト組成物、並びにそれを用いた半田接合部、半導体パッケージ及び半導体装置
JP2003045911A (ja) 2001-07-31 2003-02-14 Kyocera Corp 半導体素子の実装構造および実装用配線基板
JP2005272547A (ja) 2004-03-24 2005-10-06 Sumitomo Bakelite Co Ltd 一液型エポキシ樹脂組成物
JP2006169407A (ja) 2004-12-16 2006-06-29 Nitto Denko Corp 半導体封止用樹脂組成物
JP2006188573A (ja) 2005-01-04 2006-07-20 Hitachi Chem Co Ltd 液状エポキシ樹脂組成物、該組成物を用いた電子部品装置及びその製造方法
JP2007043010A (ja) * 2005-08-05 2007-02-15 Matsushita Electric Ind Co Ltd 電子部品の実装方法
JP5217260B2 (ja) 2007-04-27 2013-06-19 住友ベークライト株式会社 半導体ウエハーの接合方法および半導体装置の製造方法
US9230933B2 (en) * 2011-09-16 2016-01-05 STATS ChipPAC, Ltd Semiconductor device and method of forming conductive protrusion over conductive pillars or bond pads as fixed offset vertical interconnect structure
US8970034B2 (en) * 2012-05-09 2015-03-03 Micron Technology, Inc. Semiconductor assemblies and structures

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10270498A (ja) * 1997-03-27 1998-10-09 Toshiba Corp 電子装置の製造方法
JP2003031613A (ja) * 2001-07-12 2003-01-31 Matsushita Electric Works Ltd フリップチップ実装体及びフリップチップ実装方法
CN101295692A (zh) * 2007-04-06 2008-10-29 株式会社日立制作所 半导体装置
US20100314745A1 (en) * 2009-06-11 2010-12-16 Kenji Masumoto Copper pillar bonding for fine pitch flip chip devices
JP2015228524A (ja) * 2015-09-02 2015-12-17 日立化成株式会社 液状感光性接着剤

Also Published As

Publication number Publication date
JPWO2019054509A1 (ja) 2020-10-15
US20200273837A1 (en) 2020-08-27
WO2019054509A1 (ja) 2019-03-21
SG11202002226QA (en) 2020-04-29
US11444054B2 (en) 2022-09-13
KR20200054961A (ko) 2020-05-20
KR102574011B1 (ko) 2023-09-04
TW202326974A (zh) 2023-07-01
TW201933561A (zh) 2019-08-16

Similar Documents

Publication Publication Date Title
US7390700B2 (en) Packaged system of semiconductor chips having a semiconductor interposer
US8076232B2 (en) Semiconductor device and method of forming composite bump-on-lead interconnection
TWI567864B (zh) 在基板上形成高繞線密度互連位置的半導體裝置及方法
US7026188B2 (en) Electronic device and method for manufacturing the same
US20130241083A1 (en) Joint Structure for Substrates and Methods of Forming
US20150214207A1 (en) Chip stack, semiconductor devices having the same, and manufacturing methods for chip stack
JP6189181B2 (ja) 半導体装置の製造方法
JP5465942B2 (ja) 半導体装置およびその製造方法
KR102121176B1 (ko) 반도체 패키지의 제조 방법
CN111095508A (zh) 半导体元件的安装构造以及半导体元件与基板的组合
TW201232681A (en) Semiconductor device and method of forming bump-on-lead interconnection
US20120077312A1 (en) Flip-chip bonding method to reduce voids in underfill material
JP2012204631A (ja) 半導体装置、半導体装置の製造方法及び電子装置
JP6958156B2 (ja) 半導体装置の製造方法
TWI778938B (zh) 半導體裝置和製造其之方法
TW201448071A (zh) 晶片堆疊、具有晶片堆疊之半導體裝置及晶片堆疊之製造方法
USRE44500E1 (en) Semiconductor device and method of forming composite bump-on-lead interconnection
JP5812123B2 (ja) 電子機器の製造方法
KR101053746B1 (ko) 반도체 시스템 및 그 제조 방법
TW201836103A (zh) 半導體晶片之製造方法
TWI738725B (zh) 半導體封裝及其製造方法

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
CB02 Change of applicant information
CB02 Change of applicant information

Address after: Tokyo

Applicant after: Lishennoco Co.,Ltd.

Address before: Tokyo

Applicant before: HITACHI CHEMICAL Co.,Ltd.