CN111090969A - EDA tool-based flat panel display layout generation method - Google Patents
EDA tool-based flat panel display layout generation method Download PDFInfo
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- CN111090969A CN111090969A CN201911316878.5A CN201911316878A CN111090969A CN 111090969 A CN111090969 A CN 111090969A CN 201911316878 A CN201911316878 A CN 201911316878A CN 111090969 A CN111090969 A CN 111090969A
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Abstract
A flat panel display layout generation method based on an EDA tool comprises the following steps: constructing a parameter file and importing the parameter file into an EDA tool; limiting the positions of the parts of the FPD; associating and modifying various parameters in the parameter file; drawing an FPD Layout, and outputting an FPD Layout drawing and a Log file. According to the method for generating the flat-panel display layout based on the EDA tool, a designer does not need to manually draw or modify on the EDA tool, drawing efficiency is improved, the correctness and the reliability of drawing are guaranteed, drawing errors of artificial layout are avoided, and labor and production cost is greatly reduced.
Description
Technical Field
The invention relates to the technical field of integrated circuit design, in particular to a layout generation method of a flat-panel display.
Background
The FPD layout design is an indispensable functional work of the current panel factory and is also a very important link in the production engineering of flat panel display products. The traditional FPD layout design process is finished by hand drawing of each part of EDA drawing software by designers, the designers are required to master rich technical experience, and the requirements on operation and use of an EDA tool are very high.
However, the traditional design process has low efficiency, high error rate and high cost for skill learning and layout trial and error modification, and is always the problem to be solved urgently faced by all panel factories.
Disclosure of Invention
In order to solve the defects in the prior art, the invention aims to provide a method for generating a flat panel display layout based on an EDA Tool, which comprises the steps of parameterizing various design indexes of an FPD to form a file form capable of being identified by the EDA Tool, importing the parameter file through the EDA Tool, calling corresponding functions of the EDA Tool by various Source parameters in the EDA Tool, automatically copying the parameters in the file to the Option parameter setting of the EDA Tool, and completing the layout drawing action.
In order to achieve the above object, the present invention provides a method for generating a flat panel display layout based on EDA tools, comprising the following steps:
constructing a parameter file and importing the parameter file into an EDA tool;
limiting the positions of the parts of the FPD;
associating and modifying various parameters in the parameter file;
drawing an FPD Layout, and outputting an FPD Layout drawing and a Log file.
Further, the parameter file is shown to include, TOP type, Pixel type, GOA type, RGB type, ESD type, and Fanout type.
Further, the step of importing the parameter file into the EDA tool, comprises,
identifying a parameter file format;
comparing the contents of the parameter files, and checking whether the format and the contents of the files are consistent with the interface data;
each item of content of the identified file is scanned line by line.
Further, the step of defining the positions of the portions of the FPD further comprises,
and grabbing the names of the parts on the drawing, identifying the positions, and limiting the matched parts at the positions of the Panel layout when laying out and wiring.
Furthermore, the step of associating and modifying each parameter in the parameter file further comprises associating the parameters in the parameter file by using an EXCEL table calculation function, so as to avoid the phenomenon that the parameter file is not compliant or contradictory.
In order to achieve the above object, the present invention further provides an EDA tool-based flat panel display layout generating apparatus, including a memory and a processor, where the memory stores a program running on the processor, and the processor runs the program to implement the steps of the EDA tool-based flat panel display layout generating method.
To achieve the above object, the present invention provides a computer readable storage medium having stored thereon a computer program, which when executed by a processor, implements the steps of the EDA tool-based flat panel display layout generation method described above.
The method for generating the flat panel display layout based on the EDA tool can simplify the FPD design flow, does not need designers to manually draw or modify on the EDA tool, and improves the drawing efficiency. In addition, by automatically generating the layout, the correctness and the reliability of the drawing can be improved, the drawing error of the artificial layout is avoided, and the labor and the production cost are greatly reduced. For designers, the learning cost is low, only the parameters of the adjusting file are filled in and input into an EDA tool, the EDA operation is not required to be high, and the problem of shortage of designers is solved.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a flow chart of a method for generating a flat panel display layout based on EDA tools according to the present invention;
FIG. 2 is a schematic diagram of a parameter file according to the present invention;
FIG. 3 is a schematic diagram of a Panel layout according to the present invention;
FIG. 4 is a schematic diagram of an EDA tool import setup according to the present invention;
FIG. 5 is a schematic diagram of an EDA tool automatically generating layout according to the present invention;
FIG. 6 is a schematic illustration of a run Log results display according to the present invention;
FIG. 7 is a schematic diagram of the EDA tool based layout generation apparatus according to the present invention.
Detailed Description
The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are described herein for the purpose of illustration and explanation and not limitation.
Fig. 1 is a flowchart of a method for generating a flat panel display layout based on an EDA tool according to the present invention, and the method for generating a flat panel display layout based on an EDA tool according to the present invention will be described in detail with reference to fig. 1.
First, at step 101, a parameter file containing versions of CSV, World, etc. is set and imported into an EDA tool, the file type being importable into a specific EDA tool. The parameter file contains index parameters of FPD design. Fig. 2 is a schematic diagram of a parameter file according to the present invention, as shown in fig. 1, in the first step, each part of the Panel is classified into 6 types, which are TOP (TOP layer layout), Pixle (pixel), GOA (driver circuit), RGB (light emitting display type), ESD (electrostatic protection unit), Fanout (physical wiring); each class is provided with each part limiting parameter respectively. Each parameter has a corresponding EDA Tool, after the parameter file is imported into the EDA Tool, the EDA software scans each fixed classification, and each parameter is scanned to open the corresponding function of the EDA Tool according to the information of the EDA Tool column, import Value into the Option and execute drawing operation.
In the embodiment of the invention, the limitation parameters of each part are set by writing aiming at the parameter table, the parameter table is in a file form of Excel/World and the like, the parameter table can be directly edited and set, the specific contents of the limitation parameters are shown in figure 1, and all ITEM columns are the limitation parameters of the parameter table.
Fig. 4 is a schematic diagram of an EDA tool import setting according to the present invention, and as shown in fig. 4, the step of importing the parameter file into the EDA tool includes: open EDA tool, select Import function, CSV File select parameter File, then point Aply or OK.
In the embodiment of the invention, when the EDA tool executes the operation command, the Value column of the identification (Source) parameter table is scanned at the same time, and the Value is read and Copy is carried out in the Option.
In step 102, the locations of the various portions of the FPD are defined.
In the embodiment of the invention, the positions of all parts of the FPD are limited, after the EDA imports the drawing, the names of all parts on the drawing are grabbed, the positions are identified, and the matched parts are limited at the positions of the Panel layout when the wiring is laid out.
Fig. 3 is a schematic diagram of a Panel layout according to the present invention, where Panel _ layout.dxf is input in the parameter Panel layout to define the positions of the parts, and thus, the situation of graphics confusion and overlap will not occur.
In step 103, parameters in the parameter file are associated and modified.
In the embodiment of the invention, all parameters in the parameter file can be modified but are not mutually independent, and after partial key parameters are input, other related parameters can be automatically generated by a calculation formula, so that the phenomenon that the parameter file is not in compliance or contradictory is avoided.
And calculating a function for the EXCEL table, for example, if the AA area W x L is given, calculating the diagonal length of the AA area through the Pythagorean theorem, and converting the diagonal length into Inch (L/25.4), namely the size of Panel.
And step 104, drawing the FPD Layout, and outputting a Layout drawing and a Log file of the FPD Layout.
In this step, the final output result shows the completed Layout drawing and a Log file, which records the process and the result of each part for automatically drawing the Layout (each time the EDA tool performs an operation from importing a parameter file, the name of the operation, whether the process result has an error, the coordinates of an error position, and the parameters of the error are output in the Log file, and after the final automatic Layout is completed, the Log file pops up), and if there is an error type, the Log file can prompt the error type. And the designer returns to modify the parameter file according to the Erro information, and finally obtains the FPD layout meeting the requirements.
Example 1
FIG. 2 is a schematic diagram of a parameter file according to the present invention, as shown in FIG. 1, the parameter file imported to the EDA tool, which may be but is not limited to CSV/Word format, can be recognized by the EDA tool, and imports various parameters of the file and information of DXF drawing, Check rule, etc. The parameter file is divided into 6 parts, namely TOP (TOP layer layout), Pixle (pixel), GOA (drive circuit), RGB (light emitting Display type), ESD (electrostatic protection unit) and Fanout (physical wiring), each part represents each component of the Flat panel Display, and the parameter file is provided with a plurality of limiting parameters, and each limiting parameter represents one or more operation commands to be executed in an EDA tool. And when the EDA tool performs Source ITEM content ITEM by ITEM, executing a corresponding function and importing Value into a function Option to automatically draw the layout. After each ITEM of ITEM Source is finished, the six parts are placed at corresponding positions according to the DXF drawing of the Panel layout, the connection is finished, and the automatic generation operation of the layout of each part follows the Rule file set by each part.
Fig. 3 is a schematic diagram of the Panel layout according to the present invention, as shown in fig. 3, in the TOP category of the parameter file, together with the Out Line as the definition of the Panel Size and the respective part Size and specific location. The sections of Layout drawings of the EDA tool, which are formed when the first operation is performed, are laid out at corresponding positions according to the Layout drawing of Panel and automatically aligned and adjusted, where alignment or adjustment rules can be set according to the process conditions. After the classification and placement of each part are finished, the GOA and Fanout connection operation is carried out, the GOA connection can be aligned line by line from top to bottom or from bottom to top, or the operation can be repeated after the number of Dummy GOAs is set. The Fanout connection line can be connected from left to right or from right to left, and the Dummy number and the resistance rule can be set. The situations that the space is insufficient and the number of the ports is not matched in the layout process of all the operations are recorded in the Log file, so that layout inspection and parameter modification are facilitated.
Fig. 4 is a schematic diagram of the EDA tool import setting according to the present invention, as shown in fig. 4, the EDA tool import setting is achieved by an algorithm that the EDA tool can recognize the parameter file and Source each parameter command line by line after importing the parameter file. If the EDA tool has Source TOP parameters, calling the DXF drawing of the Panel layout and the Out Line item to form the peripheral graph of the FPD; and then, Source Pixel classification, Pixel Model Layout (PDK is set in advance), and Pixel Size and TFT w/l values are modified according to Pixel Size and Pixel Circuit. After the modification is finished, performing Array operation on the pixels by Source Resolution to form an AA area; the following GOA, RGB, ESD, Fanout parts work in the same logic.
In this embodiment, an interface is added to the EDA tool, and the interface is used for identifying the format of the parameter file. When the Import command of the EDA is started, the tool searches whether the CSV file format exists under the directory through the structure, and if so, the CSV file format is displayed and can be clicked. And then, comparing the contents of the files, judging whether the format and the contents of the Check file are consistent with the interface data, and if so, determining each content of the Source file line by line. Wherein the Item columns are all corresponding commands to start different functions of the EDA.
Fig. 5 is a schematic diagram of an EDA tool automatically generating layout according to the present invention, and as shown in fig. 5, after each partial layout is automatically generated and combined, a Preview layout can schematically see whether the expected effect is met, and a part with an operation error or an incomplete parameter will be highlighted, so as to facilitate rapid positioning and inspection.
Fig. 6 is a schematic diagram showing a Log result of the present invention, and the Log result shows that the Log file can completely record the automatic layout generation operation process, read the Final information viewing and positioning error, and modify and adjust the parameter file to achieve an ideal effect.
Fig. 7 is a schematic structural diagram of an EDA tool-based flat-panel display layout generating apparatus 70 according to the present invention, as shown in fig. 7, the EDA tool-based flat-panel display layout generating apparatus 70 of the present invention includes a processor 701 and a memory 702, where the memory 702 stores a program, and when the program is read and executed by the processor 701, the program performs the following operations:
constructing a parameter file and importing the parameter file into an EDA tool;
limiting the positions of the parts of the FPD;
associating and modifying various parameters in the parameter file;
drawing an FPD Layout, and outputting an FPD Layout drawing and a Log file.
The computer-readable storage medium provided by the present invention can be located on one or more computing devices, and the computing device comprises a processor, and the processor executes a computer program in the computer-readable storage medium on the computing device, so as to implement the steps of the EDA tool-based flat panel display layout generation method of the present invention described above.
Those of ordinary skill in the art will understand that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (7)
1. A flat panel display layout generation method based on an EDA tool comprises the following steps:
constructing a parameter file and importing the parameter file into an EDA tool;
limiting the positions of the parts of the FPD;
associating and modifying various parameters in the parameter file;
drawing an FPD Layout, and outputting an FPD Layout drawing and a Log file.
2. The EDA tool based flat panel display layout generation method of claim 1, wherein said parameter files comprise TOP type, Pixel type, GOA type, RGB type, ESD type, and Fanout type.
3. The EDA tool-based flat panel display layout generation method according to claim 1, wherein the step of importing the parameter file into the EDA tool, comprises,
identifying a parameter file format;
comparing the contents of the parameter files, and checking whether the format and the contents of the files are consistent with the interface data;
each item of content of the identified file is scanned line by line.
4. The EDA tool based flat panel display layout generation method of claim 1, wherein said step of defining locations of portions of the FPD further comprises,
and grabbing the names of the parts on the drawing, identifying the positions, and limiting the matched parts at the positions of the Panel layout when laying out and wiring.
5. The EDA tool-based flat panel display layout generation method of claim 1, wherein the step of associating and modifying the parameters in the parameter file further comprises using an EXCEL table computation function to associate the parameters in the parameter file, so as to avoid the occurrence of the phenomena of non-compliance or mutual contradiction of the parameter file.
6. An EDA tool-based flat panel display layout generation apparatus, comprising a memory and a processor, wherein the memory stores a program running on the processor, and the processor executes the program to perform the steps of the EDA tool-based flat panel display layout generation method according to any one of claims 1 to 5.
7. A computer readable storage medium, having stored thereon a computer program, characterized in that the program, when being executed by a processor, realizes the steps of the EDA tool based flat panel display layout generation method of any of the claims 1 to 5.
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Cited By (3)
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| CN111681580A (en) * | 2020-07-01 | 2020-09-18 | 深圳市华星光电半导体显示技术有限公司 | Display panel design method and device and electronic equipment |
| CN112149377A (en) * | 2020-11-04 | 2020-12-29 | 深圳华大九天科技有限公司 | Method and device for rapidly generating FPD layout and readable storage medium |
| CN117077616A (en) * | 2023-10-17 | 2023-11-17 | 苏州异格技术有限公司 | Circuit generation method, device, equipment and medium based on structure guidance |
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| CN117077616B (en) * | 2023-10-17 | 2024-01-26 | 苏州异格技术有限公司 | Circuit generation method, device, equipment and medium based on structure guidance |
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Application publication date: 20200501 |