CN111081753A - Thin film transistor and preparation method thereof - Google Patents
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- CN111081753A CN111081753A CN201911219953.6A CN201911219953A CN111081753A CN 111081753 A CN111081753 A CN 111081753A CN 201911219953 A CN201911219953 A CN 201911219953A CN 111081753 A CN111081753 A CN 111081753A
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- 239000010409 thin film Substances 0.000 title claims abstract description 61
- 238000002360 preparation method Methods 0.000 title claims description 7
- 239000004065 semiconductor Substances 0.000 claims abstract description 150
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000000034 method Methods 0.000 claims description 24
- 239000000463 material Substances 0.000 claims description 18
- 238000000151 deposition Methods 0.000 claims description 11
- 239000007789 gas Substances 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 10
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- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 5
- 239000001272 nitrous oxide Substances 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 229910052734 helium Inorganic materials 0.000 claims description 3
- 239000001307 helium Substances 0.000 claims description 3
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
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- HLLICFJUWSZHRJ-UHFFFAOYSA-N tioxidazole Chemical compound CCCOC1=CC=C2N=C(NC(=O)OC)SC2=C1 HLLICFJUWSZHRJ-UHFFFAOYSA-N 0.000 claims 1
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- HRHKULZDDYWVBE-UHFFFAOYSA-N indium;oxozinc;tin Chemical compound [In].[Sn].[Zn]=O HRHKULZDDYWVBE-UHFFFAOYSA-N 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- NQBRDZOHGALQCB-UHFFFAOYSA-N oxoindium Chemical compound [O].[In] NQBRDZOHGALQCB-UHFFFAOYSA-N 0.000 description 1
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- 238000001259 photo etching Methods 0.000 description 1
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- 239000004033 plastic Substances 0.000 description 1
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- 230000002035 prolonged effect Effects 0.000 description 1
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 1
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
- H01L29/78693—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate the semiconducting oxide being amorphous
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
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- H01L29/1025—Channel region of field-effect devices
- H01L29/1029—Channel region of field-effect devices of field-effect transistors
- H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
- H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
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- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
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- Thin Film Transistor (AREA)
Abstract
The thin film transistor comprises a substrate, a gate layer, an insulating layer, a semiconductor layer, a source electrode and a drain electrode, wherein the semiconductor layer comprises a first semiconductor layer and a second semiconductor layer, the first semiconductor layer is an amorphous oxide semiconductor, the second semiconductor layer is a polycrystalline oxide semiconductor, the carrier concentration in the second semiconductor layer is larger than that in the first semiconductor layer, the second semiconductor layer contains a large number of crystal boundaries and defects, and the second semiconductor layer effectively captures free electrons generated in working, reduces leakage current and improves stability of devices.
Description
Technical Field
The disclosure relates to the field of display technologies, and in particular, to a thin film transistor and a method for manufacturing the thin film transistor.
Background
In recent years, the application field of display panels has become wider and wider. In display devices, thin film transistor devices play an important role in display panels such as liquid crystal display panels and organic light emitting diodes.
To realize a large-sized, high-resolution display panel, a thin film transistor having a smaller size needs to be fabricated to match it. Among them, the back channel etching type structure is a method that can realize the miniaturization of the device, however, in the existing miniaturized thin film transistor device, the preparation material usually adopts the traditional a-Si or organic semiconductor material, and the mobility in the formed thin film transistor is low. The electrical conductance in the internal semiconductor layers of the device is low during normal operation. Meanwhile, the device may still have a high leakage current in the off state, or easily generate carriers sensitive to light, which finally causes the device to be damaged, and reduces the service life of the display panel.
In summary, the mobility of carriers in the thin film transistor in the conventional display panel is low, and the device still has a high leakage current in the off state, which results in poor stability of the device and unsatisfactory lifetime of the display panel.
Disclosure of Invention
The present disclosure provides a thin film transistor and a method for manufacturing the thin film transistor, so as to solve the problems of low electron mobility, poor stability and short panel service life of the thin film transistor in the existing display panel.
To solve the above technical problem, the technical solution provided by the embodiment of the present disclosure is as follows:
according to a first aspect of embodiments of the present disclosure, there is provided a thin film transistor including:
a substrate;
a gate layer disposed on the substrate;
an insulating layer disposed on the substrate and covering the gate layer;
a semiconductor layer disposed on the insulating layer; and
the source electrode and the drain electrode are arranged on two opposite sides of the semiconductor layer and are electrically connected with the semiconductor layer;
the semiconductor layer comprises a first semiconductor layer and a second semiconductor layer, the second semiconductor layer is arranged on the first semiconductor layer, and the carrier concentration in the second semiconductor layer is greater than that in the first semiconductor layer.
According to an embodiment of the present disclosure, the material of the first semiconductor layer is an amorphous oxide, and the material of the second semiconductor layer is a polycrystalline oxide.
According to an embodiment of the present disclosure, a thickness of the second semiconductor layer is smaller than a thickness of the first semiconductor layer.
According to an embodiment of the present disclosure, the second semiconductor layer has a thickness of
According to an embodiment of the present disclosure, a material of the semiconductor layer includes at least one of IGZO, IZO, AZO, ATO, GZO, ITO, TiOx, and ZnO.
According to an embodiment of the present disclosure, the thickness of the semiconductor layer is
According to a second aspect of the embodiments of the present disclosure, there is also provided a method for manufacturing a thin film transistor, including the steps of:
s100: depositing a gate layer on a substrate;
s101: preparing an insulating layer on the surface of the gate layer;
s102: depositing a semiconductor layer on the insulating layer;
s103: preparing a source electrode and a drain electrode on the semiconductor layer, and carrying out graphical etching;
s104: processing the semiconductor layer to enable the semiconductor layer to form a second semiconductor layer;
s105: and depositing a passivation layer to form the thin film transistor.
According to an embodiment of the present disclosure, in the step S104, the semiconductor layer is processed by a radio frequency plasma process.
According to an embodiment of the present disclosure, the plasma includes a mixed gas of oxygen and helium or nitrous oxide gas.
According to an embodiment of the present disclosure, the rf frequency in the rf plasma process is 1 MHz-200 MHz, and the power is 500W-2000W.
In summary, the beneficial effects of the embodiment of the present disclosure are:
the invention provides a thin film transistor and a preparation method of the thin film transistor, wherein a semiconductor layer in a channel region of the thin film transistor is processed, in the embodiment of the thin film transistor, the surface of the semiconductor layer is processed mainly through a radio frequency plasma process, atoms in the semiconductor layer are rearranged, nucleated and grown up through energy generated in the radio frequency process, and after the processing is completed, the semiconductor layer forms a second semiconductor layer, wherein grain boundaries and defects of materials in the formed second semiconductor layer are increased, the grain size is increased, and meanwhile, the concentration of carriers in the second semiconductor layer is improved. The formed crystal boundary and crystal defects can effectively capture carriers, and reduce the leakage current of a back channel region of the device, so that the high mobility is realized, the lower leakage current of the device is ensured, the stability of the device is improved, and the service life of the device is prolonged.
Drawings
In order to illustrate the embodiments or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some of the disclosed embodiments, and that other drawings can be obtained by those skilled in the art without inventive effort.
FIG. 1 is a schematic structural diagram of a thin film transistor according to an embodiment of the present disclosure;
FIG. 2 is a schematic diagram of a two-dimensional model structure of a semiconductor die according to an embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of another thin film transistor according to an embodiment of the disclosure;
FIG. 4 is a flow chart illustrating a process for fabricating a thin film transistor according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. It is to be understood that the described embodiments are merely illustrative of some, but not all embodiments of the disclosure. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any inventive step, are intended to be within the scope of the present disclosure.
As shown in fig. 1, fig. 1 is a schematic structural diagram of a thin film transistor in an embodiment of the disclosure. In an embodiment of the present disclosure, the thin film transistor includes a substrate base plate 100, an insulating layer 101, and a gate electrode 104. A gate electrode 104 is disposed on the base substrate 100, an insulating layer 101 is disposed on the base substrate 100, and the insulating layer 101 covers the gate electrode 104. The insulating layer 101 may be a gate insulating layer. In the embodiments of the present disclosure, a bottom gate thin film transistor is taken as an example for description.
The substrate base 100 may be a glass base or a flexible base, and may be formed of various materials including a metal material, a plastic material such as polyethylene terephthalate, polyethylene naphthalate, polyimide, or the like. Meanwhile, the substrate 100 may further include a single-layer or multi-layer structure material of silicon oxide or silicon nitride, which may effectively serve as a buffer.
The thin film transistor further includes a semiconductor layer 108. The semiconductor layer 108 is disposed on the insulating layer 101, and in the embodiment of the present disclosure, the semiconductor layer 108 includes a first semiconductor layer 106 and a second semiconductor layer 107, the first semiconductor layer 106 is disposed on the insulating layer 101, and the second semiconductor layer 107 is disposed on the first semiconductor layer 101. In the embodiment of the present disclosure, the semiconductor layer 108 further includes a channel region 105 thereon. The source electrode 103 and the drain electrode 102 of the thin film transistor are disposed on opposite sides of the semiconductor layer 108, and a channel region 105 is formed at a position opposite to the semiconductor layer 108. In the subsequent process of manufacturing the thin film transistor, the semiconductor layer 108 corresponding to the channel region 105 is processed, so as to obtain the thin film transistor in the embodiment of the present disclosure.
The semiconductor layer 108 has a large influence on the performance and stability of the thin film transistor device. For the thin film transistor, when the thin film transistor normally operates, a positive voltage is applied to the gate 104, the gate voltage generates an electric field in the insulating layer 101, the electric field lines of the electric field are directed from the gate 104 to the surface of the semiconductor layer 101, and the depletion layer is converted into an electron accumulation layer on the surface of the semiconductor layer 101, and an inversion layer is formed on the surface. When the electron accumulation reaches a strong inversion, i.e., a turn-on voltage, a voltage is applied between the source 103 and the drain 102 to allow carriers to pass through the channel region 105. When the voltage of the channel region 105 is small, the conductive channel region 105 is approximately a constant resistance, and the drain current increases linearly with the increase of the source-drain voltage; when the source-drain voltage is large, it affects the gate voltage and causes electrons in the inversion layer of the surface of the semiconductor layer 101 to gradually decrease from the source terminal to the drain terminal. Therefore, the size of carriers within semiconductor layer 101 in channel region 105 will directly affect the current voltage of the device.
In the embodiment of the present disclosure, the semiconductor layer 101 is processed by an rf plasma process, and the first semiconductor layer 106 and the second semiconductor layer 107 are formed after the processing is completed. During the rf plasma treatment, the upper half of the semiconductor layer 101 is subjected to high energy, so that the atoms in the semiconductor layer 101 are arranged, agglomerated and grown up, and finally crystallized, thereby forming the second semiconductor layer 107 in the embodiment of the present disclosure. The finally formed first semiconductor layer 106 may be an amorphous oxide semiconductor layer, and the second semiconductor layer 107 may be a polycrystalline oxide semiconductor layer. Since the energy taken up in the second semiconductor layer 107 is greater than the energy taken up in the first semiconductor layer 106, during the treatment, re-nucleation of atoms mainly occurs in the second semiconductor layer 107, neglecting the first semiconductor layer 106. The second semiconductor layer 107 formed under the high temperature has a larger number of grain boundaries than those in the first semiconductor layer 106, and forms grains having a larger size than those in the first semiconductor layer 106 due to the re-nucleation.
Specifically, after the rf plasma process is completed, the first semiconductor layer 106 is mainly an amorphous oxide semiconductor layer, and the second semiconductor layer 107 is mainly a polycrystalline oxide semiconductor layer. Referring to fig. 2, fig. 2 is a schematic diagram of a two-dimensional model structure of a semiconductor layer grain according to an embodiment of the present disclosure. After the recrystallization is completed, the first crystal grains 200 in the first semiconductor layer 106 are hardly changed, the arrangement of the first crystal grains 200 is disordered or ordered in a short range, and the second crystal grains 201 in the second semiconductor layer 107 are ordered in a certain lattice structure due to the re-nucleation and ordered in a long range. Meanwhile, after the recrystallization is completed, the size of crystal grains in the second semiconductor layer 107 is significantly increased. When a voltage is applied to the channel region, free carriers generated in the semiconductor layer 108 are blocked by a plurality of grain boundaries and trapped. Thereby reducing the density of carriers entering the source and drain electrodes and effectively reducing the leakage current. The purpose of improving the stability of the thin film transistor device is achieved.
Since the energy is limited during the rf plasma process, the thickness of the second semiconductor layer 107 can be smaller than the thickness of the first semiconductor layer 106 in the embodiment of the present disclosure. The thickness of the semiconductor layer 108 may be
Preferably, the thickness of the second semiconductor layer 107 can be selected to be
Within. Meanwhile, at the time of processing, the affected region is mainly in the channel region, and thus, the surface area of the second semiconductor layer 107 may be smaller than that of the first semiconductor layer 106.
When the second semiconductor layer 107 is formed, the upper surface of the second semiconductor layer 107 may be a plane, a curved surface, or other shapes. In the case of ensuring that the operation performance of the second semiconductor layer 107 is not affected, the height between each region of the upper surface and each region of the bottom surface may be the same or different, and specifically, the thickness of the second semiconductor layer 107 may be set to be equal to or different from each other
Further, the material of the semiconductor layer 108 may include an oxide semiconductor. Such as a metal oxide semiconductor, which may be formed of an oxide formed of a metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti) or a metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), and titanium (Ti), and an oxide combination thereof. For example, the oxide semiconductor material may include zinc oxide (ZnO), Zinc Tin Oxide (ZTO), indium zinc oxide (ZIO), indium oxide (InO), titanium oxide (TiOx), Indium Gallium Zinc Oxide (IGZO), Indium Zinc Tin Oxide (IZTO), and Indium Tin Oxide (ITO), and at least one of ATO, AZO, or a combination thereof. The oxide has a higher carrier concentration, wherein the second semiconductor layer 107 is a polycrystalline oxide, and the material of the second semiconductor layer 107 may include one or more of the above-mentioned oxide semiconductor materials.
Specifically, as shown in fig. 3, fig. 3 is a schematic structural diagram of another thin film transistor provided in the embodiment of the present disclosure. The thin film transistor further includes a passivation layer 300 and a pixel electrode 301. A passivation layer 300 is disposed on the source and drain electrodes of the thin film transistor and covers the semiconductor layer, and a pixel electrode 301 is disposed on the passivation layer 300. Meanwhile, a via hole 302 is formed at a position corresponding to the thin film transistor drain 102, and the pixel electrode 301 is connected to the thin film transistor drain 102 through the via hole 302.
In a second aspect of the present disclosure, a method for manufacturing a thin film transistor is further provided, as shown in fig. 4, and fig. 4 is a schematic flow chart of a manufacturing process of the thin film transistor in the present disclosure. The preparation process comprises the following steps:
s100: depositing a gate layer on a substrate;
s101: preparing an insulating layer on the surface of the gate layer;
s102: depositing a semiconductor layer on the insulating layer;
s103: preparing a source electrode and a drain electrode of the thin film transistor on the semiconductor layer, and carrying out graphical etching;
s104: processing the semiconductor layer to enable the semiconductor layer to form a second semiconductor layer;
s105: and depositing a passivation layer to form the thin film transistor.
In steps S100 to S103, the thin film transistor can be manufactured according to a normal manufacturing process flow of the thin film transistor. When each film layer of the thin film transistor is prepared, the thin film transistor can be prepared through photoetching processes such as exposure, development, etching and the like, and the specific preparation process is not described here.
And after the semiconductor layer is prepared, processing the semiconductor layer. In an embodiment of the present disclosure, a semiconductor layer is processed by a radio frequency plasma process. Preferably, the frequency of the radio frequency is 1 MHz-200 MHz and the power is 500W-2000W. Adjusting the frequency of the radio frequency may be performed according to the thickness of the semiconductor layer to ensure formation of the second semiconductor layer.
Meanwhile, in the radio frequency treatment process, mixed gas of oxygen and helium is introduced, the gas generates electricity under the action of radio frequency and acts on the semiconductor layer, and materials in the semiconductor layer are recrystallized and nucleated. Finally, the second semiconductor layer is formed in which crystal grains of the material are fine and defects between grain boundaries and the crystal grains increase, and the carrier concentration in the second semiconductor layer increases. When voltage is applied to the source electrode and the drain electrode of the thin film transistor, the grain boundary in the second semiconductor layer and the defects between grains capture current carriers in the back channel and prevent the current carriers from entering other film layers, so that the leakage current and photon-generated current carriers of the back channel are reduced, the low leakage current influence of a thin film transistor device is guaranteed while high mobility is achieved, and the stability of the device is improved.
Before the RF plasma treatment, the semiconductor layer may be cleaned to remove impurities on the surface thereof which may affect the ionization. When the second semiconductor layer is formed, the radio frequency treatment time can be regulated and controlled according to the actual product, and the thickness of the second semiconductor layer can be regulated and controlled. The gas introduced in the radio frequency process is not limited to the gas, and can also be nitrous oxide and other gases which can be ionized under the radio frequency action, and the nitrous oxide and other gases act on the semiconductor layer to recrystallize and nucleate the region corresponding to the semiconductor layer.
At the semiconductor layerAfter finishing the treatment, continuously depositing a passivation layer, and preparing the passivation layer above the channel by a plasma enhanced chemical vapor deposition method, wherein the passivation layer can be SiO2The thickness of the film is 300nm, and the deposition temperature is preferably 300 ℃. And preparing a pixel electrode layer on the passivation layer, and finally forming the structure of the thin film transistor.
The thin film transistor and the method for manufacturing the thin film transistor provided by the embodiment of the present disclosure are described in detail above, and the description of the embodiment is only used to help understanding the technical solution and the core idea of the present disclosure; those of ordinary skill in the art will understand that: it is to be understood that modifications may be made to the arrangements described in the embodiments above, and such modifications or alterations may be made without departing from the spirit of the respective arrangements of the embodiments of the present disclosure.
Claims (10)
1. A thin film transistor, comprising:
a substrate;
a gate layer disposed on the substrate;
an insulating layer disposed on the substrate and covering the gate layer;
a semiconductor layer disposed on the insulating layer; and
the source electrode and the drain electrode are arranged on two opposite sides of the semiconductor layer and are electrically connected with the semiconductor layer;
the semiconductor layer comprises a first semiconductor layer and a second semiconductor layer, the second semiconductor layer is arranged on the first semiconductor layer, and the carrier concentration in the second semiconductor layer is greater than that in the first semiconductor layer.
2. The thin film transistor according to claim 1, wherein a material of the first semiconductor layer is an amorphous oxide, and a material of the second semiconductor layer is a polycrystalline oxide.
3. The thin film transistor according to claim 1, wherein a thickness of the second semiconductor layer is smaller than a thickness of the first semiconductor layer.
4. The thin film transistor according to claim 3, wherein the second semiconductor layer has a thickness of
5. The thin film transistor according to claim 1, wherein a material of the semiconductor layer includes at least one of IGZO, ZIO, AZO, ATO, ZTO, ITO, TiOx, and ZnO.
6. The thin film transistor according to claim 1, wherein the semiconductor layer has a thickness of
7. A preparation method of a thin film transistor is characterized by comprising the following steps:
s100: depositing a gate layer on a substrate;
s101: preparing an insulating layer on the surface of the gate layer;
s102: depositing a semiconductor layer on the insulating layer;
s103: preparing a source electrode and a drain electrode on the semiconductor layer, and carrying out graphical etching;
s104: processing the semiconductor layer to enable the semiconductor layer to form a second semiconductor layer;
s105: and depositing a passivation layer to form the thin film transistor.
8. The method of manufacturing a thin film transistor according to claim 7, wherein the semiconductor layer is treated by a radio frequency plasma process in step S104.
9. The method for manufacturing a thin film transistor according to claim 8, wherein the plasma includes a mixed gas of oxygen and helium or a nitrous oxide gas.
10. The method of claim 8, wherein the RF plasma process has a frequency of 1MHz to 200MHz and a power of 500W to 2000W.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110017990A1 (en) * | 2009-07-24 | 2011-01-27 | Son Kyoung-Seok | Thin-film transistor and method of manufacturing the same |
| CN102246310A (en) * | 2008-12-11 | 2011-11-16 | 株式会社半导体能源研究所 | Thin film transistor and display device |
| CN102484139A (en) * | 2009-10-08 | 2012-05-30 | 株式会社半导体能源研究所 | Oxide semiconductor layer and semiconductor device |
| US20160300951A1 (en) * | 2015-04-13 | 2016-10-13 | Au Optronics Corporation | Active device structure and fabricating method thereof |
| CN106158978A (en) * | 2016-07-08 | 2016-11-23 | 武汉华星光电技术有限公司 | Thin film transistor (TFT), array base palte and preparation method thereof |
-
2019
- 2019-12-03 CN CN201911219953.6A patent/CN111081753A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102246310A (en) * | 2008-12-11 | 2011-11-16 | 株式会社半导体能源研究所 | Thin film transistor and display device |
| US20110017990A1 (en) * | 2009-07-24 | 2011-01-27 | Son Kyoung-Seok | Thin-film transistor and method of manufacturing the same |
| CN102484139A (en) * | 2009-10-08 | 2012-05-30 | 株式会社半导体能源研究所 | Oxide semiconductor layer and semiconductor device |
| US20160300951A1 (en) * | 2015-04-13 | 2016-10-13 | Au Optronics Corporation | Active device structure and fabricating method thereof |
| CN106158978A (en) * | 2016-07-08 | 2016-11-23 | 武汉华星光电技术有限公司 | Thin film transistor (TFT), array base palte and preparation method thereof |
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