CN111081682B - Semiconductor test structure and test method - Google Patents
Semiconductor test structure and test method Download PDFInfo
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- CN111081682B CN111081682B CN201911261700.5A CN201911261700A CN111081682B CN 111081682 B CN111081682 B CN 111081682B CN 201911261700 A CN201911261700 A CN 201911261700A CN 111081682 B CN111081682 B CN 111081682B
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Abstract
The invention provides a semiconductor test structure, comprising: the test structure comprises a main test structure, an auxiliary test structure, two groups of first test pads, at least two second test pads and a first dielectric layer, wherein the second test pads are electrically connected with the main test structure so that the main test structure can be electrically tested through two second test pad sections; further, the present invention also provides a short circuit testing method, comprising: roughly positioning the defect points by using a resistance ratio method to determine a snake-shaped structure where the defect points are located; fine positioning the defect point through the second test pad by using a resistance value variation technology; observing the defect points and collecting SEM images of the defect points; TEM samples were prepared to determine the cause of the main test structure short circuit. Through addding the second test pad, main test structure can divide into multistage test structure for each section test structure all can independently carry out the electrical property test, thereby can effectively find the defect point.
Description
Technical Field
The invention relates to the field of semiconductor testing, in particular to a semiconductor testing structure and a testing method.
Background
The semiconductor manufacturing process is divided into a front-stage device process and a back-stage metal interconnection process, wherein a back-stage metal interconnection layer in the back-stage metal interconnection process is used for leading out a front-stage device in the front-stage device process so as to carry out testing or working. During semiconductor manufacturing, the back-end metal interconnection lines often suffer from short-circuit failures or open-circuit failures, which are mainly due to design problems and process problems. In order to evaluate the design structure and monitor the on-line process stability, complex product structures are extracted individually or are recombined into a repetitive, large-area and convenient-to-Test structure by taking the structure as a unit, the Test structures are electrically tested to obtain a large number of corresponding electrical parameters, and the electrical parameters are analyzed to find problems in advance and solve the problems, and the structure is called a Test-key (Test-key). The test structure is spread over almost all levels in the manufacturing process and it has the characteristics of being easy to test and easy to fail to analyze.
Referring to fig. 1, fig. 1 is a schematic diagram of a prior art test structure, which generally includes: snakelike main test line 11, snakelike auxiliary test line 12 and with the test pad 13 that main test line links to each other, snakelike main test line 11 with snakelike auxiliary test line 12 is parallel to each other just snakelike main test line 11 with snakelike auxiliary test line 12 has the interval, wherein, sets up snakelike auxiliary test line 12's main objective is the homogeneity that improves metal test line space density. And applying a voltage on the test pad 13 to test whether leakage current exists between the snake-shaped main test lines 11 or not so as to judge whether the snake-shaped main test lines 11 have a short circuit problem or not, if the snake-shaped main test lines 11 have the short circuit problem, a failure analysis means is required to find a short circuit point and deduce a root cause causing the short circuit of the snake-shaped main test lines 11, wherein the positioning of the failure point is a very critical step.
Currently, the location of the failure point is usually performed by at least one of the three technologies of the photoresistance changing technology (OBIRCH), the Thermal emission microscopy technology (Thermal) and the electroresistance changing technology (EBIRCH), wherein the electroresistance changing technology is most suitable for being applied in the short circuit test. However, when the short-circuit failure point of a repeated and large-area test structure is positioned by using the resistance value variation technology, the failure point cannot be effectively found, and the position of the positioned failure point is not particularly accurate; in addition, the utilization of the resistance value variation technique to locate the short-circuit failure point of the repeated and large-area test structure also causes the waste of human resources and machine resources.
Disclosure of Invention
The invention aims to provide a semiconductor test structure and a test method, which aim to solve the problem of inaccurate positioning when positioning a short circuit failure point of a repeated and large-area test structure.
To solve the above technical problem, the present invention provides a semiconductor test structure, comprising: the test structure comprises a main test structure, an auxiliary test structure, two groups of first test pads, at least two second test pads and a first dielectric layer, wherein the main test structure, the auxiliary test structure, the first test pads and the second test pads are all arranged on the first dielectric layer, and the two groups of first test pads are respectively arranged at the head end and the tail end of the main test structure;
the auxiliary test structure comprises at least two U-shaped structures, the U-shaped structures are arranged side by side and are centrosymmetric with two adjacent U-shaped structures, the main test structure is arranged between the U-shaped structures, each second test pad is electrically connected with the main test structure so that the main test structure can perform electrical test through each second test pad segment, and a gap is reserved between each second test pad and the U-shaped structure.
Optionally, in the semiconductor test structure, the semiconductor test structure further includes a second dielectric layer and a third dielectric layer, the first dielectric layer, the second dielectric layer and the third dielectric layer are stacked in sequence from bottom to top, a third test pad is arranged on the second dielectric layer, a fourth test pad is arranged on the third dielectric layer, and the first test pad, the third test pad and the fourth test pad are electrically connected.
Optionally, in the semiconductor test structure, the main test structure includes at least two serpentine structures, each serpentine structure includes a plurality of groups of rod portions and a plurality of groups of handle portions, the number of each group of rod portions is two, the number of each group of handle portions is one, each group of rod portions is disposed at two opposite ends of each group of handle portions, the rod portions are perpendicular to the handle portions, and the second test pads are electrically connected to the handle portions.
Optionally, in the semiconductor test structure, an accommodating space is formed between each handle portion and two adjacent rod portions.
Optionally, in the semiconductor test structure, the U-shaped structure is disposed in the accommodating space, and the U-shaped structure is parallel to the serpentine structure.
Optionally, in the semiconductor test structure, the U-shaped structure includes a plurality of U-shaped metal lines parallel to each other.
Optionally, in the semiconductor test structure, a first plug is disposed in the second dielectric layer, a second plug is disposed in the third dielectric layer, a head end and a tail end of the U-shaped metal line are electrically connected to the first plug, and the first plug is electrically connected to the second plug.
Optionally, in the semiconductor test structure, the U-shaped metal line is made of copper, and the first plug and the second plug are made of copper.
Optionally, in the semiconductor test structure, the auxiliary test structure further includes a plurality of finger structures, the finger structures are disposed on two sides of the rod portion of the serpentine structure far away from the U-shaped structure, and the finger structures are parallel to the U-shaped structure and the rod portion.
Optionally, in the semiconductor test structure, the main test structure includes at least two serpentine metal lines parallel to each other.
Optionally, in the semiconductor test structure, the main test structure is made of copper.
Based on the same inventive concept, the invention also provides a short circuit testing method, which comprises the following steps:
placing two probes on the fourth test pad of the third dielectric layer respectively to detect whether the main test structure on the first dielectric layer is short-circuited, wherein one probe is connected with forward bias voltage, the other probe is grounded, and after the main test structure is confirmed to be short-circuited, a resistance ratio method is used for roughly positioning a defect point to determine a snake-shaped structure where the defect point is located;
stripping the third dielectric layer and a partial thickness of the second dielectric layer from the semiconductor test structure;
bombarding the second dielectric layer with the residual thickness by using a focused ion beam until the second test pad electrically connected with the serpentine structure on the first dielectric layer is exposed;
respectively placing two probes on the second test bonding pad, finely positioning the defect point by using a resistance value variation technology, and determining a local area with the defect point, wherein one probe is connected with a forward bias voltage, and the other probe is grounded;
observing the defect point by using a scanning electron microscope, and acquiring a scanning electron microscope image of the local area by using scanning equipment;
preparing a transmission electron microscope sample from the scanning electron microscope image to determine the cause of the short circuit of the main test structure.
In summary, the present invention provides a semiconductor test structure, comprising: the device comprises a main test structure, an auxiliary test structure, two groups of first test pads, at least two second test pads and a first dielectric layer, wherein the auxiliary test structure comprises at least two U-shaped structures, and the second test pads are electrically connected with the main test structure; further, the present invention also provides a short circuit testing method, comprising: roughly positioning the defect points by using a resistance ratio method to determine a snake-shaped structure where the defect points are located; fine positioning the defect point through the second test pad by using a resistance value variation technology; observing the defect spot and collecting a scanning electron microscope image (SEM image) thereof; transmission electron microscope samples (TEM samples) were prepared to determine the cause of the main test structure short circuit. Wherein, through the second test pad with main test structure electrical property links to each other, main test structure can divide into multistage test structure for each section test structure homoenergetic test can independently carry out the test of electric property in order to realize that large tracts of land test structure divides segmentation detects, can conveniently find the defect point effectively like this, makes the location of defect point more accurate, has also saved manpower resources and board resource simultaneously, has improved efficiency of software testing.
Drawings
FIG. 1 is a schematic diagram of a prior art test structure;
FIG. 2 is a schematic diagram of a semiconductor test structure according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a main test structure of an embodiment of the present invention;
FIG. 4 is a schematic diagram of an auxiliary test structure according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a proportional resistance method according to an embodiment of the present invention;
wherein the reference numbers indicate:
11-main test line, 12-auxiliary test line, 13-test pad;
110-main test structure, 111-serpentine structure, 120-auxiliary test structure, 121-U structure, 122-finger structure, 130-first test pad, 140-second test pad, 200-defect point.
Detailed Description
The semiconductor test structure and the test method according to the present invention will be described in detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention. Further, the structures illustrated in the drawings are often part of actual structures. In particular, the drawings may have different emphasis points and may sometimes be scaled differently.
Referring to fig. 2, fig. 3 and fig. 4, fig. 2 is a schematic diagram of a semiconductor test structure according to an embodiment of the present invention, fig. 3 is a schematic diagram of a main test structure according to an embodiment of the present invention, and fig. 4 is a schematic diagram of an auxiliary test structure according to an embodiment of the present invention. As shown in fig. 2, the semiconductor test structure includes: the main test structure 110, assist test structure 120, two sets of first test pads 130, two at least second test pads 140 and first dielectric layer 100, main test structure 110 assist test structure 120, two sets of first test pads 130 and second test pads 140 all locate on the first dielectric layer 100, first test pads 130 are located respectively the head end and the end of main test structure 110, usually first test pads 130 pass through the wire with main test structure 110 electric connection. Further, as shown in fig. 4, the auxiliary test structure 120 includes at least two U-shaped structures 121, the U-shaped structures 121 are arranged side by side and the two adjacent U-shaped structures 121 are centrosymmetric, the main test structure 110 is disposed between the U-shaped structures 121, each of the second test pads 140 is electrically connected to the main test structure 110 through a wire, so that the main test structure 110 performs an electrical test through the second test pads 140 in a segmented manner, and a space is provided between the second test pads 140 and the U-shaped structures 121.
Further, the semiconductor test structure further includes a second dielectric layer and a third dielectric layer (not shown), the first dielectric layer 100, the second dielectric layer and the third dielectric layer are sequentially stacked from bottom to top, a third test pad is disposed on the second dielectric layer, a fourth test pad is disposed on the third dielectric layer, the first test pad 130, the third test pad and the fourth test pad are electrically connected, and the fourth test pad can detect the electrical property of the main test structure on the first dielectric layer 100 on the third dielectric layer, that is, the main test structure 110 can be effectively monitored whether there is a short circuit or an open circuit fault without grinding and removing the third dielectric layer and the second dielectric layer.
The inventor has found that, when the defect point is located by using the electrical resistance variation technology, if the area of the main test structure 110 is too large (larger than 1E5 μm)2) In this case, the technology of changing the electrical resistance value cannot effectively find the position of the defect point, so the inventor of the present invention proposes a method of performing a segment test on the main test structure 110.
As shown in fig. 3, the main test structure 110 includes at least two serpentine structures 111, each serpentine structure 111 includes a plurality of groups of stems and a plurality of groups of stems, each group of stems includes two segments, each group of stems includes one segment, each group of stems is disposed at two opposite ends of each group of stems, the stems are perpendicular to the stems, the second test pads 140 are electrically connected to the stems, and each serpentine structure 111 has an area smaller than 1E5 μm2Therefore, the subsequent electric resistance value change technology used for detecting the defect point can be effectively and accurately positioned at the defect point, the main test structure is divided into at least two small-area serpentine structures 111, and the second test pad 140 detects each short circuit or open circuit fault of the serpentine structures, so that each section of test structure can independently perform electric performance test to realize large-area test structure segmentation detection, the defect point can be conveniently and quickly found, the defect point is more accurately positioned, and manpower resources and machine resources are saved simultaneouslyThe test efficiency is improved by the platform resources.
An accommodating space 160 is formed between each handle portion and two adjacent rod portions, the U-shaped structure 121 is disposed in the accommodating space 160, the U-shaped structure 121 is parallel to the serpentine structure 111, the U-shaped structure 121 and the serpentine structure 111 are not in contact with each other, and the U-shaped structure 121 mainly plays a role in improving the uniformity of the density of the main test structures (metal test lines) on the first dielectric layer.
Further, the U-shaped structure 121 includes a plurality of U-shaped metal lines parallel to each other. Preferably, a first plug is disposed in the second dielectric layer, a second plug is disposed in the third dielectric layer, the U-shaped structure 121 is electrically connected to the first plug, and the first plug is electrically connected to the second plug, that is, the U-shaped structure 121 can be led to the third dielectric layer (top layer) through the first plug and the second plug. The U-shaped metal wire is made of copper, and the first plug and the second plug are made of copper. As can be seen from fig. 2, the two sides of the main test structure 110 are exposed at the outermost layer, so that on one hand, the position for disposing the second test pad 140 can be reserved, and on the other hand, the second test pad 140 is not in contact with the U-shaped metal line and is only electrically connected with the main test structure 110, thereby providing a necessary precondition for the serpentine structure 111 to be capable of performing a segmented electrical test.
Preferably, as shown in fig. 4, the secondary test structure 120 further includes a plurality of fingers 122, the fingers 122 are disposed on two sides of the rod portion of the serpentine structure 111 away from the U-shaped structure 121, and the fingers 122 are disposed in parallel with the U-shaped structure 121 and the rod portion. Likewise, the finger 122 functions as the U-shaped structure 121, and is also used to assist in testing the serpentine 111 for short defects or open defects.
Further, the main test structure 110 includes at least two serpentine metal lines parallel to each other, and the main test structure 110 is made of copper.
Based on the same inventive concept, the invention also provides a short circuit testing method, which comprises the following steps:
firstly, two probes are respectively placed on the fourth test pad of the third dielectric layer to detect whether the main test structure 110 on the first dielectric layer is short-circuited, wherein one probe is forward biased, and the other probe is grounded, after the main test structure 110 is confirmed to be short-circuited, the defect point 200 is coarsely positioned by using a resistance ratio method to determine the serpentine structure 111 where the defect point 200 is located. Specifically, referring to fig. 5, fig. 5 is a schematic diagram of a proportional resistance method according to an embodiment of the present invention, in which the main test structure 110 is pre-disposed on the first dielectric layer, so that whether the main test structure 110 on the first dielectric layer is short-circuited can be directly detected on a third dielectric layer by using a probe, and the resistance ratio method is used to coarsely position a defect point 200 to determine in which serpentine 111 of the first dielectric layer the defect point 200 is specifically located. As shown in fig. 5, the main test structure 110 is simplified into two metal lines, two ends of each of the two metal lines are connected to the two first test pads 130, and when a short-circuit fault occurs in the metal line due to the defect point 200, the defect point 200 can be regarded as having a resistance value R3, the metal line can be regarded as having a resistance value R4 and a resistance value R4 is known, wherein the resistance values of the AF section and the CE section are R1, the resistance values of the BF section and the DE section are R2, the resistance value of the CA section is 2R1+ R3, and the resistance value of the DA section is R1+ R2+ R3-R4 + R3, so as to calculate the resistance values of R1 and R3. Since the resistance value is proportional to the length of the metal line, wherein the lengths of AB and CD are known, the length of af (ce) or bf (ed) is calculated by using the ratio of R1/R4, so that the serpentine structure 111 where the defect point 200 is located is quickly determined without grinding to remove (strip) the rest of the dielectric layers on the first dielectric layer (the main test structure), thereby improving the working efficiency.
Then, the third dielectric layer and a partial thickness of the second dielectric layer are stripped from the semiconductor test structure. Specifically, when the main test structure 110 is detected to have a short-circuit defect, the third dielectric layer and a part of the thickness of the second dielectric layer need to be sequentially stripped from the semiconductor test structure, and the remaining thickness of the second dielectric layer is left.
Further, the second dielectric layer with the remaining thickness is bombarded by a Focused Ion Beam (FIB) until the second test pad 140 on the first dielectric layer 100 electrically connected to the serpentine structure 111 is exposed. Specifically, the second dielectric layer with the remaining thickness is bombarded by the focused ion beam to expose the second test pad 140 for facilitating the subsequent more detailed short circuit analysis.
Next, two probes are respectively placed on the two second test pads 140, the defective point 200 is finely located by using a resistance value variation technique, and a local area having the defective point 200 is determined, wherein one probe is connected to a forward bias voltage, and the other probe is connected to a ground. Specifically, the defect point 200 is finely positioned by using an electric resistance value changing technology, the electric resistance value changing technology is to scan the surface of the device by using an electron beam under a constant voltage, the position of the defect point is positioned by inducing resistance change through the electron beam and detecting the variable quantity of current of the induced point, and the electric resistance value changing technology is high in positioning precision and can detect a short circuit with a leakage current of nA level.
Next, the defect point 200 is observed with a Scanning Electron Microscope (SEM), and a scanning electron microscope image (SEM image) of the local area is acquired with a scanning apparatus.
Finally, transmission electron microscope samples (TEM samples) were prepared from the SEM images to determine the cause of the short circuit of the primary test structure 110. Specifically, a TEM sample is prepared by using a focused ion beam, the TEM sample is a cross-sectional sample of the top view angle of the serpentine structure 111 where the defect point 200 is located, and the cause of the short circuit of the main test structure 110 is determined by analyzing the TEM sample and observing the defect point 200.
In summary, the present invention provides a semiconductor test structure, comprising: the device comprises a main test structure, an auxiliary test structure, two groups of first test pads, at least two second test pads and a first dielectric layer, wherein the auxiliary test structure comprises at least two U-shaped structures, and the second test pads are electrically connected with the main test structure; further, the present invention also provides a short circuit testing method, comprising: roughly positioning the defect points by using a resistance ratio method to determine a snake-shaped structure where the defect points are located; fine positioning the defect point through the second test pad by using a resistance value variation technology; observing the defect spot and collecting a scanning electron microscope image (SEM image) thereof; transmission electron microscope samples (TEM samples) were prepared to determine the cause of the main test structure short circuit. Wherein, through the second test pad with main test structure electrical property links to each other, main test structure can divide into multistage test structure for each section test structure homoenergetic test can independently carry out the test of electric property in order to realize that large tracts of land test structure divides segmentation detects, can conveniently find the defect point effectively like this, makes the location of defect point more accurate, has also saved manpower resources and board resource simultaneously, has improved efficiency of software testing.
The above description is only for the purpose of describing the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention, and any variations and modifications made by those skilled in the art based on the above disclosure are within the scope of the appended claims.
Claims (11)
1. A semiconductor test structure, comprising: the test structure comprises a main test structure, an auxiliary test structure, two groups of first test pads, at least two second test pads and a first dielectric layer, wherein the main test structure, the auxiliary test structure, the first test pads and the second test pads are all arranged on the first dielectric layer, and the two groups of first test pads are respectively arranged at the head end and the tail end of the main test structure;
the auxiliary test structure comprises at least two U-shaped structures, the U-shaped structures are arranged side by side, the adjacent two U-shaped structures are centrosymmetric, the main test structure is arranged between the U-shaped structures, each second test pad is electrically connected with the main test structure so that the main test structure can perform electrical test through each second test pad section, and a gap is formed between each second test pad and the U-shaped structure;
the main test structure comprises at least two serpentine structures, each serpentine structure comprises a plurality of groups of rod parts and a plurality of groups of handle parts, the number of each group of rod parts is two sections, the number of each group of handle parts is one section, each group of rod parts is arranged at each group of two opposite ends of each handle part, the second test pads are electrically connected with the handle parts, and the area of each serpentine structure is smaller than 1E5 mu m 2.
2. The semiconductor test structure of claim 1, further comprising a second dielectric layer and a third dielectric layer, wherein the first dielectric layer, the second dielectric layer and the third dielectric layer are stacked in sequence from bottom to top, a third test pad is disposed on the second dielectric layer, a fourth test pad is disposed on the third dielectric layer, and the first test pad, the third test pad and the fourth test pad are electrically connected.
3. The semiconductor test structure of claim 2, wherein each handle portion and two adjacent rod portions form a receiving space therebetween.
4. The semiconductor test structure of claim 3, wherein the U-shaped structure is disposed in the accommodating space, and the U-shaped structure is parallel to the serpentine structure.
5. The semiconductor test structure of claim 4, wherein the U-shaped structure comprises a plurality of U-shaped metal lines parallel to each other.
6. The semiconductor test structure of claim 5, wherein a first plug is disposed in the second dielectric layer, a second plug is disposed in the third dielectric layer, a head end and a tail end of the U-shaped metal line are electrically connected to the first plug, and the first plug is electrically connected to the second plug.
7. The semiconductor test structure of claim 6, wherein the U-shaped metal line is made of copper, and the first plug and the second plug are both made of copper.
8. The semiconductor test structure of claim 2, wherein the secondary test structure further comprises fingers disposed on opposite sides of the stem portion of the serpentine structure away from the U-shaped structure, the fingers being disposed parallel to the U-shaped structure and the stem portion.
9. The semiconductor test structure of claim 1, wherein the main test structure comprises at least two serpentine metal lines parallel to each other.
10. The semiconductor test structure of claim 1, wherein the main test structure is copper.
11. A short circuit test method for a semiconductor test structure as claimed in claim 2, characterized in that it comprises:
placing two probes on the fourth test pad of the third dielectric layer respectively to detect whether the main test structure on the first dielectric layer is short-circuited, wherein one probe is connected with forward bias voltage, the other probe is grounded, and after the main test structure is confirmed to be short-circuited, a resistance ratio method is used for roughly positioning a defect point to determine a snake-shaped structure where the defect point is located;
stripping the third dielectric layer and a partial thickness of the second dielectric layer from the semiconductor test structure;
bombarding the second dielectric layer with the residual thickness by using a focused ion beam until the second test pad electrically connected with the serpentine structure on the first dielectric layer is exposed;
respectively placing two probes on the second test bonding pad, finely positioning the defect point by using a resistance value variation technology, and determining a local area with the defect point, wherein one probe is connected with a forward bias voltage, and the other probe is grounded;
observing the defect point by using a scanning electron microscope, and acquiring a scanning electron microscope image of the local area by using scanning equipment;
preparing a transmission electron microscope sample from the scanning electron microscope image to determine the cause of the short circuit of the main test structure.
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| JP2861849B2 (en) * | 1994-08-31 | 1999-02-24 | 日本電気株式会社 | Wiring test method and device on semiconductor integrated circuit chip |
| KR20070087846A (en) * | 2005-12-28 | 2007-08-29 | 동부일렉트로닉스 주식회사 | Test pattern and method for analyzing delay characterization of interconnection line |
| CN206584011U (en) * | 2017-01-12 | 2017-10-24 | 中芯国际集成电路制造(北京)有限公司 | A kind of test structure for detecting metal line bridging |
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| CN101826510A (en) * | 2009-03-04 | 2010-09-08 | 恩益禧电子股份有限公司 | TCP N-type semiconductor N device |
| CN102023236A (en) * | 2009-09-11 | 2011-04-20 | 中芯国际集成电路制造(上海)有限公司 | Test structure and test method |
| CN110400788A (en) * | 2018-04-25 | 2019-11-01 | 无锡华润上华科技有限公司 | A kind of test structure and test method checking semiconductor device design rule |
| CN109490758A (en) * | 2018-12-12 | 2019-03-19 | 上海华力集成电路制造有限公司 | A kind of localization method of short-circuit failure |
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