CN111050493A

CN111050493A - Method for determining shape of via hole reverse pad and printed circuit board

Info

Publication number: CN111050493A
Application number: CN201811190793.2A
Authority: CN
Inventors: 孙跃
Original assignee: ZTE Corp
Current assignee: ZTE Corp
Priority date: 2018-10-12
Filing date: 2018-10-12
Publication date: 2020-04-21
Anticipated expiration: 2038-10-12
Also published as: WO2020073857A1; CN111050493B

Abstract

The application provides a method for determining the shape of a via hole reverse pad and a printed circuit board, wherein the method comprises the following steps: the method comprises the steps of obtaining the position of a via hole stub in a PCB, determining the diameter of via hole anti-bonding pads of a plurality of plane layers in the PCB according to the position of the stub, and solving the problem of low impedance consistency of all via holes in the related technology by adopting the scheme to reduce the influence of the via hole stub on the via hole impedance as much as possible due to the fact that the via hole anti-bonding pads and the via hole stub have influence on the via hole impedance, so that the higher consistency of the via hole impedance is ensured.

Description

Method for determining shape of via hole reverse pad and printed circuit board

Technical Field

The application relates to the field of communication, in particular to a method for determining the shape of a via hole anti-pad and a printed circuit board.

Background

In the related art, in the design of the PCB, when designing a layer-changing via hole used for a signal line due to a layer-changing requirement or a press-connecting via hole of a connector, the design of such a via hole is completed based on two aspects:

first, considering a processing process, in general, fig. 1 is a schematic view of via hole components of a PCB according to the related art, and as shown in fig. 1, an effective signal via hole is composed of four parts: via hole aperture, pad, anti-pad and stub.

Secondly, the SI technology considers that one of the key factors affecting the signal integrity is the impedance continuity of the via, and the via impedance is related to all the above four factors.

The impedance of a via is strongly related to its constituent parts. In actual processing, certain limiting requirements are imposed on the sizes of the via hole diameter and the bonding pad of the determined PCB plate material and the thickness of the PCB plate.

In order to solve the problem of impedance discontinuity at the via, the conventional design method mainly includes digging up an anti-pad to increase the impedance at the via, and fig. 2 is a schematic diagram of the conventional via anti-pad design according to the related art, which has the effect of actually increasing the impedance value of the via, but actually the impedance at the via is entirely increased, and a part (a part not to be increased) which is already large enough before is forced to be increased. Fig. 3 is a schematic diagram illustrating a change in impedance of a via according to a design manner in the related art, as shown in fig. 3, it can be seen from the above that the conventional design for the via improves the impedance at the via as a whole, and there is a defect that the impedance is further raised for a portion of the via where the impedance does not need to be increased, thereby having a certain negative effect on the continuity of the impedance at the via.

Aiming at the problem of low impedance consistency at all positions of a via hole in the related art, no effective solution is available at present.

Disclosure of Invention

The embodiment of the application provides a method for determining the shape of a via hole reverse pad and a printed circuit board, which are used for at least solving the problem of low impedance consistency at all positions of via holes in related technologies.

According to an embodiment of the present application, there is provided a method for determining a via antipad shape, including: acquiring the position of a via hole stub in a PCB to be laid with a via hole anti-pad; and determining the diameter of the via hole anti-bonding pad of one or more plane layers of the PCB according to the position of the via hole stub.

According to another embodiment of the present document, there is also provided a printed circuit board PCB board including: a plurality of planar layers, wherein a diameter of the via antipad of each planar layer decreases as a distance between each planar layer and the via stub location increases.

According to a further embodiment of the present application, there is also provided a storage medium having a computer program stored therein, wherein the computer program is arranged to perform the steps of any of the above method embodiments when executed.

According to yet another embodiment of the present application, there is also provided an electronic device, comprising a memory in which a computer program is stored and a processor arranged to run the computer program to perform the steps of any of the above method embodiments.

Through this application, acquire the position of the via hole stub in the PCB, confirm the diameter of the anti-pad of via hole of a plurality of plane layers in the PCB board according to the position of this stub, because the anti-pad of via hole and via hole stub all have the influence to the via hole impedance, adopt above-mentioned scheme in order to minimize the influence of via hole stub to the via hole impedance, solved the problem that the impedance uniformity everywhere of via hole is low among the correlation technique, guaranteed the higher uniformity of via hole impedance.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:

fig. 1 is a schematic view of a via hole part of a PCB panel according to the related art;

FIG. 2 is a schematic diagram of a conventional via antipad design according to the related art;

FIG. 3 is a schematic diagram illustrating a variation in via resistance according to a design of the related art;

FIG. 4 is a flow chart of a method of determining via antipad shape according to an embodiment of the present application;

FIG. 5 is a schematic view of a funnel-shaped via anti-pad design according to another embodiment of the present application;

FIG. 6 is a schematic diagram of a via antipad design according to specific embodiment 1;

FIG. 7 is a schematic diagram of a via antipad design according to specific embodiment 2;

FIG. 8 is a comparison of via return loss in accordance with another embodiment of the present application;

FIG. 9 is a schematic diagram comparing via impedances according to another embodiment of the present application;

FIG. 10 is a schematic view of an exemplary PCB stack according to the present document;

FIG. 11 is a return loss contrast chart according to example 2 of the present application;

fig. 12 is an impedance comparison diagram according to example 2 of the present application.

Detailed Description

The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.

It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.

The technical scheme of this document can be used for when designing the PCB board, to the via hole that has the stub, can adopt the scheme of this document to design the anti-pad of via hole on every plane layer.

Alternatively, the determination method of the via anti-pad shape according to the present application may be executed by a computer terminal, that is, the computer terminal performs simulation, calculates the via anti-pad of each planar layer, and then manufactures the corresponding PCB board.

Example one

In the present embodiment, a method for determining a via antipad shape is provided, and fig. 4 is a flowchart of a method for determining a via antipad shape according to an embodiment of the present application, as shown in fig. 4, the flowchart includes the following steps:

s402, acquiring the position of a via hole stub in the PCB to be distributed with the via hole anti-pad;

and S404, determining the diameter of the via hole anti-bonding pad of one or more plane layers of the PCB according to the position of the via hole stub.

Through the steps, the positions of the via hole stubs in the PCB are obtained, the diameters of the via hole anti-bonding pads of the multiple plane layers in the PCB are determined according to the positions of the via hole stubs, and due to the fact that the via hole anti-bonding pads and the via hole stubs have influences on the impedance of the via holes, the influences of the via hole stubs on the impedance of the via holes are reduced as much as possible by adopting the scheme, the problem that the impedance consistency of all the via holes in the related technology is low is solved, and the high consistency of the impedance of the via holes is guaranteed.

The size of the anti-pad, the position or length of the stub, and both are factors that affect the via impedance.

Optionally, determining a diameter of a via anti-pad of one or more planar layers of the PCB board according to the position of the via stub includes: determining a distance between each planar layer and a location of the stub; determining a diameter of the via antipad of each planar layer to decrease with increasing distance.

Alternatively, the diameter may be inversely proportional to the distance.

Optionally, determining a diameter of a via anti-pad of one or more planar layers of the PCB board according to the position of the via stub includes: determining two outgoing line layers A and B of the via hole, wherein A is a top layer or a bottom layer, B is an inner layer, and a stub exists on one side of B; determining via anti-pad diameters S1 of adjacent planar layers of A through simulation; determining via anti-pad diameter S2 of the adjacent planar layer on side B through simulation; according to the S1 and S2, the diameter of the via anti-pad of each planar layer is determined. The final shape of the via hole reverse pad layout designed in the embodiment can be trapezoidal, that is, the diameter of the via hole reverse pad close to the stub is large, and the diameter of the via hole reverse pad is reduced with the increase of the distance, so that the final multilayer plane layer is trapezoidal.

Optionally, the diameter of the via anti-pad of each planar layer is determined according to the distance between the planar layers A and B and the distance between the planar layers S1 and S2.

Optionally, determining a diameter of a via anti-pad of one or more planar layers of the PCB board according to the position of the via stub includes: determining two outgoing line layers C and D of the via hole, wherein A and B are inner layers, and stubs exist in C and D; determining a via anti-pad diameter of the adjacent planar layer on side C by simulation S4, and determining a via anti-pad diameter of the adjacent planar layer on side D by simulation S5; determining the position of a middle plane layer according to the length of the stub at the position C and the length of the stub at the position D, wherein the diameter of a via hole anti-pad of the middle plane layer is the shortest; determining via antipad diameter of the midplane layer by simulation S6; according to the S4, S5, and S6, a diameter of the via anti-pad of each planar layer is determined. In the scheme of this embodiment, because the stubs are located at both sides, the final via hole anti-pads of the multiple planar layers have large diameters at both ends, and the via hole anti-pad of the middle planar layer has the smallest diameter, that is, two trapezoids.

Optionally, the position of the middle plane layer is determined according to the ratio of the length of the stub at the position C to the length of the stub at the position D.

Optionally, the diameter of the via anti-pad of each planar layer is determined according to the distances of the planar layers between the C and D from each other, and the S4, S5 and S6.

The following description will be made in conjunction with another embodiment of the present document.

Through the via hole model after comprehensive analysis actual processing, the impedance of forced most part is strong relevant with the stub that leaves certain length behind the via hole back drilling in whole impedance, mainly has following three points:

1) the capacitive effect of the stub pulls down the impedance of the via hole;

2) the influence of the stub on the z-axis of the via hole is not consistent, namely the stub has large influence on the part of the via hole close to the stub on the z-axis of the via hole and has small influence on the part far away from the stub;

3) the anti-bonding pad is enlarged, so that the via capacitance can be reduced, and the impedance is improved.

If larger reverse bonding pads with the same size are dug in all the plane layers, the impedance of the via holes at the stub positions is improved, and the impedance of the via holes far away from the stub positions is larger. The method improves the impedance of the via hole to a certain degree, but the consistency of the impedance of the via hole cannot be ensured.

The technical problem to be solved by the invention is as follows: in order to overcome the defect that the impedance continuity is affected due to the fact that the overall impedance of a via hole in the prior art is improved, the invention provides a funnel-shaped via hole reverse pad, reverse pads with different sizes are dug on different plane layers aiming at the influence of a stub, namely the reverse pad near the stub is larger, the size of the reverse pad is gradually reduced as the reverse pad is farther away from the stub, fig. 5 is a design schematic diagram of the funnel-shaped via hole reverse pad according to another embodiment of the application, and as shown in fig. 5, the impedance of the via hole at the stub is improved as the reverse pad near the stub is larger; and the reverse bonding pad far away from the stub is smaller, so that the impedance of the via hole at the position is ensured not to be too large. The method can well improve the return loss and the impedance of the via hole and ensure the consistency of the impedance of the via hole on the z axis.

In embodiment 1, it is assumed that the via has two outgoing layers A, B, a being a TOP or BOTTOM layer and B being an inner layer.

The via antipad diameter S1 of the plane layer adjacent to line a was determined by simulation, and the via antipad diameters S2, S3 of the plane layer adjacent to line B were determined by simulation.

Other planar layer anti-pad diameters (e.g., 1, 2, 3) can be linearly calculated from S1, S2 and their positions on the z-axis, and fig. 6 is a schematic diagram of a via anti-pad design according to specific example 1.

In embodiment 2, it is assumed that the via hole has two outgoing line layers a and B, and both a and B are inner layers. The stub length at A is L1, and the stub length at B is L2. Via antipad diameters S1, S2 of the plane layers adjacent to line a were determined by simulation, and via antipad diameters S3, S4 of the plane layers adjacent to line B were determined by simulation. The position of the planar layer 2 is determined (L1/L2 ═ L3/L4 should be satisfied on the via), the via anti-pad diameter S5 of the planar layer 2 is determined by simulation, and the other planar layer anti-pad diameters (e.g. 1, 3) can be calculated by S2, S3, S5 and their position linearity on the z-axis. FIG. 7 is a schematic diagram of a via antipad design according to specific embodiment 2.

Fig. 8 is a diagram illustrating via return loss comparison according to another embodiment of the present application, as shown in fig. 8, the initial case (ori), the conventional (ini) and the "funnel" (opt) design method.

Fig. 9 is a schematic diagram of a via impedance comparison according to another embodiment of the present application, as shown in fig. 9, comparing the initial case (ori), the conventional (ini) and the "funnel" (opt) design method.

In the solution of the present document, there are two features:

1. in via anti-pad design, anti-pads of different sizes are dug in different planar layers.

2. In the design of the via hole anti-bonding pad, the via hole anti-bonding pad dug near the stub is larger, the size of the anti-bonding pad is gradually reduced as the via hole anti-bonding pad is farther away from the stub, and the shape of the anti-bonding pad is similar to a funnel.

In order to make the purpose, technical scheme and advantages of the present invention more clear, the following detailed description of the specific design method of the present invention is made with reference to the accompanying drawings:

fig. 10 is a schematic diagram of an exemplary PCB stack according to the present document, as shown in fig. 10, illustrating an exemplary PCB stack.

Example 1

Assuming that a high speed differential signal is fanned out from the inner layer L14, through the via swap layer to the TOP layer, the via stub length is 8 mils.

First, the diameter S1 of the via anti-pad of the TOP layer adjacent planar layer (L2) is determined to be 27.56mil by simulation.

And step two, determining the diameters S2 and S3 of via hole anti-bonding pads of two adjacent planar layers (L13 and L15) of the routing layer L14 to be 39.56mil through simulation.

Step three, the distance from the TOP layer to the L13 layer is 68.8mil, and the diameter of the anti-pad is 39.56 mil; the distance from the TOP layer to the L2 layer was 4.8 mils and the diameter of the anti-pad used was 27.56 mils. Assuming that the distance from the TOP layer to other layers is L, if the diameter of the anti-pad is S, the following equation is satisfied:

the anti-pad diameters for the other layers were calculated as shown in table 1 below:

TABLE 1

Planar layer	Distance/mil from top layer to corresponding layer	Diameter/mil of anti-pad
			L2	4.8	S₁＝27.56
L4	16	29.66
			L6	27.2	31.76
L8	38.4	33.86
			L9	44.6	35.02
L10	50.8	36.18
			L11	57	37.34
L13	68.8	S₂＝39.56
			L15	80	S₃＝39.56

The return loss and impedance ratio of example 1 is shown in fig. 8 and 9.

Example 2

Assume that a high speed differential signal is fanned out from inner layer L3, through the via switch layer, to inner layer L14. The via stub length is 8 mil.

Firstly, determining the diameters S1 and S2 of via hole anti-bonding pads of two adjacent planar layers (L2 and L4) of the routing layer L3 to be 41.56mil through simulation.

And step two, determining the diameters S3 and S4 of via hole anti-bonding pads of two adjacent planar layers (L13 and L15) of the routing layer L14 to be 41.56mil through simulation.

And step three, determining the position of the plane layer 2, wherein the position of the plane layer 2 is in the middle of L3 and L14 because the stubs on the two sides of the via hole are both 8 mil. I.e., the distance from the TOP layer to the corresponding layer, while the position of the L9 layer is at 44.6 mils, so planar layer 2 is L9. The via antipad diameter S5 of L9 was then determined by simulation to be 27.56 mil.

Step four, if the diameter of the anti-bonding pads adopted by the L6 and the L8 is S, assuming that the distance from the TOP layer to the L6 and the L8 is L, the following equation is satisfied:

if the diameters of the anti-pads used for L10 and L11 are S ', the distance from the TOP layer to L10 and L11 is L', and the following equation is satisfied:

the anti-pad diameters for the other layers were calculated as shown in table 2 below:

TABLE 2

Planar layer	Distance/mil from top layer to corresponding layer	Diameter/mil of anti-pad
			L2	4.8	S₁＝41.56
L3	10.4	/
			L4	16	S₂＝41.56
L6	27.2	36.08
			L8	38.4	30.60
L9	44.6	S₅＝27.56
			L10	50.8	31.15
L11	57	34.73
			L13	68.8	S₃＝41.56
L14	74.4	/
			L15	80	S₄＝41.56

Fig. 11 is a return loss contrast graph according to example 2 of the present application, and shows the via return loss contrast for the initial case (ori), the conventional (ini), and the "funnel" (opt) design method, as shown in fig. 11.

Fig. 12 is a schematic impedance comparison according to example 2 of the present application, and shows the initial case (ori), the conventional (ini) and the via impedance comparison of the "funnel" (opt) design method as shown in fig. 12.

The consistency of improvement via hole impedance that this scheme of adoption can be very big reduces via hole return loss and improves via hole impedance.

Through the above description of the embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but the former is a better implementation mode in many cases. Based on such understanding, the technical solutions of the present application may be embodied in the form of a software product, which is stored in a storage medium (e.g., ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal device (e.g., a mobile phone, a computer, a server, or a network device) to execute the method according to the embodiments of the present application.

Example two

EXAMPLE III

Embodiments of the present application also provide a storage medium. Alternatively, in the present embodiment, the storage medium may be configured to store program codes for performing the following steps:

s1, acquiring the position of the via stub in the PCB to be laid with the via hole anti-pad;

and S2, determining the diameter of the via hole anti-pad of one or more plane layers of the PCB board according to the position of the via hole stub.

Optionally, in this embodiment, the storage medium may include, but is not limited to: a U-disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a removable hard disk, a magnetic or optical disk, and other various media capable of storing program codes.

Embodiments of the present application further provide an electronic device comprising a memory having a computer program stored therein and a processor configured to execute the computer program to perform the steps of any of the above method embodiments.

Optionally, the electronic apparatus may further include a transmission device and an input/output device, wherein the transmission device is connected to the processor, and the input/output device is connected to the processor.

Optionally, in this embodiment, the processor may be configured to execute the following steps by a computer program:

Optionally, the specific examples in this embodiment may refer to the examples described in the above embodiments and optional implementation manners, and this embodiment is not described herein again.

It will be apparent to those skilled in the art that the modules or steps of the present application described above may be implemented by a general purpose computing device, they may be centralized on a single computing device or distributed across a network of multiple computing devices, and alternatively, they may be implemented by program code executable by a computing device, such that they may be stored in a storage device and executed by a computing device, and in some cases, the steps shown or described may be performed in an order different than that described herein, or they may be separately fabricated into individual integrated circuit modules, or multiple ones of them may be fabricated into a single integrated circuit module. Thus, the present application is not limited to any specific combination of hardware and software.

The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for determining a via anti-pad shape, comprising:

acquiring the position of a via hole stub in a PCB to be laid with a via hole anti-pad;

and determining the diameter of the via hole anti-bonding pad of one or more plane layers of the PCB according to the position of the via hole stub.

2. The method of claim 1, wherein determining a diameter of a via antipad of one or more planar layers of the PCB board as a function of the location of the via stub comprises:

determining a distance between each planar layer and a location of the stub;

determining a diameter of the via antipad of each planar layer to decrease with increasing distance.

3. The method of claim 1, wherein determining a diameter of a via antipad of one or more planar layers of the PCB board as a function of the location of the via stub comprises:

determining two outgoing line layers A and B of the via hole, wherein A is a top layer or a bottom layer, B is an inner layer, and a stub exists on one side of B;

determining via anti-pad diameters S1 of adjacent planar layers of A through simulation;

determining via anti-pad diameter S2 of the adjacent planar layer on side B through simulation;

according to the S1 and S2, the diameter of the via anti-pad of each planar layer is determined.

4. The method of claim 3, wherein determining the diameter of the via antipad for each planar layer according to the S1 and S2 comprises:

determining the diameter of the via anti-pad of each planar layer according to the S1 and S2 and the distance of the planar layers between A and B from each other.

5. The method of claim 1, wherein determining a diameter of a via antipad of one or more planar layers of the PCB board as a function of the location of the via stub comprises:

determining two outgoing line layers C and D of the via hole, wherein A and B are inner layers, and stubs exist in C and D;

determining a via anti-pad diameter of the adjacent planar layer on side C by simulation S4, and determining a via anti-pad diameter of the adjacent planar layer on side D by simulation S5;

determining the position of a middle plane layer according to the length of the stub at the position C and the length of the stub at the position D, wherein the diameter of a via hole anti-pad of the middle plane layer is the shortest;

determining via antipad diameter of the midplane layer by simulation S6;

according to the S4, S5, and S6, a diameter of the via anti-pad of each planar layer is determined.

6. The method of claim 5, wherein determining the location of the midplane layer based on the stub length at C and the stub length at D comprises:

and determining the position of the middle plane layer according to the ratio of the length of the stub at the position C to the length of the stub at the position D.

7. The method of claim 5, wherein determining the diameter of the via antipad for each planar layer in accordance with the S4, S5, and S6 comprises:

determining the diameter of the via anti-pad of each planar layer according to the S4, S5 and S6 and the distance of the planar layers between C and D.

8. A printed circuit board, PCB, comprising:

a plurality of planar layers, wherein a diameter of the via antipad of each planar layer decreases as a distance between each planar layer and the via stub location increases.

9. A storage medium, in which a computer program is stored, wherein the computer program is arranged to perform the method of any of claims 1 to 7 when executed.

10. An electronic device comprising a memory and a processor, wherein the memory has stored therein a computer program, and wherein the processor is arranged to execute the computer program to perform the method of any of claims 1 to 7.