CN218634401U

CN218634401U - Printed circuit board via hole structure and electronic device

Info

Publication number: CN218634401U
Application number: CN202222862972.4U
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Moore Threads Technology Co Ltd
Current assignee: Moore Threads Technology Co Ltd
Priority date: 2022-10-28
Filing date: 2022-10-28
Publication date: 2023-03-14
Anticipated expiration: 2032-10-28

Abstract

The disclosure provides a printed circuit board via hole structure and an electronic device. Printed circuit board includes a plurality of layers and walks the line, and printed circuit board via hole structure includes: a via extends through the layers of the printed circuit board and includes a first type pad and a second type pad. The first type bonding pad and the trace are located on the same layer and are connected with the trace and the via. The second type of pad is not connected with the trace and is located in a selected layer of the printed circuit board to reduce impedance fluctuation of the via hole, and the selected layer is a part of or all of the rest layers except the layer where the surface layer and the first type of pad are located.

Description

Printed circuit board via hole structure and electronic device

Technical Field

The present disclosure relates to the field of communications technologies, and in particular, to a PCB via structure and a method for optimizing PCB via impedance fluctuation.

Background

Printed Circuit Boards (PCBs) are important components in communication devices, and are the support for electronic components and the provider of electrical connections. As the rate at which PCBs carry electronic signals for communications becomes higher, the impedance of the electronic circuitry on the PCB needs to be optimized to ensure electronic signal quality. The high-speed signal transmission of the multi-layer PCB generally adopts a layer-changing design, and the traces of different layers on the PCB are connected by via holes to form a communication network communicated with each other. The via hole is an important component of the PCB communication network and has the same distributed impedance characteristic as the trace. As the PCB communication rate enters the GHz era, the stability of the impedance at the via becomes increasingly a key technology for ensuring the quality of PCB communication signals.

SUMMERY OF THE UTILITY MODEL

In view of the above, embodiments of the present disclosure provide a PCB via structure and a method, an electronic device, a computing apparatus, a computer program product, and a computer-readable storage medium for optimizing PCB via impedance fluctuation, which can reduce the fluctuation of impedance at a via, reduce the impedance value of the via to near a target value, and improve the signal quality of a printed circuit board.

According to an aspect of the present disclosure, there is provided a printed circuit board via hole structure, the printed circuit board including a plurality of layers and a trace, the printed circuit board via hole structure including: a via extends through the layers of the printed circuit board and includes a first type pad and a second type pad. The first type of bonding pad and the trace are located on the same layer and are connected with the trace and the via hole, the second type of bonding pad is not connected with the trace and is located in a selected layer of the printed circuit board to reduce impedance fluctuation of the via hole, and the selected layer is a part of or all of the rest layers except the layer where the surface layer and the first type of bonding pad are located.

In some embodiments, the via further comprises a surface pad, the via is connected with a device via the surface pad, and the via comprises a first section having a length H and connected with its beginning with the surface pad, the first section spans several of the plurality of layers, and the second type pad is not disposed in the several layers.

In some embodiments, the device includes at least one of a solder ball and a capacitor.

In some embodiments, the length H is about 15 mils.

In some embodiments, the via further comprises a second section having a length H1 between an end of the first section and the first type pad.

In some embodiments, the printed circuit board further comprises at least two anti-pads surrounding and insulated from the via, each of the at least two anti-pads is located in one of the layers other than the layer where the first type pad is located, adjacent two anti-pads of the at least two anti-pads are located within the second section, and a distance between the adjacent two anti-pads is greater than a threshold value.

In some embodiments, the threshold is about 8 mils.

In some embodiments, the via is unconnected to a device, the device including at least one of a solder ball and a capacitor.

In some embodiments, the second type of pad is located in all of the remaining layers of the plurality of layers except for the surface layer and the layer where the first type of pad is located.

In some embodiments, the selected layer is a single layer or a plurality of layers.

According to another aspect of the present disclosure, there is provided an electronic device comprising the printed circuit board via structure described in any of the previous embodiments.

According to yet another aspect of the present disclosure, there is provided a method of optimizing impedance fluctuations of a via of a printed circuit board, the printed circuit board including a plurality of layers and a trace, the via extending through the plurality of layers, the method comprising: obtaining a 3D model of a via hole, wherein the via hole comprises a first type pad which is positioned on the same layer as a routing and is connected with the routing and the via hole; based on the simulation result of the via hole, the following operations are executed: and in response to the impedance value of the via hole being larger than a target value, adding at least one second type pad to the via hole to reduce impedance fluctuation of the via hole, wherein the second type pad is not connected with the trace and is located in a selected layer of the printed circuit board, and the selected layer is part or all of the rest layers except the layer where the surface layer and the first type pad are located.

In some embodiments, the method further comprises: in response to the impedance value of the via being less than a target value, the second type of pad need not be added to the via.

In some embodiments, the via further comprises a surface pad, the via being connected to the device via the surface pad. The step of adding at least one pad of a second type to the via in response to the impedance value of the via being greater than a target value comprises: determining a first section of the via, the first section having a length H and having a beginning connected to the skin pad, the first section spanning several of the plurality of layers; and not providing the second type of pad in the number of layers.

In some embodiments, the printed circuit board further comprises at least two anti-pads surrounding and insulated from the via, each of the at least two anti-pads being located in a respective one of the layers other than the layer in which the first type of pad is located. The step of adding at least one second type pad to the via in response to the impedance value of the via being greater than a target value comprises: in response to the existence of a distance between two adjacent anti-pads of the at least two anti-pads being greater than a threshold value within the second segment, determining a continuous layer of the printed circuit board involved from the layer on which one of the two adjacent anti-pads is located to the layer on which the other of the two adjacent anti-pads is located; and determining the successive layers as potential selected layers.

In some embodiments, the step of adding at least one pad of the second type to the via in response to the impedance value of the via being greater than a target value comprises: selecting a target layer from the potential selected layers as the selected layer based on simulation results of corresponding via impedances of pads of a second type in different layers of the potential selected layers.

In some embodiments, the step of not adding the second type pad to the via in response to the impedance value of the via being less than a target value comprises: determining a first section of the via, the first section having a length H and having a beginning connected to the skin pad, the first section spanning several of the plurality of layers; and responding to the first type of bonding pad being positioned in the range of the first section, and not adding the second type of bonding pad for the via hole.

In some embodiments, the via is not connected to a device, the device includes at least one of a solder ball and a capacitor, and the step of adding at least one second type pad to the via in response to the impedance value of the via being greater than a target value includes: and adding the second type of bonding pad in all the other layers except the layer where the surface layer and the first type of bonding pad are positioned in the plurality of layers of the printed circuit board.

In some embodiments, the step of adding at least one pad of the second type to the via in response to the impedance value of the via being greater than a target value comprises: adding the second type of pad to the via in a selected layer of the printed circuit board, the selected layer being a single layer or a plurality of layers.

According to yet another aspect of the present disclosure, there is provided a computing device comprising: a memory configured to store computer-executable instructions; a processor configured to perform the method as described in any of the previous embodiments when the computer-executable instructions are executed by the processor.

According to yet another aspect of the present disclosure, there is provided a computer program product comprising computer executable instructions that when executed perform a method as described in any of the previous embodiments.

According to yet another aspect of the present disclosure, there is provided a computer-readable storage medium having stored thereon computer-executable instructions that, when executed, perform a method as described in any of the previous embodiments.

The second type of bonding pads are arranged in the PCB via hole structure, the capacitance C of the via hole is increased by using the capacitance between the second type of bonding pads and a power supply/ground plane and the capacitance between the second type of bonding pads, and the impedance Z of the via hole is reduced, so that the via hole impedance fluctuating above a target value is optimized to be close to the target value, the impedance fluctuation of the PCB via hole structure is reduced, and the communication signal quality of the PCB is improved. In addition, the second type of bonding pad can be arranged in a part of layers of the PCB except the layer where the surface layer and the first type of bonding pad are located, and can also be arranged in all layers of the PCB except the layer where the surface layer and the first type of bonding pad are located, so that the PCB can be suitable for wider scenes.

These and other aspects of the disclosure will be apparent from and elucidated with reference to the embodiments described hereinafter.

Drawings

In order to more clearly describe the technical solutions in the embodiments of the present disclosure, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 shows impedance plots of traces and vias of a PCB in the related art;

fig. 2 is a schematic view illustrating a via hole of a PCB in the related art;

FIG. 3 shows a schematic diagram of an anti-pad of a PCB;

FIGS. 4-8 are schematic diagrams illustrating vias of a PCB in the related art;

FIG. 9 is a schematic diagram of a PCB with via and solder ball connections;

FIG. 10 shows a schematic diagram of a PCB via and capacitor connection;

FIG. 11 shows a schematic structural diagram of a via after adding a second type pad according to an embodiment of the present disclosure;

FIG. 12 illustrates a flow chart of a method of optimizing via impedance fluctuations for a PCB in accordance with an embodiment of the present disclosure;

FIG. 13 illustrates parameters of various layers of a PCB according to an embodiment of the present disclosure;

FIG. 14 shows impedance plots of vias obtained using methods provided by embodiments of the present disclosure and methods of the related art;

FIG. 15 shows a flow chart of a method of optimizing via impedance of a PCB according to an embodiment of the present disclosure;

FIG. 16 shows a 3D simulation diagram of vias built using simulation software according to an embodiment of the present disclosure;

FIG. 17 shows an impedance plot simulated for the via of FIG. 16;

FIG. 18 shows another impedance plot simulated for the via in FIG. 16;

FIG. 19 shows a schematic diagram of a via during simulation according to an embodiment of the present disclosure;

FIG. 20 shows a schematic diagram of a via during simulation according to an embodiment of the present disclosure;

FIG. 21 shows a schematic diagram of an anti-pad during simulation according to an embodiment of the present disclosure;

FIG. 22 shows impedance plots of vias using methods provided by embodiments of the present disclosure and methods of the related art;

FIG. 23 shows a block diagram of an electronic device according to an embodiment of the disclosure; and

FIG. 24 is a block diagram of a computing device in accordance with an embodiment of the present disclosure.

Detailed Description

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. It is to be understood that the embodiments described are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure.

As PCB signal rates become higher and higher, it is often necessary to control and optimize the impedance of the physical links on the PCB to improve the signal quality of the PCB. Impedance typically fluctuates at the vias of the PCB, and therefore optimization of impedance at the vias has a critical impact on ensuring the quality of the communication signals of the PCB.

Fig. 1 is a graph of impedance at various positions of a PCB via hole in the related art obtained by a three-dimensional electromagnetic field simulation tool. The abscissa in fig. 1 is the time unit picosecond (ps), and the ordinate in fig. 1 is the impedance unit ohm (Ω). The time t of the abscissa is mapped to the position p of the via according to the following formula:

wherein v refers to the propagation speed of the electromagnetic wave along the via hole, c refers to the speed of light in vacuum, and dk refers to the dielectric constant of the medium at the corresponding position of the via hole when the electromagnetic wave propagates for t/2 time.

The left portion of the curve shown in fig. 1 (corresponding to abscissas 40.00-92.00) represents the impedance of the traces, and the portion of the curve shown in fig. 1 encircled by a box (corresponding to abscissas 92.00-140.00) represents the impedance of the vias. As can be seen from fig. 1, the impedance fluctuation amplitude of the via is larger than that of the trace, which is not favorable for the stability and integrity of the communication signal quality of the PCB.

The impedance formula of the transmission line is as follows:

wherein, R refers to the resistance of the transmission line of unit length, G refers to the admittance of the transmission line of unit length, L refers to the inductance of the transmission line of unit length, C refers to the capacitance of the transmission line of unit length, Z refers to the impedance of the transmission line, j refers to the imaginary unit, and w refers to the angular frequency.

In most cases, the impedance of the via of the PCB is below a set target value. In order to increase the impedance of the via to approach the target value, the related art generally adopts a scheme of removing all the non-functional pads from the via 10, leaving only the superficial layer pad 11 and the outgoing line layer pad 12, as shown in fig. 2. The wire layer pads 12 are connected to traces 13 and the surface layer pads 11 are connected to devices 15 (e.g., solder balls). Non-functional pads refer to those pads on the via 10 that are not in electrical connection with the trace 13. Removing all non-functional pads allows the capacitance C to be reduced, as can be seen from the impedance equation above, when the inductance L is constant, the impedance Z decreases with increasing capacitance C and increases with decreasing capacitance C. Thus, by removing all non-functional pads, the capacitance C of the via 10 may be reduced, and thus the impedance Z of the via 10 may be increased.

In other cases, the impedance of the via of the PCB is higher than a set target value. In order to reduce the impedance of the via to approach a target value, the related art generally adopts a scheme of reducing the size of an anti-pad of the PCB to increase the capacitance C, thereby reducing the impedance Z of the via. During PCB processing, the copper layer of other networks around the via needs to be spaced from the via and the pad (including the surface layer pad 11 and the wire-out layer pad 12) to form a cavity around the via, which is called an anti-pad. Due to the limitation of the processing precision of the PCB, the anti-bonding pad can not be infinitely reduced, and the edge of the anti-bonding pad and the edge of the through hole have to be separated by a certain distance, wherein the distance is about 8mil at minimum. Fig. 3 shows a schematic plan view of the anti-pad 16. As shown in fig. 3, the anti-pad 16 may be a circular void. In such a case, reducing the diameter D of the anti-pad 16 may increase the capacitance C of the via, thereby reducing the impedance Z of the via, such that the via impedance above a target value may approach the target value.

The method of reducing the via impedance Z by reducing the size of the anti-pad is effective in most cases, but the size of the anti-pad can be reduced only to a limited extent due to processability problems, and cannot be reduced without limitation, so that the optimization of the impedance by the reduction of the size of the anti-pad is also limited.

Examples of scenarios where the inductance of the via part (or whole) is relatively strong or the capacitance is relatively weak include, but are not limited to, the following:

I. as shown in fig. 4, in the multilayer structure of the PCB, the dielectric thickness T between a certain pair or pairs of adjacent layers is much larger than that between other adjacent layers, and fig. 4 shows, as an example, that the dielectric thickness T between a pair of adjacent layers is much larger than that between other adjacent layers. This causes the average distributed capacitance of the via at the section with the thicker dielectric thickness T to be much smaller than the average distributed capacitance of the other sections of the via, causing the impedance of the via at the section with the thicker dielectric thickness T to fluctuate above a target value. The reason for such a laminated structure with non-uniform media thickness is generally as follows: (a) Two adjacent layers of the PCB are provided with overlapped wiring in space, and the thickness of a medium between the two adjacent layers needs to be increased in order to reduce crosstalk between the two adjacent layers of the wiring; (b) PCBs generally have thickness requirements, and sometimes to meet the thickness requirements of PCBs, it is necessary to increase the thickness of the dielectric between adjacent layers.

As shown in fig. 5, although the dielectric thickness between some adjacent two layers does not appear to be large on the laminated structure of the PCB, copper is not laid around the via hole in the successive two or more layers of the PCB. Due to layout design considerations, the two layers indicated by 1 and 2 in fig. 5 are not copper-plated around the via, which results in a smaller distributed capacitance in the part of the via (i.e., the area defined by the anti-pad located above the number 1 and the anti-pad located below the number 2 in fig. 5), thereby causing the impedance of the via in this part to fluctuate above a target value.

Vias with an aperture D2 smaller than the conventional aperture D1 are often used in certain routing dense areas of the PCB, as illustrated in fig. 6, the aperture D2 of the vias being, for example, less than or equal to 8 mils. The smaller the aperture of the via hole is, the larger the distributed inductance per unit length of the via hole is, which results in a large overall impedance of the via hole, and thus causes the via hole impedance to fluctuate above a target value.

Any of the three scenarios described above may cause the impedance of the via to fluctuate above the target value. In order to reduce the impedance of the via, the related art can only increase the distributed capacitance C of the via by reducing the size of the anti-pad of the corresponding layer, thereby reducing the impedance of the via to some extent. However, the size of the anti-pad cannot be reduced infinitely due to the limitation of the manufacturing capability of the PCB, so that the fluctuation of the via resistance higher than a target value cannot be effectively reduced by reducing the size of each layer of the anti-pad.

The related art has attempted to improve the uniformity of the distributed capacitance per unit length of the via by adding non-functional pads to all layers other than the surface layer and the outlet layer without distinction, as shown in fig. 7. For the via hole 20, except for the layer L1 where the surface layer pad 21 is located and the layers L2 and L4 where the outlet layer pad 22 is located, the other layers L3, L5 and L6 of the PCB are provided with non-functional pads 24. For the purpose of achieving consistency of distributed capacitance per unit length, the scheme requires that the distance between any two adjacent laminates in L1 to L6 needs to be kept consistent, application scenarios are very limited, and if the via hole is further connected with other devices, or the via hole has a stub shown in fig. 9 (the stub refers to an unused part on the via hole), or the PCB has a non-uniform laminated structure, it is difficult to achieve corresponding effects.

In practice, vias are often required to connect to devices, such as BGA (Ball Grid Array) solder balls or capacitors. Fig. 9 shows a schematic diagram of the connection of the BGA ball 15 to the via and fig. 10 shows a schematic diagram of the connection of the capacitor 17 to the via. In engineering practice, the device connected to the via, the wire connecting the device and the via, and the via need to be optimized for overall impedance as a whole. PCBs with non-uniform laminate structures are often common and necessary in engineering practice.

The embodiment of the disclosure provides a PCB via hole structure and a method for optimizing PCB via hole impedance fluctuation, which can reduce the via hole impedance fluctuating above a target value to be near the target value, thereby reducing the fluctuation of the impedance at the via hole, improving the signal quality of the PCB, and being applicable to various common multilayer PCBs in engineering.

Fig. 11 shows a schematic structural diagram of a PCB via structure 400 according to an embodiment of the present disclosure. As shown in fig. 11, the PCB includes a plurality of layers and a trace 103, and the PCB via structure 400 includes vias that extend through the plurality of layers and include a first type pad 102 and a second type pad 105, three second type pads 105 being shown. The first type pads 102 are located at the same layer as the traces 103 and connect the traces 103 with the vias. The second type pad 105 is not connected to the trace 103 and is located in a selected layer of the PCB to reduce impedance fluctuation of the via hole, where the selected layer is a part or all of the rest layers of the multiple layers of the PCB except the layer where the surface layer and the first type pad 102 are located, or the number of the selected layers is less than or equal to the number of the rest layers. The selected layer may be a single layer or a plurality of layers. When the selected layer is a single layer, it means that the second type pads 105 are located in one of the layers of the PCB other than the surface layer and the layer where the first type pads 102 are located. When the selected layer is a plurality of layers, it means that the second type pads 105 are located in any combination of the remaining layers of the plurality of layers of the PCB, except the surface layer and the layer where the first type pads 102 are located.

It should be noted that the term "first type pad" refers to a pad connected to the trace 103, that is, a common pad, and the first type pad can enhance the mechanical connection performance between the PCB trace and the via, which is beneficial for the machining of the PCB. The term "second type pads" refers to non-functional pads, i.e., those pads that are not in electrical connection with trace 103, and the terms "second type pads" and "non-functional pads" may be used interchangeably herein.

The via also includes a blanket pad 101. In some embodiments, the via is connected to device 104 via a blanket pad 101 and a wire. In an alternative embodiment, the via is not connected to the device 104, in which case the second type pad 105 is located in all of the remaining layers of the PCB except the surface layer and the layer in which the first type pad 102 is located. The device 104 may be, for example, at least one of a BGA solder ball and a capacitor.

Referring to fig. 20, in some embodiments, the via 200 includes a first section Q1, the first section Q1 having a length H and connected at its beginning to the skin pad 101, the first section Q1 spanning several of the layers, e.g., spanning layers 1-3 of the PCB, and the second type pad 105 not being disposed in the several layers. In one example, the length H is about 15 mils.

As shown in fig. 20, the first-type pad 102 is located on a side of the first section Q1 away from the surface layer pad 101, and the via 200 further includes a second section Q2 with a length H1 located between an end of the first section Q1 and the first-type pad 102. In some embodiments, the PCB further comprises at least two anti-pads surrounding the via 200 and insulated from the via 200, each anti-pad being located in one of the other layers of the plurality of layers of the PCB than the first type of pad 102, adjacent two of the at least two anti-pads being located within the second section Q2, and the distance H2 between the adjacent two anti-pads being greater than a threshold value. In one example, the threshold is about 8 mils. In an alternative embodiment, the PCB may not include an anti-pad.

By providing the second type of pad 105 in the PCB via structure 400, the capacitance C of the via is increased by the capacitance between the second type of pad 105 and the power/ground plane and the capacitance between each second type of pad 105, and the impedance Z of the via is reduced, thereby optimizing the via impedance that fluctuates above a target value to near the target value, reducing the impedance fluctuation of the PCB via structure 400, and improving the communication signal quality of the PCB. In addition, the second type bonding pad 105 may be disposed in a part of the rest layers of the PCB except the layer where the surface layer and the first type bonding pad 102 are located, or may be disposed in all the rest layers of the PCB except the layer where the surface layer and the first type bonding pad 102 are located, so that the PCB may be applicable to a wider range of scenes.

In some embodiments, referring to fig. 11, the PCB has 8 layers, respectively, 1 st layer L1 to 8 th layer L8, and the first type pads 102 are located at 7 th layer of the PCB and the second type pads 105 are located at 4 th layer, 5 th layer, and 6 th layer of the PCB, respectively. When the PCB has 8 layers and the second type bonding pad 105 is added on the 4 th, 5 th and 6 th layers of the PCB, the impedance fluctuation of the via hole can be reduced to the minimum, and the communication signal quality of the PCB is further improved.

Fig. 12 illustrates a method 100 of optimizing via impedance fluctuations for a PCB according to an embodiment of the present disclosure, the PCB provided by an embodiment of the present disclosure including a plurality of layers through which vias extend, the method 100 including the steps of: 110: and acquiring a 3D model of a via hole, wherein the via hole comprises a first type pad which is positioned on the same layer as the routing wire and is connected with the routing wire and the via hole.

It should be noted that the 3D model of the via hole is established according to the laminated structure of the actual PCB, and the 3D model of the via hole is different correspondingly when the laminated structure of the PCB is different.

120: based on the simulation result of the via hole, the following steps are performed.

130: judging whether the impedance value of the via hole is larger than a target value, if so, turning to step 140; if not, proceed to step 150.

140: and adding at least one second type bonding pad for the via hole, wherein the second type bonding pad is not connected with the routing wire and is positioned in a selected layer of the PCB, the selected layer is a part of or all the layers of the plurality of layers of the PCB except the layer where the surface layer and the first type bonding pad are positioned, or the number of the selected layer is less than or equal to that of the rest layers, and the second type bonding pad is configured to reduce impedance fluctuation of the via hole.

150: and in response to the impedance value of the via being smaller than the target value, the size of the anti-pad is increased without adding a second type pad for the via.

In some embodiments, the via is not connected to the device, and the device may be at least one of a solder ball and a capacitor. In this case, the second type pads are added to all of the remaining layers of the plurality of layers of the printed circuit board except for the surface layer and the layer where the first type pads are located.

In some embodiments, one situation in which a via has an impedance value less than a target value without adding a pad of the second type to the via occurs is, with reference to fig. 20, a via having a first section Q1, the first section Q1 having a length H and being connected at its beginning to a surface pad 101, the first section Q1 spanning several of the layers of the PCB. However, unlike fig. 20, the first type pads are located within the first section Q1, i.e. the first type pads are located in a film layer of the PCB closer to the surface layer pads 101, e.g. the first type pads are located in layer 2 or layer 3 of the PCB. In this case, no pads of the second type need to be provided for the vias.

In short, in the method 100, the second type pads may be added to a single layer of the remaining layers of the plurality of layers of the PCB except for the layer where the top layer and the first type pads are located, or the second type pads may be added to a plurality of layers of the remaining layers of the plurality of layers of the PCB except for the layer where the top layer and the first type pads are located, or the second type pads may be added to all layers of the remaining layers of the plurality of layers of the PCB except for the layer where the top layer and the first type pads are located, or the second type pads may not be added to the PCB.

In the method 100, the second type of pad is disposed in a selected layer of the PCB, and the selected layer is a portion or all of the remaining layers of the plurality of layers of the PCB except the surface layer and the layer in which the first type of pad is disposed. In short, in the method 100, the second type pads may be provided in part of the layers of the PCB except the layer where the surface layer and the first type pads are located, or may be provided in all the layers of the PCB except the layer where the surface layer and the first type pads are located, that is, the method 100 covers the arrangement manner of the non-functional pads 24 in fig. 7, and may be applied to more scenarios. The capacitance C of the via is increased by using the capacitance between the second type pads and the power/ground plane and the capacitance between the second type pads, so that the impedance Z of the via is reduced, thereby optimizing the impedance of the via, which fluctuates above a target value, to be near the target value, and reducing the impedance fluctuation of the via. In addition, as described previously, the method of reducing the via impedance Z by reducing the size of the anti-pad provided by the related art is not applicable to the scenarios shown in fig. 4 to 6, and the method of fig. 7 provided by the related art is not applicable to the scenarios of fig. 9 to 10. In contrast, the method 100 provided by the embodiments of the present disclosure is applicable to various scenarios, including but not limited to the scenarios shown in fig. 4-6 and 9-10.

To further prove the beneficial effects of the method 100, the inventors of the present application take a PCB with an 8-layer stacked structure as an example, and compare the via impedance obtained by the method of the related art and the via impedance obtained by the method 100 provided by the embodiment of the present disclosure, fig. 13 shows parameters of various layers of the example PCB, and fig. 14 shows an impedance comparison graph. In this example PCB, the vias are connected to BGA balls, and the trace layer pads are on layer 7. The dielectric thickness and copper thickness in fig. 13 are in mils, and it can be seen from fig. 13 that the dielectric thickness between adjacent layers is not uniform, which is a very common design in engineering practice.

In fig. 14, the abscissa is the time unit ps and the ordinate is the impedance unit Ω. The curve denoted by the arabic numeral "1" represents the impedance curve of a via obtained using the method of fig. 2 (i.e., removing all non-functional pads), the curve denoted by the arabic numeral "2" represents the impedance curve of a via obtained using the method of fig. 7 (i.e., retaining all non-functional pads), and the curve denoted by the arabic numeral "3" represents the impedance curve of a via obtained by disposing non-functional pads only in a partial layer. As can be seen from fig. 14, the curve denoted by the arabic numeral "3", that is, the non-functional pads are provided in some layers of the remaining layers of the PCB except for the surface layer and the layer where the first type pads are located, and the impedance fluctuation of the via hole is most remarkably improved.

The second type pad is provided to improve the fluctuation of the impedance of the via hole, thereby reducing the impedance fluctuating above the target value to the vicinity of the target value. The specific number of the second type pads is provided, which is related to the number of layers of the PCB, the outgoing line from the fourth layer, the effective length of the via hole, the number of power/ground planes, and so on, and cannot be summarized. The present application further provides a universal method 300 based on the method 100, which can determine which layers need to be provided with the second type of bonding pads according to different scenarios, so as to achieve the optimal improvement on the via impedance fluctuation.

Fig. 15 schematically shows a flow chart of a method 300, the steps of the method 300 being as follows: 210: a 3D model of the via is obtained, and a schematic diagram of the 3D model is shown in fig. 16. As mentioned above, the 3D model of the via hole is established according to the actual laminated structure of the PCB, which is different, and the 3D model of the via hole is correspondingly different.

A 3D model of the via may be built in an electromagnetic field simulation tool such as High Frequency Structure Simulation (HFSS). In one embodiment, the PCB may be a 1.57mm thick circuit board having an 8-layer stack structure with the re-layer vias re-layered from top to 7 th layers of the PCB, and the BGA solder balls and vias connected.

220: all non-functional pads are removed in the model. It should be noted that this step can be performed in combination with step 210, i.e., all non-functional pads are removed when the 3D model of the via is created, or can be performed separately after step 210. Then, simulating the impedance of the via hole, if the impedance of the via hole fluctuates above the target value, adding a second type of pad, and entering step 230; if the impedance of the via hole fluctuates below the target value, the second type of bonding pad does not need to be added, and only the size of each layer of anti-bonding pad needs to be adjusted appropriately to increase the impedance of the via hole. As shown in fig. 17, the curve circled by the box represents the impedance fluctuation curve of the via, and it can be seen that the maximum value of the impedance fluctuation of the via exceeds the target impedance value (45 Ω) by about 7 Ω, which obviously requires the addition of the second type pad. In contrast, as shown in fig. 18, the curves circled in the boxes represent the impedance fluctuation curves of the vias, and it can be seen that the impedances of the vias all fluctuate substantially below the target impedance value (45 Ω), which eliminates the need to add pads of the second type. It should be noted that, the phrase "if the impedance of the via fluctuates above the target value, the second type of pad needs to be added; if the impedance of the via hole fluctuates below a target value, the second type of pad does not need to be added, and in practice, when the impedance of the via hole fluctuates within +/-2 Ω range of the target impedance value, whether the influence of the second type of pad on the impedance of the via hole is added or not is not very obvious, so that when the target impedance value is less than the impedance value of the via hole < the target impedance value +2 Ω, the second type of pad can be added or not; similarly, when the target impedance value-2 Ω < the impedance value of the via < the target impedance value, the second type of pad may not be added, and may also be added. However, when the impedance of the vias fluctuates over a greater range (e.g., +/-5 Ω) above and below the target impedance value, then the impedance of the vias fluctuates above the target value and adds to the second type of pad, and the impedance of the vias fluctuates below the target value and does not add to the second type of pad, as previously described.

Step 140 "adding at least one second type pad to the via in response to the impedance value of the via being greater than the target value" in the method 100 may further include the following steps 230-280.

As shown in fig. 19, a via 200 provided by the embodiment of the present disclosure includes a surface pad 101, and the via 200 is connected to the device 104 via the surface pad 101 and a wire. In one example, the devices 104 are BGA solder balls.

230: referring to fig. 19, a first section Q1 of the via 200 is determined, the first section Q1 having a length H and connected at its beginning to the skin pad 101, the first section Q1 spanning several of the layers of the PCB.

240: the second type of pads are not provided in the several layers mentioned above.

Referring to fig. 19, the device 104 connected to the via 200 and the first section Q1 of the via 200 form an ensemble whose average distributed inductance and average distributed capacitance determine the impedance of the area. While the size of the device 104 connected to the via 200 is typically larger than the size of the via 200, the distributed inductance of the device 104 is relatively smaller, which may cause the impedance of the whole formed by the device 104 and the first section Q1 of the via 200 to drop below a target value. If a second type of pad is added to the first section Q1, this may result in a further decrease in impedance in this area, which is undesirable. Since the first section Q1 having the length H spans several layers of the PCB, the second type pad cannot be provided in the several layers. In some embodiments, the number of layers may include layers 1-3 of the PCB. In some embodiments, the length H is about 15 mils, i.e., within 15 mils from the blanket pad 101 of the via 200 in fig. 19, and no second type pad is provided. Of course, this constraint is not present if the via 200 is not connected to other devices.

Fig. 20 shows a more detailed structure of the via 200, and as shown, the via 200 includes the aforementioned first type pad 102, and the first type pad 102 is connected to the trace 103. The first type pads 102 are located on a side of the first section Q1 away from the skin pad 101. The via 200 further includes a second section Q2 having a length H1 between an end of the first section Q1 and the first type pad 102, and the PCB further includes at least two anti-pads surrounding the via 200 and insulated from the via 200, each anti-pad being located in a respective one of the layers of the PCB other than the layer in which the first type pad 102 is located, fig. 21 showing a schematic plan view of the anti-pads. Of course, in alternative embodiments, the PCB may not include anti-pads.

250: referring to fig. 20, it is determined whether a distance between two adjacent anti-pads is greater than a threshold value within the second section Q2 of the via 200, and if so, go to step 260; if not, go to step 290. In some embodiments, the threshold may be, for example, 8 mils.

260: determining successive layers of the PCB involved from the layer in which one of the two adjacent anti-pads is located to the layer in which the other of the two adjacent anti-pads is located.

It should be noted that the term "continuous layer of PCB" in step 260 means that, assuming that a layer on which one of two adjacent anti-pads is located is an mth layer of PCB and a layer on which the other of two adjacent anti-pads is located is an nth layer of PCB, and n > m, the continuous layer of PCB includes the mth layer, the (m + 1) th layer, the (m + 2) th layer 8230, the (n-2) th layer, the (n-1) th layer, and the nth layer. For example, if one of the two adjacent anti-bonding pads is the 4 th layer of the PCB and the other of the two adjacent anti-bonding pads is the 6 th layer of the PCB, the continuous layer of the PCB refers to the 4 th to 6 th layers of the PCB.

270: the successive layers are identified as potential selected layers.

As previously noted, the second type of pad is provided in a selected layer of the PCB. By "potentially selected layers" is meant that the successive layers determined in step 260 are likely to be selected layers, i.e., it is possible to provide the second type of pads in all of the successive layers, or it is possible to provide the second type of pads only in some of the successive layers, and by this step, the initial selection and determination of the selected layers is achieved. The particular layer(s) of the successive layers that are the final selected layer is determined further by relying on the following steps.

Fig. 20 shows that the via 200 penetrates from the 1 st layer L1 to the 8 th layer L8, i.e. the PCB comprises 8 layers, and the first type pad 102 is located at the 7 th layer L7. As shown in fig. 20, the distance between the anti-pad of the 4 th layer and the anti-pad of the 6 th layer is H2, and the anti-pad of the 5 th layer is not provided, so that the anti-pad of the 4 th layer and the anti-pad of the 6 th layer are the "two adjacent anti-pads" as described above. In one embodiment, H2 equals 29.92 mils, much greater than the threshold of 8 mils. In this case, layers 4 through 6 of the PCB are potentially selected layers, and thus, layers 4, 5, and 6 may all have the potential to add pads of the second type.

280: and selecting the target layer from the potential selected layers as the selected layer based on simulation results of corresponding via impedances of the second type pads in different layers of the potential selected layers.

And if the first type of bonding pad is positioned on the X-th layer of the PCB, adding a second type of bonding pad from the (X-1) -th layer upwards, respectively carrying out impedance simulation on the via hole according to each condition of the added second type of bonding pad, and determining the optimal combination of the adding positions of the second type of bonding pad according to the simulation result.

In one example, still taking an 8-layer PCB as an example, for the potential selected layer identified in step 270, since the first type of pad is located at the 7 th layer, the second type of pad is added layer by layer from the 6 th layer to the 4 th layer for via impedance simulation, and the optimal combination of the second type of pad is determined according to the simulation result. Fig. 22 shows a simulation graph of via impedance for three cases. In fig. 22, a curve denoted by a letter a represents a graph of the impedance of a via after a pad of the second type is added only to the 6 th layer, a curve denoted by a letter B represents a graph of the impedance of a via after pads of the second type are added only to the 5 th layer and the 6 th layer, and a curve denoted by a letter C represents a graph of the impedance of a via after pads of the second type are added to all of the 4 th, 5 th, and 6 th layers. From the simulation results of fig. 22, it can be seen that by adding the second type pad to each of the 4 th, 5 th and 6 th layers, the impedance fluctuation of the via is minimal.

290: and (6) ending.

Through the method 300, the impedance of the via hole fluctuating above the target value can be reduced to be close to the target value, the impedance fluctuation of the via hole is reduced, the communication signal quality of the PCB is improved, and the optimal impedance optimization effect can be obtained by determining which layer or layers of the PCB are added with the second type of bonding pads, so that the impedance fluctuation of the via hole is minimum.

It should be noted that although only a PCB having an 8-layer stacked structure is illustrated herein, the PCB via structure 400 and the

methods

100 and 300 provided by the embodiments of the present disclosure may be applied to various stacked PCB via structures. In addition, although it is mentioned herein that the first type pads may be located in the 7 th layer of an 8-layer PCB, this is only one example and the first type pads may be located in any layer of the PCB. In addition, the

methods

100 and 300 provided by the embodiments of the present disclosure are also applicable to the layer-change via of the differential line.

Fig. 23 schematically illustrates an example block diagram of an electronic device 500, the electronic device 500 including the PCB via structure 400 described in any of the previous embodiments, in accordance with some embodiments of the present disclosure.

The electronic device 500 may have substantially the same technical effects as the PCB via structure 400 described in the previous embodiment, and for the sake of brevity, the technical effects of the electronic device 500 will not be described repeatedly herein.

Fig. 24 schematically illustrates an example block diagram of a computing device 700, in accordance with some embodiments of this disclosure.

As shown in fig. 24, computing device 700 includes a processing system 701, one or more computer-readable media 702, and one or more input/output (I/O) interfaces 703 communicatively coupled to each other. Although not shown, the computing device 700 may also include a system bus or other data and command transfer system that couples the various components to one another. A system bus can include any one or combination of different bus structures, such as a memory bus or memory controller, a peripheral bus, a universal serial bus, and/or a processor or local bus that utilizes any of a variety of bus architectures, or that also includes data lines, such as control and data lines.

Processing system 701 represents functionality to perform one or more operations using hardware. Thus, the processing system 701 is illustrated as including hardware elements 704 that may be configured as processors, functional blocks, and so forth. This may include implementing an application specific integrated circuit or other logic device formed using one or more semiconductors in hardware. Hardware element 704 is not limited by the materials from which it is formed or the processing mechanisms employed therein. For example, a processor may be comprised of semiconductor(s) and/or transistors (e.g., electronic Integrated Circuits (ICs)). In such a context, processor-executable instructions may be electronically-executable instructions.

The computer-readable medium 702 is illustrated as including memory/storage 705. Memory/storage 705 represents memory/storage associated with one or more computer-readable media. Memory/storage 705 may include volatile storage media (such as Random Access Memory (RAM)) and/or nonvolatile storage media (such as Read Only Memory (ROM), flash memory, optical disks, magnetic disks, and so forth). The memory/storage 705 may include fixed media (e.g., RAM, ROM, a fixed hard drive, etc.) as well as removable media (e.g., flash memory, a removable hard drive, an optical disk, and so forth). Illustratively, the memory/storage 705 may be used to store computer-executable instructions that, when executed by a processor, perform the method of optimizing via impedance of a printed circuit board described in the previous embodiments. The computer-readable medium 702 may be configured in various other ways, which are further described below.

One or more input/output interfaces 703 represent functionality that allows a user to enter commands and information to computing device 700, and also allows information to be presented to the user and/or sent to other components or devices using a variety of input/output devices. Examples of input devices include a keyboard, a cursor control device (e.g., a mouse), a microphone (e.g., for voice input), a scanner, touch functionality (e.g., capacitive or other sensors configured to detect physical touch), a camera (e.g., motion that does not involve touch may be detected as gestures using visible or invisible wavelengths such as infrared frequencies), a network card, a receiver, and so forth. Examples of output devices include a display device (e.g., a display or projector), speakers, a printer, a haptic response device, a network card, a transmitter, and so forth.

Various techniques may be described herein in the general context of software, hardware, components, or program modules. Generally, these modules include routines, programs, objects, elements, components, data structures, etc. that perform particular tasks or implement particular abstract data types. The terms "module," "functionality," and the like, as used herein generally represent software, firmware, hardware, or a combination thereof. The features of the techniques described herein are platform-independent, meaning that the techniques may be implemented on a variety of computing platforms having a variety of processors.

An implementation of the described modules and techniques may be stored on or transmitted across some form of computer readable media. Computer readable media can include a variety of media that can be accessed by computing device 700. By way of example, and not limitation, computer-readable media may comprise "computer-readable storage media" and "computer-readable signal media".

"computer-readable storage medium" refers to a medium and/or device, and/or a tangible storage apparatus, capable of persistently storing information, as opposed to mere signal transmission, carrier wave, or signal per se. Accordingly, computer-readable storage media refers to non-signal bearing media. Computer-readable storage media include hardware such as volatile and nonvolatile, removable and non-removable media and/or storage devices implemented in methods or technology suitable for storage of information such as computer-executable instructions, data structures, program modules, logic elements/circuits or other data. Examples of computer readable storage media may include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital Versatile Disks (DVD) or other optical storage, hard disks, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or other storage, tangible media, or an article of manufacture suitable for storing the desired information and which may be accessed by a computer.

"computer-readable signal medium" refers to a signal-bearing medium configured to transmit instructions to the hardware of computing device 700, such as via a network. Signal media may typically embody computer-executable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave, data signal, or other transport mechanism. Signal media also includes any information delivery media. By way of example, and not limitation, signal media includes wired media such as a wired network or direct-wired connection, and wireless media such as acoustic, RF, infrared and other wireless media.

As previously described, hardware element 704 and computer-readable medium 702 represent instructions, modules, programmable device logic, and/or fixed device logic implemented in hardware form that may be used in some embodiments to implement at least some aspects of the techniques described herein. The hardware elements may include integrated circuits or systems-on-chips, application Specific Integrated Circuits (ASICs), field Programmable Gate Arrays (FPGAs), complex Programmable Logic Devices (CPLDs), and other implementations in silicon or components of other hardware devices. In this context, a hardware element may serve as a processing device to perform program tasks defined by instructions, modules, and/or logic embodied by the hardware element, as well as a hardware device to store instructions for execution, such as the computer-readable storage medium described previously.

Combinations of the foregoing may also be used to implement the various techniques and modules described herein. Thus, software, hardware, or program modules and other program modules may be implemented as one or more instructions and/or logic embodied on some form of computer-readable storage medium and/or by one or more hardware elements 704. The computing device 700 may be configured to implement particular instructions and/or functions corresponding to software and/or hardware modules. Thus, implementing a module as a module executable by computing device 700 as software may be implemented at least partially in hardware, for example, using computer-readable storage media of a processing system and/or hardware elements 704. The instructions and/or functions may be executed/operable by, for example, one or more computing devices 700 and/or processing systems 701 to implement the techniques, modules, and examples described herein.

The techniques described herein may be supported by these various configurations of the computing device 700 and are not limited to the specific examples of the techniques described herein.

It should be understood that embodiments of the disclosure have been described with reference to different functional units for clarity. However, it will be apparent that the functionality of each functional unit may be implemented in a single unit, in a plurality of units or as part of other functional units without departing from the disclosure. For example, functionality illustrated to be performed by a single unit may be performed by a plurality of different units. Thus, references to specific functional units are only to be seen as references to suitable units for providing the described functionality rather than indicative of a strict logical or physical structure or organization. Thus, the present disclosure may be implemented in a single unit or may be physically and functionally distributed between different units and circuits.

Embodiments of the present disclosure provide a computer-readable storage medium having stored thereon computer-executable instructions that, when executed, implement the above-described method of optimizing via impedance fluctuations for a printed circuit board.

Embodiments of the present disclosure provide a computer program product or computer program comprising computer-executable instructions stored in a computer-readable storage medium. The processor of the computing device reads the computer-executable instructions from the computer-readable storage medium, and the processor executes the computer-executable instructions to cause the computing device to perform the method for optimizing the via impedance fluctuation of the printed circuit board provided in the various embodiments described above.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed above could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. In the description herein, references to the description of "one embodiment," "another embodiment," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Moreover, various embodiments or examples and features of various embodiments or examples described in this specification can be combined and combined by one skilled in the art without being mutually inconsistent.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present specification and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

The above description is only a specific embodiment of the present disclosure, but the scope of the present disclosure is not limited thereto. Any person skilled in the art can easily conceive of changes or substitutions within the technical scope of the disclosure, and all the changes or substitutions are covered by the protection scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. The utility model provides a printed circuit board via hole structure, printed circuit board includes a plurality of layers and walks the line, its characterized in that, printed circuit board via hole structure includes:

a via extending through the plurality of layers and including a first type pad and a second type pad;

wherein the first type pads and the traces are located on the same layer and connect the traces and the vias, and

the second type of bonding pad is not connected with the trace and is positioned in a selected layer of the printed circuit board to reduce impedance fluctuation of the via hole, and the selected layer is a part of or all of the layers except the layer where the surface layer and the first type of bonding pad are positioned.

2. The printed circuit board via structure of claim 1,

the via further includes a surface layer pad, the via is connected with a device via the surface layer pad, and

the via includes a first segment having a length H and a beginning connected with the skin pad, the first segment spanning several of the plurality of layers and the second type pad not disposed in the several layers.

3. The printed circuit board via structure of claim 2, wherein the device comprises at least one of a solder ball and a capacitor.

4. The printed circuit board via structure of claim 2, wherein the length H is approximately 15 mils.

5. The printed circuit board via structure of claim 2, wherein the via further comprises a second section having a length H1 between the end of the first section and the first type of pad.

6. The printed circuit board via structure of claim 5, further comprising at least two anti-pads surrounding and insulated from the via, each of the at least two anti-pads being located in one of the other layers of the plurality of layers except the layer in which the first type of pad is located, wherein there are two adjacent anti-pads of the at least two anti-pads that are located within the second section, and wherein a distance between the two adjacent anti-pads is greater than a threshold.

7. The printed circuit board via structure of claim 6, wherein the threshold is about 8 mils.

8. The printed circuit board via structure of claim 1, wherein the via is unconnected to a device, the device comprising at least one of a solder ball and a capacitor.

9. The printed circuit board via structure of claim 8, wherein the second type of pad is located in all of the remaining layers of the plurality of layers except for the surface layer and the layer in which the first type of pad is located.

10. The printed circuit board via structure of any of claims 1-9, wherein the selected layer is a single layer or a plurality of layers.

11. An electronic device, characterized in that it comprises a printed circuit board via structure according to any of claims 1-10.