CN110994996A - Asynchronous step-down DCDC chip and bootstrap circuit based on asynchronous step-down DCDC chip - Google Patents

Asynchronous step-down DCDC chip and bootstrap circuit based on asynchronous step-down DCDC chip Download PDF

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CN110994996A
CN110994996A CN201911413532.7A CN201911413532A CN110994996A CN 110994996 A CN110994996 A CN 110994996A CN 201911413532 A CN201911413532 A CN 201911413532A CN 110994996 A CN110994996 A CN 110994996A
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voltage
boot
output end
dcdc chip
asynchronous
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CN110994996B (en
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冯翰雪
皮文兵
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3Peak Inc
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3Peak Inc
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The invention discloses an asynchronous step-down DCDC chip and a bootstrap circuit based on the sameBOOTWherein: a plurality of first MOS tubes are arranged between the input end and the first output end; a BOOT reference voltage unit is arranged between the grid electrode of the first MOS tube and the second output end; and a second MOS tube is arranged between the second output end and the reference potential and is driven by the logic control unit. The bootstrap circuit includes: an asynchronous buck DCDC chip; a bootstrap capacitor; an inductance; output capacitance and load resistance. The invention solves the problem of bootstrap capacitor C under the condition of light load by connecting the lower end of the BOOT reference voltage unit to the second output end SWBOOTThe problem of incapability of charging.

Description

Asynchronous step-down DCDC chip and bootstrap circuit based on asynchronous step-down DCDC chip
Technical Field
The invention belongs to the technical field of power management chips, and particularly relates to an asynchronous step-down DCDC chip and a bootstrap circuit based on the asynchronous step-down DCDC chip.
Background
Referring to fig. 1, a bootstrap circuit based on an asynchronous buck DCDC chip in the prior art is shown, wherein a specific circuit of a BOOT reference voltage unit is shown in fig. 2, the asynchronous buck DCDC chip needs to use a schottky diode D0 to form a freewheeling path of an inductive current to complete an input voltage VINTo an output voltage VOUTThe conversion of (1).
An NMOS transistor is generally used as a high-side power transistor of an asynchronous step-down DCDC chip, and in order to drive the high-side NMOS transistor, a BOOT drive circuit needs to be designed inside the chip, and the chip is matched with an external bootstrap capacitor CBOOTTo generate the power source BOOT of the high-side NMOS transistor driving circuit. Meanwhile, in order to ensure that the BOOT voltage is sufficient for the high-side NMOS transistor driver circuit to operate normally, a UVLO (under voltage latch) circuit is usually used to monitor the voltage difference V between the BOOT and the SWBOOTVoltage difference VBOOTLarge enough to allow the high side NMOS transistor to turn on.
Referring to fig. 3a to 3c, which are waveform diagrams illustrating the operation of the bootstrap circuit in the prior art, it can be found that the bootstrap circuit in the prior art has the following disadvantages:
as shown in FIG. 3a, the bootstrap circuit requires a low SW voltage and can only bootstrap the capacitor C during the OFF periodBOOTCharging;
as shown in FIG. 3b, under the light-load DCM operation condition, the OFF time is very short, and the voltage in the IDEL period SW is higher, so that the bootstrap capacitor C cannot be effectively usedBOOTCharging;
as shown in fig. 3c, the input voltage VINClose to the output voltage VOUTThe OFF time is short under the operating condition of a large duty ratio, no matter in a CCM Mode (continuous conduction Mode) or a DCM Mode (Discontinuous conduction Mode), and the bootstrap capacitor C is shortBOOTAnd sufficient charging cannot be achieved.
Referring to fig. 4 and 5, the above problem can be improved by using an external diode and a dummy load, such as the diode D in fig. 4A1Intensifies the OFF time period to the bootstrap capacitance CBOOTCan allow a smaller OFF-time, diode D in fig. 5A1The bootstrap capacitor C can be given during IDEL period of DCM modeBOOTAnd (6) charging. The dummy load resistor R is added in the two schemesdmyThe extreme light load state is avoided and the OFF time is not limited too short, but the above method impairs the light load efficiency.
Therefore, in order to solve the above technical problems, it is necessary to provide an asynchronous buck DCDC chip and a bootstrap circuit based on the asynchronous buck DCDC chip.
Disclosure of Invention
The invention aims to provide an asynchronous step-down DCDC chip and a bootstrap circuit based on the asynchronous step-down DCDC chip, so as to solve the problem that a bootstrap capacitor cannot be charged under the condition of light load.
In order to achieve the above object, an embodiment of the present invention provides the following technical solutions:
the utility model provides an asynchronous step-down DCDC chip, DCDC chip includes input, first output and second output, and the input links to each other with input voltage, and the voltage difference between first output and the second output is VBOOTWherein:
a plurality of first MOS tubes are arranged between the input end and the first output end;
a BOOT reference voltage unit is arranged between the grid electrode of the first MOS tube and the second output end;
and a second MOS tube is arranged between the second output end and the reference potential and is driven by the logic control unit.
In an embodiment, the first MOS transistor is a high-side NMOS transistor, and includes a first high-side NMOS transistor connected to the input terminal and a second high-side NMOS transistor connected to the first output terminal.
In one embodiment, the first high-side NMOS transistor and the second high-side NMOS transistor are respectively connected to the BOOT reference voltage unit, a source of the first high-side NMOS transistor is connected to the input terminal, a drain of the first high-side NMOS transistor is connected to a drain of the second high-side NMOS transistor, and a drain of the second high-side NMOS transistor is connected to the first output terminal.
In an embodiment, a low voltage latch unit is disposed between the first output terminal and the second output terminal, and the low voltage latch unit is configured to monitor a voltage difference V between the first output terminal and the second output terminalBOOTSo as to control the on/off of the first MOS transistor.
In one embodiment, the second MOS transistor includes:
in the first state, when the voltage difference between the input end and the second output end is less than or equal to the preset threshold voltage, the logic control unit drives the second MOS tube to be conducted, and the voltage of the second output end is pulled down to the reference potential;
in the second state, when the voltage difference between the input end and the second output end is greater than the preset threshold voltage, the logic control unit drives the second MOS tube to be cut off.
In one embodiment, the second MOS transistor includes:
third state, voltage difference V between first output terminal and second output terminalBOOTWhen the threshold voltage of the low-voltage latch unit is less than or equal to the threshold voltage of the low-voltage latch unit, the logic control unit drives the second MOS tube to conduct for preset time;
fourth state, voltage difference V between first output terminal and second output terminalBOOTAnd when the voltage is greater than the threshold voltage of the low-voltage latch unit, the logic control unit drives the second MOS tube to be cut off.
In one embodiment, the second output terminal and the second MOS transistor are provided with a first diode, an anode of the first diode is connected to the second output terminal, and a cathode of the first diode is connected to the second MOS transistor.
In one embodiment, the BOOT reference voltage unit includes a first resistor and a second diode connected in series between an input terminal and a reference potential.
The technical scheme provided by another embodiment of the invention is as follows:
a bootstrap circuit based on asynchronous step-down DCDC chip, the bootstrap circuit includes:
an asynchronous buck DCDC chip;
the bootstrap capacitor is connected between the first output end and the second output end of the asynchronous step-down DCDC chip;
the inductor is connected with the second output end of the asynchronous step-down DCDC chip;
and the output capacitor and the load resistor are connected between the inductor and the reference potential after being connected in parallel.
In an embodiment, the bootstrap circuit further includes a third diode, an anode of the third diode is connected to the reference potential, and a cathode of the third diode is connected to the second output terminal of the asynchronous buck DCDC chip.
Compared with the prior art, the invention has the following advantages:
the invention connects the lower end of the BOOT reference voltage unit to the second output endSW solves the problem of bootstrap capacitor C under the condition of light loadBOOTThe problem of incapability of charging;
by controlling the state of the second MOS tube, sufficient voltage space can be provided for the bootstrap capacitor CBOOTCharging, suitable for application condition with low input voltage, and capable of controlling bootstrap capacitor CBOOTThe number of times of charging actions reduces the disturbance to normal operation.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
FIG. 1 is a schematic circuit diagram of a bootstrap circuit based on an asynchronous buck DCDC chip in the prior art;
FIG. 2 is a schematic circuit diagram of a BOOT reference voltage unit in the prior art;
FIGS. 3 a-3 c are waveform diagrams illustrating the operation of a bootstrap circuit in the prior art;
FIG. 4 is a schematic circuit diagram of an external diode and dummy load of the bootstrap circuit;
FIG. 5 is another schematic circuit diagram of the bootstrap circuit with an external diode and dummy load;
FIG. 6 is a schematic circuit diagram of an asynchronous buck DCDC chip according to an embodiment of the present invention;
fig. 7 is a schematic circuit diagram of a bootstrap circuit based on an asynchronous buck DCDC chip according to an embodiment of the present invention.
Detailed Description
The present invention will be described in detail below with reference to embodiments shown in the drawings. The embodiments are not intended to limit the present invention, and structural, methodological, or functional changes made by those skilled in the art according to the embodiments are included in the scope of the present invention.
The invention discloses an asynchronous step-down circuitThe DCDC chip comprises an input end, a first output end and a second output end, wherein the input end is connected with an input voltage, and the voltage difference between the first output end and the second output end is VBOOTWherein:
a plurality of first MOS tubes are arranged between the input end and the first output end;
a BOOT reference voltage unit is arranged between the grid electrode of the first MOS tube and the second output end;
and a second MOS tube is arranged between the second output end and the reference potential and is driven by the logic control unit.
The invention also discloses a bootstrap circuit based on the asynchronous step-down DCDC chip, which comprises:
an asynchronous buck DCDC chip;
the bootstrap capacitor is connected between the first output end and the second output end of the asynchronous step-down DCDC chip;
the inductor is connected with the second output end of the asynchronous step-down DCDC chip;
and the output capacitor and the load resistor are connected between the inductor and the reference potential after being connected in parallel.
The present invention is further illustrated by the following specific examples.
Referring to fig. 6, a schematic circuit diagram of an asynchronous buck DCDC chip according to an embodiment of the invention is shown, the DCDC chip includes an input terminal IN, a first output terminal BOOT, a second output terminal SW, an input terminal and an input voltage VINConnected, the voltage difference between the first output terminal BOOT and the second output terminal SW is VBOOTWherein:
a plurality of first MOS tubes are arranged between the input end IN and the first output end BOOT;
a BOOT reference voltage unit is arranged between the grid of the first MOS tube and the second output end SW;
a second MOS transistor M is arranged between the second output end SW and the reference potential3Second MOS transistor M3Driven by a logic control unit.
IN this embodiment, the first MOS transistor is a high-side NMOS transistor, and includes a first high-side NMOS transistor M connected to the input terminal IN1And a second high connected to the first output terminal BOOTSide NMOS tube M2。
Specifically, the first high side NMOS transistor M1And a second high side NMOS transistor M2Connected with BOOT reference voltage unit, and a first high side NMOS transistor M1Is connected with the input end IN, a first high side NMOS tube M1Drain electrode of and the second high side NMOS transistor M2Is connected with the drain electrode of the second high side NMOS tube M2Is connected to the first output terminal BOOT.
A low-voltage latch unit is arranged between the first output terminal BOOT and the second output terminal SW and is used for monitoring the voltage difference V between the first output terminal and the second output terminal SWBOOTSo as to control the on/off of the first MOS transistor. The low-voltage latch unit is a low-voltage latch circuit commonly used in the prior art, which belongs to the prior art and is not described in detail herein.
In the embodiment, a second MOS transistor M is added between the second output end SW and the reference potential3And is driven by a logic control unit, and the driving principle of the logic control unit is as follows:
when the voltage difference between the input end IN and the second output end SW is less than or equal to the preset threshold voltage, the logic control unit drives the second MOS transistor M3Conducting, and pulling down the voltage of the second output end SW to the reference potential;
when the voltage difference between the input end IN and the second output end SW is larger than the preset threshold voltage, the logic control unit drives the second MOS transistor M3And (6) cutting off.
The driving principle of the logic control unit can also be as follows:
when the voltage difference V between the first output terminal BOOT and the second output terminal SWBOOTWhen the threshold voltage of the logic control unit is less than or equal to the threshold voltage of the low-voltage latch unit, the logic control unit drives the second MOS transistor M3Conducting for a preset time;
when the voltage difference V between the first output terminal BOOT and the second output terminal SWBOOTWhen the threshold voltage of the logic control unit is higher than that of the low-voltage latch unit, the logic control unit drives the second MOS transistor M3And (6) cutting off.
Preferably, in the present embodiment, the second output terminal SW and the second MOS transistor M3Is provided with a first diode D1First diode D1Is connected with the second output terminal SW, and has a cathode D1And a second MOS transistor M3Connected, a first diode D1Can block the backward flow path of the current.
The BOOT reference voltage unit may adopt a circuit configuration as shown IN FIG. 2, including a first resistor R connected IN series between an input terminal IN and a reference potential1And a second diode D2First resistance R1And a second diode D2Voltage N betweenGATEIs a first high side NMOS transistor M1And a second high side NMOS transistor M2The gate driving voltage of (1).
Fig. 7 is a schematic circuit diagram of a bootstrap circuit based on an asynchronous buck DCDC chip according to another embodiment of the present invention, where the bootstrap circuit includes:
the circuit principle of the asynchronous step-down DCDC chip is as described in the above embodiment and fig. 6, and is not described herein again;
bootstrap capacitor CBOOTThe first output end BOOT of the asynchronous buck DCDC chip is connected with the second output end SW;
inductor L0And is connected with the second output end SW of the asynchronous buck DCDC chip;
output capacitor COUTAnd a load resistor RloadAnd connected in parallel between the inductor L0 and a reference potential.
In addition, the bootstrap circuit in this embodiment further includes a third diode D0A third diode D0The anode of the voltage-reducing DCDC chip is connected with the reference potential, and the cathode of the voltage-reducing DCDC chip is connected with the second output end SW of the asynchronous voltage-reducing DCDC chip.
The design principle in this embodiment is specifically as follows:
by connecting the lower end of the BOOT reference voltage unit to the second output terminal SW, the bootstrap circuit can operate as long as the voltage difference between the input terminal IN and the second output terminal SW is large enough (e.g., greater than a certain voltage value), and can be the bootstrap capacitor C IN both the OFF period and the IDEL periodBOOTCharging, i.e. solving the problem of bootstrap capacitance C under light loadBOOTThe problem of incapability of charging;
a second MOS transistor M is added between the second output end SW and the reference potential3When the voltage difference between the input terminal IN and the second output terminal SW is small, the control logic can turn on M3The voltage of the second output terminal SW is pulled down to be close to 0V, and a sufficient voltage space is provided for the bootstrap capacitor CBOOTCharging, adapted to input voltage VINVery low application conditions;
the control logic may also adaptively control M3 to turn on, for example, when the voltage difference V between the first output terminal BOOT and the second output terminal SWBOOTWhen the threshold voltage of the low-voltage latch unit is less than or equal to the threshold voltage of the low-voltage latch unit, M is conducted3Time of one switching cycle, VBOOTWhen the voltage is above the threshold voltage of the low-voltage latch unit3The cut-off is maintained. Thus bootstrap capacitor CBOOTThe charging action is as few as possible, and the disturbance to the normal work is reduced.
By being provided withThe technical scheme shows that the invention has the following beneficial effects:
the invention solves the problem of bootstrap capacitor C under the condition of light load by connecting the lower end of the BOOT reference voltage unit to the second output end SWBOOTThe problem of incapability of charging;
by controlling the state of the second MOS tube, sufficient voltage space can be provided for the bootstrap capacitor CBOOTCharging, suitable for application condition with low input voltage, and capable of controlling bootstrap capacitor CBOOTThe number of times of charging actions reduces the disturbance to normal operation.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are therefore to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be combined as appropriate to form other embodiments understood by those skilled in the art.

Claims (10)

1. The asynchronous step-down DCDC chip is characterized by comprising an input end, a first output end and a second output end, wherein the input end is connected with an input voltage, and the voltage difference between the first output end and the second output end is VBOOTWherein:
a plurality of first MOS tubes are arranged between the input end and the first output end;
a BOOT reference voltage unit is arranged between the grid electrode of the first MOS tube and the second output end;
and a second MOS tube is arranged between the second output end and the reference potential and is driven by the logic control unit.
2. The asynchronous buck DCDC chip of claim 1, wherein the first MOS transistor is a high side NMOS transistor, and comprises a first high side NMOS transistor connected to the input terminal and a second high side NMOS transistor connected to the first output terminal.
3. The asynchronous buck DCDC chip of claim 2, wherein the first high side NMOS transistor and the second high side NMOS transistor are respectively connected to a BOOT reference voltage unit, a source of the first high side NMOS transistor is connected to the input terminal, a drain of the first high side NMOS transistor is connected to a drain of the second high side NMOS transistor, and a drain of the second high side NMOS transistor is connected to the first output terminal.
4. The asynchronous buck DCDC chip of claim 1, wherein one of said first and second output terminalsA low-voltage latch unit for monitoring the voltage difference between the first output terminal and the second output terminalBOOTSo as to control the on/off of the first MOS transistor.
5. The asynchronous buck DCDC chip of claim 1, wherein the second MOS transistor comprises:
in the first state, when the voltage difference between the input end and the second output end is less than or equal to the preset threshold voltage, the logic control unit drives the second MOS tube to be conducted, and the voltage of the second output end is pulled down to the reference potential;
in the second state, when the voltage difference between the input end and the second output end is greater than the preset threshold voltage, the logic control unit drives the second MOS tube to be cut off.
6. The asynchronous buck DCDC chip of claim 4, wherein the second MOS transistor comprises:
third state, voltage difference V between first output terminal and second output terminalBOOTWhen the threshold voltage of the low-voltage latch unit is less than or equal to the threshold voltage of the low-voltage latch unit, the logic control unit drives the second MOS tube to conduct for preset time;
fourth state, voltage difference V between first output terminal and second output terminalBOOTAnd when the voltage is greater than the threshold voltage of the low-voltage latch unit, the logic control unit drives the second MOS tube to be cut off.
7. The asynchronous buck DCDC chip of claim 1, wherein the second output terminal and the second MOS transistor are provided with a first diode, the anode of the first diode is connected to the second output terminal, and the cathode of the first diode is connected to the second MOS transistor.
8. The asynchronous buck DCDC chip of claim 1, wherein the BOOT reference voltage unit comprises a first resistor and a second diode connected in series between an input terminal and a reference potential.
9. A bootstrap circuit based on asynchronous step-down DCDC chip, characterized in that, the bootstrap circuit includes:
the asynchronous buck DCDC chip of any one of claims 1 to 8;
the bootstrap capacitor is connected between the first output end and the second output end of the asynchronous step-down DCDC chip;
the inductor is connected with the second output end of the asynchronous step-down DCDC chip;
and the output capacitor and the load resistor are connected between the inductor and the reference potential after being connected in parallel.
10. The asynchronous buck DCDC chip-based bootstrap circuit of claim 9, characterized in that, said bootstrap circuit further includes a third diode, an anode of the third diode is connected to a reference potential, and a cathode thereof is connected to the second output terminal of the asynchronous buck DCDC chip.
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Cited By (2)

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CN115882727A (en) * 2023-02-10 2023-03-31 禹创半导体(深圳)有限公司 Step-down converter and power chip
CN117155126A (en) * 2023-03-14 2023-12-01 荣耀终端有限公司 Terminal device and control method

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CN102098030A (en) * 2009-12-09 2011-06-15 罗姆股份有限公司 Semiconductor device and switching regulator using the device
CN103199689A (en) * 2013-04-18 2013-07-10 电子科技大学 Switch power supply with input voltage undervoltage locking function
CN108494234A (en) * 2018-04-09 2018-09-04 电子科技大学 Floating power supply rail suitable for GaN high speed gate drive circuits

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Publication number Priority date Publication date Assignee Title
US20080100378A1 (en) * 2006-10-30 2008-05-01 Infineon Technologies Austria Ag Circuits and methods for controlling a switch
CN102098030A (en) * 2009-12-09 2011-06-15 罗姆股份有限公司 Semiconductor device and switching regulator using the device
CN103199689A (en) * 2013-04-18 2013-07-10 电子科技大学 Switch power supply with input voltage undervoltage locking function
CN108494234A (en) * 2018-04-09 2018-09-04 电子科技大学 Floating power supply rail suitable for GaN high speed gate drive circuits

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Publication number Priority date Publication date Assignee Title
CN115882727A (en) * 2023-02-10 2023-03-31 禹创半导体(深圳)有限公司 Step-down converter and power chip
CN117155126A (en) * 2023-03-14 2023-12-01 荣耀终端有限公司 Terminal device and control method
CN117155126B (en) * 2023-03-14 2024-06-25 荣耀终端有限公司 Terminal device and control method

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