CN110971341B

CN110971341B - DBPL code hardware decoding method and system

Info

Publication number: CN110971341B
Application number: CN201911039086.8A
Authority: CN
Inventors: 武方达; 倪园慧; 靳旭; 马盼; 谷荧柯; 任军
Original assignee: CRSC Research and Design Institute Group Co Ltd
Current assignee: CRSC Research and Design Institute Group Co Ltd
Priority date: 2019-10-29
Filing date: 2019-10-29
Publication date: 2022-09-09
Anticipated expiration: 2039-10-29
Also published as: CN110971341A

Abstract

The invention relates to a DBPL code hardware decoding method and a system, wherein the decoding method comprises the following steps: delaying an original DBPL code to obtain a delayed DBPL code, performing XOR operation to output a DBPL code edge pulse signal, triggering a monostable circuit to output a square wave with the same frequency as the DBPL code, and outputting decoding data synchronous with the DBPL code; a DBPL code hardware decoding system, the decoding system comprising: the device comprises an input module, a Schmitt trigger, an exclusive-OR gate, a monostable trigger and a D trigger. According to the DBPL code hardware decoding method and system, the 3D triggers are arranged to carry out monostable signal conversion, decoding data synchronous with the DBPL code are generated, an external clock source is not needed, the decoding output signal and the DBPL code input signal can be guaranteed to be strictly synchronous, and the reliability of a decoding system is improved.

Description

DBPL code hardware decoding method and system

Technical Field

The invention belongs to the field of rail transit communication signals, and particularly relates to a DBPL code hardware decoding method and system.

Background

In order to ensure the railway transportation safety of China, meet the demand of intercommunication operation and adapt to the implementation of the development strategy of railway construction, a railway head office issues the technical specification of a China train operation control system (CTCS), wherein CTCS-1, CTCS-2 and CTCS-3 grades all clearly require that a point type responder is arranged on the ground, and a query device (BTM) is arranged on a locomotive. The transponder system becomes an indispensable important device for railway reconstruction and construction in China.

The active transponder is an important component of a transponder system and transmits real-time ground information to the vehicle-mounted equipment through an air interface. The active transponder is connected to a ground electronic unit (LEU) via a pair of transponder-specific shielded twisted pair cables, the signals transmitted in the cables are 8.82kHz sinusoidal signals with DBPL encoded data superimposed thereon, 8.82kHz is used for energy extraction by the active transponder hardware circuits, and the DBPL encoded data is subjected to message decoding to output a variable message.

Differential biphase coding (DBPL code) is a digital coding method widely adopted in the field of rail transit communication signals. In an active transponder, a variable message is communicated with a ground electronic unit (LEU) to the vehicle equipment via the DBPL code. After receiving the DBPL code sent by the LEU, the active responder needs to decode the DBPL code, the traditional DBPL code decoding mode is based on an MCU or an FPGA at present, the complexity of a traditional DBPL code decoding system is high, an external clock source is needed, and the reliability is reduced in a severe environment.

Disclosure of Invention

Aiming at the problems, the invention provides a DBPL code hardware decoding method and system.

A DBPL code hardware decoding method, the decoding method comprises the following steps:

delaying an original DBPL code to obtain a delayed DBPL code, carrying out XOR operation on the original DBPL code and the delayed DBPL code, and outputting a DBPL code edge pulse signal;

the monostable circuit triggers the edge pulse signal of the DBPL code and outputs square waves with the same frequency as the DBPL code;

and triggering and converting the decoded data synchronized with the DBPL code through the DBPL code edge pulse signal and the DBPL code same-frequency square wave.

Further, the obtaining of the DBPL code edge pulse signal is:

and converting the rising edge or the falling edge of the original DBPL code and the delayed DBPL code into pulse signals, and extracting the DBPL code edge pulse signals.

Further, the DBPL code co-frequency square wave comprises a DBPL code co-frequency positive-phase square wave and a DBPL co-frequency inverse square wave.

Further, the generating a DBPL code co-frequency square wave comprises:

setting a transient steady-state time of the monostable circuit;

the falling edge of the DBPL code edge pulse signal triggers a monostable trigger to enter a transient steady state, the monostable trigger is not triggered again within the transient steady state time, and the falling edge of the DBPL code edge pulse signal triggers the monostable trigger again to enter the transient steady state after the monostable trigger enters the steady state;

the monostable trigger outputs the DBPL code same-frequency normal-phase square wave in a normal phase according to the transient steady trigger frequency, and the monostable trigger outputs the DBPL code same-frequency reverse-phase square wave in a reverse phase according to the transient steady trigger frequency.

Further, the transient steady time is between half a symbol period and one symbol period.

Further, outputting decoded data synchronized with the DBPL code by triggering a transform with the DBPL code co-frequency square wave through the DBPL code edge pulse signal comprises:

outputting a first output signal through a positive-phase square wave in the DBPL code edge pulse signal and the DBPL code same-frequency square wave, wherein the first output signal is logic '1' in the original DBPL code;

outputting a second output signal through an inverted square wave in the DBPL code same-frequency square wave and the first output signal, wherein the second output signal is decoded data of the original DBPL code;

and outputting a third output signal through the DBPL code edge pulse signal and the second output signal, wherein the third output signal is decoded data of the original DBPL code edge which is strictly synchronous.

A DBPL code hardware decoding system, the decoding system comprising:

the input module is used for inputting an original DBPL code and transmitting the original DBPL code;

the Schmitt trigger is used for receiving the original DBPL code, carrying out delay processing on the original DBPL code and outputting a delayed DBPL code;

an exclusive-or gate, configured to perform an exclusive-or operation on the original DBPL code and the delayed DBPL code, and output a DBPL code edge pulse signal;

the monostable trigger is used for receiving the DBPL code edge pulse signal and generating a square wave with the same frequency as the original DBPL code;

and the D flip-flop is used for receiving the positive and negative phase square waves with the same frequency as the DBPL code and the DBPL code edge pulse signals and generating decoding data synchronous with the DBPL code.

Further, the decoding system includes:

and the XOR gate converts the rising edge or the falling edge of the original DBPL code and the delayed DBPL code into a DBPL code edge pulse signal for outputting.

Further, the D flip-flop is set to be not less than two.

Further, the D flip-flop is provided with three, which are: a first D flip-flop, a second D flip-flop and a third D flip-flop;

the first D flip-flop is used for generating a first output signal according to pulse signals at the edges of a positive-phase square wave and the DBPL code in the DBPL code same-frequency square wave;

the second D flip-flop is used for generating a second output signal according to the first output signal and an inverted square wave in the DBPL code same-frequency square wave;

the third D flip-flop is used for generating a third output signal according to the second output signal and the DBPL code edge pulse signal.

Further, the edge pulse signal of the DBPL code is used as a first clock signal of the first D flip-flop, and the positive-phase square wave in the DBPL code same-frequency square wave is a first data signal D of the first D flip-flop.

Further, an inverted square wave in the DBPL code same-frequency square wave serves as a second clock signal of the second D flip-flop, and the first output signal serves as a second data signal D.

Further, the DBPL code edge pulse signal serves as a third clock signal of a third D flip-flop, and the second output signal serves as a third data signal D of the third D flip-flop.

According to the DBPL code hardware decoding method and system, the 3D triggers are arranged to carry out monostable signal conversion, decoding data synchronous with the DBPL code are generated, an external clock source is not needed, the decoding output signal and the DBPL code input signal can be guaranteed to be strictly synchronous, and the reliability of a decoding system is improved.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.

FIG. 1 is a flowchart illustrating a DBPL code hardware decoding method according to an embodiment of the present invention;

FIG. 2 shows a timing diagram for extracting DBPL code edge pulses according to an embodiment of the invention;

FIG. 3 shows a timing diagram for generating a normal phase, inverted square wave at the same frequency as the DBPL code, in accordance with an embodiment of the present invention;

FIG. 4 shows a timing diagram for extracting a logic "1" in a DBPL code, in accordance with embodiments of the present invention;

FIG. 5 illustrates a timing diagram for generating decoded data according to an embodiment of the present invention;

FIG. 6 shows a timing diagram for adjusting decoded data to be strictly synchronized with the original DBPL code, in accordance with an embodiment of the present invention;

fig. 7 shows a schematic structural diagram of a DBPL code hardware decoding system according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

A hardware decoding method of a DBPL code, as shown in fig. 1, the decoding method includes the following steps:

the method comprises the following steps: and delaying the original DBPL code, and performing XOR operation on the original DBPL code and the delayed DBPL code to obtain a DBPL code edge pulse signal.

The original DBPL code carries out delay change on the original DBPL code through a monostable trigger, namely, in the process of inputting the original DBPL code, a delay area is formed due to the arrangement inside the monostable trigger circuit, so that the output DBPL code has certain delay, and the delayed DBPL code is obtained.

And after the DBPL code in the delay state is output, carrying out XOR operation with the original DBPL code, converting the rising edge and the falling edge of the DBPL code into pulse signals, realizing extraction and integration of the DBPL code edge, and obtaining the edge pulse signal of the DBPL code.

Illustratively, as shown in fig. 2, after the original DBPL code is inputted into the one-shot flip-flop, the flip-flop delays the original DBPL code, and the delayed DBPL code has the same shape and frequency as the original DBPL code, but the waveform is shifted. After the first waveform of the original DBPL code is input, due to the existence of a monostable trigger lag zone, the output first waveform time is delayed compared with the appearance time of the first waveform of the original DBPL code, and then the appearance time of each waveform is delayed by the same time, but the interval between the delayed DBPL code waveforms is not changed.

And then performing XOR operation on the delayed DBPL code and the original DBPL code: the same portion of the delayed DBPL code waveform as the original DBPL code waveform is output as 1, and the different portion is output as 0, where a pulse signal is formed due to the difference between the rising and falling edges of the delayed DBPL code and the original DBPL code. The time of the single pulse signal is the beginning of the falling edge or rising edge of the original DBPL code and the end of the falling edge or rising edge of the delayed DBPL code. And converting a plurality of rising edges and falling edges of the delayed DBPL code and the original DBPL code into continuous pulse signals, and finally forming an exclusive-OR gate output edge pulse signal.

Step two: and performing monostable circuit triggering on the DBPL code edge pulse signal, and outputting a square wave with the same frequency as the DBPL code.

The DBPL code same-frequency square wave comprises a DBPL code same-frequency positive-phase square wave and a DBPL code same-frequency negative-phase square wave.

The edge pulse signal of the DBPL code is input into a monostable circuit, the monostable circuit is triggered by an external signal, the circuit is turned over from a steady state to a transient state, and after a period of time, the circuit automatically returns to the steady state. The transient steady state time of the monostable circuit is set between half code element period and one code element period, and the falling edge of the edge pulse signal triggers the monostable circuit to be transient steady state and can not be triggered again.

Illustratively, if the time of three consecutive edge pulses corresponds to half a symbol period, i.e., for a signal of three edge pulses whose time interval is half a symbol period. The falling edge of the first edge pulse signal triggers the monostable trigger to enter a transient steady state and output high level, and because the transient steady state time is more than half of a code element period, when the falling edge of the second edge pulse signal arrives, the monostable trigger is in the transient steady state and can not be triggered again, and at the moment, the falling edge of the edge pulse signal has no influence on the monostable trigger. The monostable of the monostable flip-flop ends in one symbol period, outputting a low level. When the falling edge of the third edge pulse signal comes, the monostable trigger is in a steady state, the monostable trigger is triggered to enter a transient steady state, a high level is output, and the like.

For two edge pulse signals with the time interval of one code element period, the falling edge of the first edge pulse signal triggers the monostable trigger to enter a transient steady state and output high level. The monostable of the monostable flip-flop ends in one symbol period, outputting a low level. When the falling edge of the second edge pulse signal comes, the monostable trigger is in a steady state, the monostable trigger is triggered to enter a transient steady state, a high level is output, and the like.

In the process of inputting the DBPL code, the frequency of the DBPL code is automatically recorded, the monostable trigger can receive the frequency of the DBPL code, the monostable trigger outputs the DBPL code same-frequency normal-phase square wave according to the tentative steady trigger frequency in a normal phase mode, and the monostable trigger outputs the DBPL code same-frequency reverse-phase square wave according to the tentative steady trigger frequency in a reverse phase mode. Thereby generating a square wave having the same frequency as the DBPL code.

Illustratively, as shown in fig. 3, the output edge pulse signal of the xor gate in fig. 2 is input into a monostable flip-flop, and the falling edge of the edge pulse signal is used for triggering, the pause time is between half a symbol period and one symbol period, and the symbol period is set to 564.48 kHz. The explanation will be given by assuming that an edge pulse signal marked 1 in the figure is a first edge pulse signal, and second, third, fourth, and the like edge pulse signals are sequentially provided in the right direction.

The falling edge of the first edge pulse signal triggers the monostable trigger to enter a transient steady state, when the second edge pulse signal is input, the monostable trigger is in the transient steady state and can not be triggered repeatedly, the monostable trigger continuously keeps the transient steady state and can not be triggered again, and after the code element period, the monostable trigger is recovered to the steady state. Then the falling edge of the third edge pulse signal input continuously triggers the monostable trigger to enter a transient steady state, the fourth edge pulse signal input continuously locates in the code element period, and then the monostable trigger restores to the steady state. When the fifth edge pulse signal is input, the transient state is triggered again, no signal is input in the code element period, and when the sixth edge pulse signal is input, a new code element period is carried out, so that the monostable trigger outputs a square wave, and the length of the square wave is one code element period.

After the output edge pulse signal of the exclusive-or gate in fig. 3 is input, the monostable flip-flop outputs a positive phase 564.48kHz square wave in a positive phase, and simultaneously, the monostable flip-flop outputs a negative phase 564.48kHz square wave in a negative phase.

And step three, triggering and converting by the edge pulse signal and the DBPL code same-frequency square wave to generate decoding data synchronous with the DBPL code.

The method comprises the following steps: 1. acquiring logic '1' in the original DBPL code through a positive phase square wave of which the edge pulse signal has the same frequency as the DBPL code;

specifically, the edge pulse signal is used as a first clock signal, and the positive-phase square wave is used as a first data signal D. After the first clock signal and the first data signal D are input, the rising edge of the edge pulse signal is obtained, meanwhile, the normal phase square wave level is collected, and a first output signal is output. The high level pulse in the first output signal is the logic "1" extracted from the DBPL code.

For example, as shown in fig. 4, the xor gate in fig. 3 outputs an edge pulse signal as the first clock signal CLK, and the monostable flip-flop in fig. 3 outputs a positive phase 564.48kHz square wave as the first data signal D. Acquiring the rising edge of an edge pulse signal, and acquiring the level of a normal-phase square wave: the rising edge of the edge pulse signal is output from the exclusive-OR gate to the rising edge of the next adjacent pulse signal by taking the wave level of the rising edge of the edge pulse signal as the output level, so that a first output signal is formed. And so on, a plurality of continuous first output signals Dout1 are formed, and the high level pulse in the first output signals is the logic "1" extracted from the DBPL code.

2. Acquiring decoded data of an original DBPL code through an inverted square wave with the same frequency of the DBPL code and a first output signal;

specifically, the inverted square wave is used as the second clock signal, and the first output signal is used as the second data signal D. And after a second clock signal and a second data signal D are input, acquiring the rising edge of the reversed-phase square wave, acquiring the high level of the second data signal D, and outputting a second output signal. The obtained second output signal is the decoded data of the original DBPL code, and because the trigger signal of each data of the second output signal is the rising edge of the inverted square wave, the frequency of the inverted square wave is synchronous with the original DBPL code, i.e., the period is one symbol period, so the holding time of each symbol of the second output signal is 1 symbol period.

For example, as shown in fig. 5, the inverted output of the monostable flip-flop in fig. 3 is an inverted 564.48kHz square wave as the second clock signal CLK, and the first output signal Dout1 in fig. 4 is the second data signal D. The rising edge of the inverted square wave is taken and the high level of Dout1 is collected: the level of the first output signal Dout1 at the rising edge of the inverted square wave is taken as the output level, and a second output signal is formed from the rising edge of the inverted square wave to the rising edge of the next adjacent inverted square wave. By analogy, a plurality of consecutive second output signals Dout2 are formed, the second output signals Dout2 being obtained by inverting a square wave as a second clock signal, each symbol of the second output signals Dout2 remaining 1 symbol period synchronized with the original DBPL code.

3. Acquiring decoding data strictly synchronous with the edge of the original DBPL code through the edge pulse signal and the second output signal;

the waveform edge of the DBPL code decoding output data needs to be synchronous with the original DBPL code, if the waveform edge is asynchronous, vehicle-mounted equipment can receive error codes or disordered codes, and the accuracy and the integrity of a decoded message need to be strictly ensured.

Specifically, the edge pulse signal in the first step is used as a third clock signal CLK, the second output signal is used as a third data signal D, and after the third clock signal and the third data signal D are input, the level of the third data signal D is acquired by using the rising edge of the edge pulse signal, and the third output signal is output, so that the strict synchronization between the edge of the third output signal and the edge of the original DBPL code is realized. The third output signal is the decoded data that is strictly synchronized with the edge of the original DBPL code and finally output by the DBPL code hardware decoding method of this embodiment.

For example, as shown in fig. 6, the xor gate outputs an edge pulse signal in fig. 2 as the third clock signal CLK, the second output signal Dout2 in fig. 4 is used as the third data signal D, the high level of the third data signal D is collected, and the rising edge of the edge pulse signal is output to the rising edge of the next adjacent pulse signal from the xor gate by using the level of the second output signal Dout2 at the rising edge of the edge pulse signal as the output level, so as to form a third output signal. And so on, a plurality of successive third output signals Dout3 are output. The third output signal Dout3 is the decoded data that is exactly synchronized with the original DBPL code edge.

The DBPL code hardware decoding method can effectively solve the problem that variable messages are output by DBPL decoding, has simple steps, outputs decoding data strictly synchronous with the edge of the original DBPL code, and ensures that the message data is accurate and complete.

The invention also relates to a DBPL code hardware decoding system, which comprises an input module, a Schmitt trigger, an exclusive-OR gate, a monostable trigger and a D trigger, as shown in figure 7.

And the input module is used for inputting the original DBPL code and transmitting the original DBPL code to the system internal module.

The Schmitt trigger is connected with the input module and is used for receiving the original DBPL code, carrying out delay processing on the original DBPL code and outputting the delayed DBPL code.

Specifically, the schmitt trigger delays the appearance time of the first waveform input in the original DBPL code, the waveform interval time is not changed, the shape of the whole original DBPL code is not changed, and the whole delay of the original DBPL code is realized.

The exclusive-or gate is connected with the input module and is connected with the Schmitt trigger. And the exclusive-OR gate is used for receiving the original DBPL code and the delayed DBPL code, performing exclusive-OR operation on the original DBPL code and the delayed DBPL code and outputting a DBPL code edge pulse signal.

Specifically, after receiving an original DBPL code and a delayed DBPL code, the XOR gate aligns the input starting points of the original DBPL code and the delayed DBPL code, outputs the same part of the delayed DBPL code waveform and the original DBPL code waveform as 1, and outputs different parts of the delayed DBPL code waveform as 0, so that pulse signal output is formed. Because the rising edge and the falling edge of the delayed DBPL code and the original DBPL code are arranged in a staggered mode to form a pulse signal, the pulse signal output by the exclusive-OR gate is an edge pulse signal of the DBPL code.

The monostable flip-flop is connected with the exclusive-or gate and used for receiving a DBPL code edge pulse signal output by the exclusive-or gate and generating a square wave with the same frequency as the original DBPL code.

Specifically, after the monostable flip-flop receives the DBPL code edge pulse signal output by the xor gate, the falling edge of the DBPL code edge pulse signal triggers the monostable flip-flop to enter a transient steady state, and after the transient steady state time is over, the monostable flip-flop enters a steady state. In a transient steady state condition, the monostable cannot be retriggered.

Furthermore, the transient state time is between half a symbol period and one symbol period, i.e. the falling edge of the pulse signal of other edges in the period can not trigger the transient state again.

The monostable circuit generates a square wave with the same frequency as the original DBPL code according to the change of the monostable-steady-state-transient-steady-state.

The D flip-flop is connected with the monostable flip-flop, is also connected with the exclusive-OR gate, and is used for receiving positive and negative square waves with the same frequency of the edge pulse signal and the DBPL code and generating decoding data synchronous with the DBPL code.

In order to ensure the accuracy and the integrity of the decoded data, a plurality of D triggers can be arranged, and the D triggers process the positive and negative phase square waves with the same frequency of the edge pulse signals and the DBPL codes in different classes and multiple layers. Therefore, the number of D flip-flops is not less than 2.

Specifically, in the implementation of the present invention, 3D flip-flops are provided, which are respectively a first D flip-flop, a second D flip-flop, and a third D flip-flop.

The first D flip-flop is used for generating a first output signal according to the DBPL code same-frequency positive-phase square wave and the edge pulse signal. The edge pulse signal is used as a first clock signal (CLK signal) of the first D flip-flop, and the positive-phase square wave is used as a first data signal D of the first D flip-flop. The first D flip-flop is triggered by the rising edge of the edge pulse signal, collects the level of the positive-phase square wave, and outputs a first output signal Dout 1. The high pulse in the Dout1 signal is the logic "1" extracted from the DBPL code.

The second D flip-flop is configured to generate a second output signal according to the first output signal Dout1 and the inverse square wave with the same frequency as the DBPL code. The inverted square wave of the same frequency as the DBPL code is used as the CLK signal as the second clock signal of the second D flip-flop, and the Dout1 signal is used as the D signal as the second data signal of the second D flip-flop. The second D flip-flop is triggered by the rising edge of the inverted square wave, collects the level of the Dout1 signal and outputs a second output signal Dout 2. The Dout2 signal is the decoded data of the original DBPL code.

The third D flip-flop is configured to generate a second output signal according to the second output signal Dout2 and the edge pulse signal.

Further, the edge pulse signal serves as a third clock signal, i.e., the CLK signal, of the third D flip-flop, and the Dout2 signal serves as a third data signal D of the third D flip-flop. The third D flip-flop 3 uses the rising edge trigger of the edge pulse signal to acquire the level of the Dout2 signal and output a third output signal Dout 3. The edge of the third output signal Dout3 is strictly synchronized with the edge of the original DBPL code, and the obtained Dout3 signal is the decoded data which is finally output by the DBPL code hardware decoding method and is strictly synchronized with the edge of the original DBPL code.

According to the DBPL code hardware decoding system, the D trigger is arranged to output decoding data strictly synchronous with the original DBPL code edge, an external clock circuit, a phase-locked loop circuit and an FPGA (field programmable gate array) are not required to be arranged, the production cost of the hardware decoding system is effectively reduced, the structure is simple, and the running reliability of the system is effectively guaranteed.

Although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims

1. A DBPL code hardware decoding method is characterized by comprising the following steps:

the monostable circuit triggers the edge pulse signal of the DBPL code and outputs a square wave with the same frequency as the DBPL code;

outputting decoded data synchronized with the DBPL code through the triggering and converting of the DBPL code edge pulse signal and the DBPL code co-frequency square wave, comprising: outputting a first output signal through a positive-phase square wave in the DBPL code edge pulse signal and the DBPL code same-frequency square wave, wherein the first output signal is logic '1' in the original DBPL code; outputting a second output signal through an inverted square wave in the DBPL code same-frequency square wave and the first output signal, wherein the second output signal is decoded data of the original DBPL code; and outputting a third output signal through the DBPL code edge pulse signal and the second output signal, wherein the third output signal is decoded data synchronized with the original DBPL code edge.

2. The decoding method of claim 1, wherein the output DBPL code edge pulse signal is:

and converting rising edges or falling edges of the original DBPL code and the delayed DBPL code into pulse signals, and extracting the DBPL code edge pulse signals.

3. The decoding method of claim 1, wherein the DBPL code co-frequency square wave comprises a DBPL code co-frequency positive-phase square wave and a DBPL co-frequency inverse square wave.

4. The decoding method according to claim 1 or 3, wherein outputting a square wave having the same frequency as the DBPL code comprises:

setting a transient steady-state time of the monostable circuit;

the monostable trigger outputs a DBPL code co-frequency normal phase square wave in a normal phase according to the transient steady state trigger frequency, and the monostable trigger outputs a DBPL code co-frequency reverse phase square wave in a reverse phase according to the transient steady state trigger frequency.

5. The decoding method of claim 4, wherein the transient time is between half a symbol period and one symbol period.

6. A hardware decoding system for DBPL code, the decoding system comprising:

the exclusive-OR gate is used for carrying out exclusive-OR operation on the original DBPL code and the delayed DBPL code and outputting a DBPL code edge pulse signal;

the D flip-flop is used for receiving positive and negative square waves with the same frequency as the DBPL code and generating decoding data synchronous with the DBPL code;

the D trigger is provided with three, is respectively: a first D flip-flop, a second D flip-flop and a third D flip-flop;

7. The decoding system of claim 6, wherein the decoding system comprises:

8. The decoding system of claim 6 or 7, wherein the D flip-flop setting is no less than two.

9. The decoding system of claim 6, wherein the edge pulse signal of the DBPL code is used as a first clock signal of the first D flip-flop, and the positive-phase square wave of the DBPL code co-frequency square wave is a first data signal D of the first D flip-flop.

10. The decoding system of claim 6, wherein an inverted square wave of the DBPL-code co-frequency square wave is used as the second D flip-flop second clock signal, and the first output signal is used as the second data signal D.

11. The decoding system of claim 6, wherein the DBPL code edge pulse signal serves as a third clock signal for a third D flip-flop, and the second output signal serves as a third data signal D for the third D flip-flop.